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developer7305b4c2020-04-21 09:28:49 +02001/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) 2020 MediaTek Inc.
4 *
5 * Author: Weijie Gao <weijie.gao@mediatek.com>
6 */
7
8#ifndef __CONFIG_MT7628_H
9#define __CONFIG_MT7628_H
10
developer7305b4c2020-04-21 09:28:49 +020011#define CONFIG_SYS_SDRAM_BASE 0x80000000
developer7305b4c2020-04-21 09:28:49 +020012
13#define CONFIG_SYS_INIT_SP_OFFSET 0x80000
14
developer7305b4c2020-04-21 09:28:49 +020015/* Serial SPL */
Simon Glassf4d60392021-08-08 12:20:12 -060016#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL)
developer7305b4c2020-04-21 09:28:49 +020017#define CONFIG_SYS_NS16550_MEM32
18#define CONFIG_SYS_NS16550_CLK 40000000
19#define CONFIG_SYS_NS16550_REG_SIZE -4
20#define CONFIG_SYS_NS16550_COM1 0xb0000c00
developer7305b4c2020-04-21 09:28:49 +020021#endif
22
23/* Serial common */
24#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \
25 230400, 460800, 921600 }
26
27/* SPL */
developer7305b4c2020-04-21 09:28:49 +020028
Simon Glass72cc5382022-10-20 18:22:39 -060029#define CONFIG_SYS_UBOOT_START CONFIG_TEXT_BASE
developer7305b4c2020-04-21 09:28:49 +020030
31/* Dummy value */
32#define CONFIG_SYS_UBOOT_BASE 0
33
34#endif /* __CONFIG_MT7628_H */