blob: 002698b501c3002026941bbc812bc0123043132b [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
David Feng85fd5f12013-12-14 11:47:35 +08002/*
3 * (C) Copyright 2013
4 * David Feng <fenghua@phytium.com.cn>
David Feng85fd5f12013-12-14 11:47:35 +08005 */
6
7#include <asm-offsets.h>
8#include <config.h>
David Feng85fd5f12013-12-14 11:47:35 +08009#include <linux/linkage.h>
10#include <asm/macro.h>
11#include <asm/armv8/mmu.h>
12
13/*************************************************************************
14 *
15 * Startup Code (reset vector)
16 *
17 *************************************************************************/
18
19.globl _start
20_start:
Mian Yousaf Kaukaba0dcfc52019-06-13 14:46:44 +020021#if defined(CONFIG_LINUX_KERNEL_IMAGE_HEADER)
Stephen Warren80a93652018-01-03 14:31:51 -070022#include <asm/boot0-linux-kernel-header.h>
23#elif defined(CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK)
Andre Przywara48321ba2016-05-31 10:45:06 -070024/*
25 * Various SoCs need something special and SoC-specific up front in
26 * order to boot, allow them to set that in their boot0.h file and then
27 * use it here.
28 */
29#include <asm/arch/boot0.h>
Andre Przywara313a5782017-01-02 11:48:33 +000030#else
31 b reset
Andre Przywara48321ba2016-05-31 10:45:06 -070032#endif
33
David Feng85fd5f12013-12-14 11:47:35 +080034 .align 3
35
36.globl _TEXT_BASE
37_TEXT_BASE:
38 .quad CONFIG_SYS_TEXT_BASE
39
40/*
41 * These are defined in the linker script.
42 */
43.globl _end_ofs
44_end_ofs:
45 .quad _end - _start
46
47.globl _bss_start_ofs
48_bss_start_ofs:
49 .quad __bss_start - _start
50
51.globl _bss_end_ofs
52_bss_end_ofs:
53 .quad __bss_end - _start
54
55reset:
Stephen Warren100a4792016-07-18 17:01:50 -060056 /* Allow the board to save important registers */
57 b save_boot_params
58.globl save_boot_params_ret
59save_boot_params_ret:
60
Stephen Warren81c21372017-11-02 18:11:27 -060061#if CONFIG_POSITION_INDEPENDENT
62 /*
63 * Fix .rela.dyn relocations. This allows U-Boot to be loaded to and
64 * executed at a different address than it was linked at.
65 */
66pie_fixup:
67 adr x0, _start /* x0 <- Runtime value of _start */
68 ldr x1, _TEXT_BASE /* x1 <- Linked value of _start */
69 sub x9, x0, x1 /* x9 <- Run-vs-link offset */
70 adr x2, __rel_dyn_start /* x2 <- Runtime &__rel_dyn_start */
71 adr x3, __rel_dyn_end /* x3 <- Runtime &__rel_dyn_end */
72pie_fix_loop:
73 ldp x0, x1, [x2], #16 /* (x0, x1) <- (Link location, fixup) */
74 ldr x4, [x2], #8 /* x4 <- addend */
75 cmp w1, #1027 /* relative fixup? */
76 bne pie_skip_reloc
77 /* relative fix: store addend plus offset at dest location */
78 add x0, x0, x9
79 add x4, x4, x9
80 str x4, [x0]
81pie_skip_reloc:
82 cmp x2, x3
83 b.lo pie_fix_loop
84pie_fixup_done:
85#endif
86
Sergey Temerkhanov78eaa492015-10-14 09:55:45 -070087#ifdef CONFIG_SYS_RESET_SCTRL
88 bl reset_sctrl
89#endif
Andre Przywara4eecab72018-07-25 00:57:01 +010090
Alexander Grafb3e9dc62019-02-20 17:14:49 +010091#if defined(CONFIG_ARMV8_SPL_EXCEPTION_VECTORS) || !defined(CONFIG_SPL_BUILD)
Andre Przywara4eecab72018-07-25 00:57:01 +010092.macro set_vbar, regname, reg
93 msr \regname, \reg
94.endm
95 adr x0, vectors
96#else
97.macro set_vbar, regname, reg
98.endm
99#endif
David Feng85fd5f12013-12-14 11:47:35 +0800100 /*
101 * Could be EL3/EL2/EL1, Initial State:
102 * Little Endian, MMU Disabled, i/dCache Disabled
103 */
David Feng85fd5f12013-12-14 11:47:35 +0800104 switch_el x1, 3f, 2f, 1f
Andre Przywara4eecab72018-07-25 00:57:01 +01001053: set_vbar vbar_el3, x0
David Feng7c5eca72014-04-19 09:45:21 +0800106 mrs x0, scr_el3
David Feng79bbde02014-03-14 14:26:27 +0800107 orr x0, x0, #0xf /* SCR_EL3.NS|IRQ|FIQ|EA */
108 msr scr_el3, x0
David Feng85fd5f12013-12-14 11:47:35 +0800109 msr cptr_el3, xzr /* Enable FP/SIMD */
Thierry Reding25657922015-08-20 11:42:18 +0200110#ifdef COUNTER_FREQUENCY
David Feng85fd5f12013-12-14 11:47:35 +0800111 ldr x0, =COUNTER_FREQUENCY
112 msr cntfrq_el0, x0 /* Initialize CNTFRQ */
Thierry Reding25657922015-08-20 11:42:18 +0200113#endif
David Feng85fd5f12013-12-14 11:47:35 +0800114 b 0f
Andre Przywara4eecab72018-07-25 00:57:01 +01001152: set_vbar vbar_el2, x0
David Feng85fd5f12013-12-14 11:47:35 +0800116 mov x0, #0x33ff
117 msr cptr_el2, x0 /* Enable FP/SIMD */
118 b 0f
Andre Przywara4eecab72018-07-25 00:57:01 +01001191: set_vbar vbar_el1, x0
David Feng85fd5f12013-12-14 11:47:35 +0800120 mov x0, #3 << 20
121 msr cpacr_el1, x0 /* Enable FP/SIMD */
1220:
Volodymyr Babchukb2b52252020-06-24 01:05:19 +0000123 isb
David Feng85fd5f12013-12-14 11:47:35 +0800124
Mingkai Hu553d4052017-01-06 17:41:10 +0800125 /*
Dinh Nguyenc3e970a2017-04-26 23:36:03 -0500126 * Enable SMPEN bit for coherency.
Mingkai Hu553d4052017-01-06 17:41:10 +0800127 * This register is not architectural but at the moment
128 * this bit should be set for A53/A57/A72.
129 */
130#ifdef CONFIG_ARMV8_SET_SMPEN
York Sune6b871e2017-05-15 08:51:59 -0700131 switch_el x1, 3f, 1f, 1f
1323:
Dinh Nguyenc3e970a2017-04-26 23:36:03 -0500133 mrs x0, S3_1_c15_c2_1 /* cpuectlr_el1 */
Mingkai Hu553d4052017-01-06 17:41:10 +0800134 orr x0, x0, #0x40
135 msr S3_1_c15_c2_1, x0
Volodymyr Babchukb2b52252020-06-24 01:05:19 +0000136 isb
York Sune6b871e2017-05-15 08:51:59 -07001371:
Mingkai Hu553d4052017-01-06 17:41:10 +0800138#endif
139
Bhupesh Sharma80a7e352015-01-23 15:50:04 +0530140 /* Apply ARM core specific erratas */
141 bl apply_core_errata
142
York Sunef042012014-02-26 13:26:04 -0800143 /*
144 * Cache/BPB/TLB Invalidate
145 * i-cache is invalidated before enabled in icache_enable()
146 * tlb is invalidated before mmu is enabled in dcache_enable()
147 * d-cache is invalidated before enabled in dcache_enable()
148 */
David Feng85fd5f12013-12-14 11:47:35 +0800149
150 /* Processor specific initialization */
151 bl lowlevel_init
152
Oded Gabbay97a8d652016-12-27 11:19:43 +0200153#if defined(CONFIG_ARMV8_SPIN_TABLE) && !defined(CONFIG_SPL_BUILD)
Masahiro Yamada2663cd62016-06-27 19:31:05 +0900154 branch_if_master x0, x1, master_cpu
155 b spin_table_secondary_jump
156 /* never return */
157#elif defined(CONFIG_ARMV8_MULTIENTRY)
David Feng85fd5f12013-12-14 11:47:35 +0800158 branch_if_master x0, x1, master_cpu
159
160 /*
161 * Slave CPUs
162 */
163slave_cpu:
164 wfe
165 ldr x1, =CPU_RELEASE_ADDR
166 ldr x0, [x1]
167 cbz x0, slave_cpu
168 br x0 /* branch to the given address */
Linus Walleij74771392015-03-09 10:53:21 +0100169#endif /* CONFIG_ARMV8_MULTIENTRY */
Masahiro Yamada2663cd62016-06-27 19:31:05 +0900170master_cpu:
David Feng85fd5f12013-12-14 11:47:35 +0800171 bl _main
172
Sergey Temerkhanov78eaa492015-10-14 09:55:45 -0700173#ifdef CONFIG_SYS_RESET_SCTRL
174reset_sctrl:
175 switch_el x1, 3f, 2f, 1f
1763:
177 mrs x0, sctlr_el3
178 b 0f
1792:
180 mrs x0, sctlr_el2
181 b 0f
1821:
183 mrs x0, sctlr_el1
184
1850:
186 ldr x1, =0xfdfffffa
187 and x0, x0, x1
188
189 switch_el x1, 6f, 5f, 4f
1906:
191 msr sctlr_el3, x0
192 b 7f
1935:
194 msr sctlr_el2, x0
195 b 7f
1964:
197 msr sctlr_el1, x0
198
1997:
200 dsb sy
201 isb
202 b __asm_invalidate_tlb_all
203 ret
204#endif
205
David Feng85fd5f12013-12-14 11:47:35 +0800206/*-----------------------------------------------------------------------*/
207
Bhupesh Sharma80a7e352015-01-23 15:50:04 +0530208WEAK(apply_core_errata)
209
210 mov x29, lr /* Save LR */
Alison Wangc1293872017-12-28 13:00:55 +0800211 /* For now, we support Cortex-A53, Cortex-A57 specific errata */
212
213 /* Check if we are running on a Cortex-A53 core */
214 branch_if_a53_core x0, apply_a53_core_errata
Bhupesh Sharma80a7e352015-01-23 15:50:04 +0530215
216 /* Check if we are running on a Cortex-A57 core */
217 branch_if_a57_core x0, apply_a57_core_errata
2180:
219 mov lr, x29 /* Restore LR */
220 ret
221
Alison Wangc1293872017-12-28 13:00:55 +0800222apply_a53_core_errata:
223
224#ifdef CONFIG_ARM_ERRATA_855873
225 mrs x0, midr_el1
226 tst x0, #(0xf << 20)
227 b.ne 0b
228
229 mrs x0, midr_el1
230 and x0, x0, #0xf
231 cmp x0, #3
232 b.lt 0b
233
234 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
235 /* Enable data cache clean as data cache clean/invalidate */
236 orr x0, x0, #1 << 44
237 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
Volodymyr Babchukb2b52252020-06-24 01:05:19 +0000238 isb
Alison Wangc1293872017-12-28 13:00:55 +0800239#endif
240 b 0b
241
Bhupesh Sharma80a7e352015-01-23 15:50:04 +0530242apply_a57_core_errata:
243
244#ifdef CONFIG_ARM_ERRATA_828024
245 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
246 /* Disable non-allocate hint of w-b-n-a memory type */
Bhupesh Sharma06a0f1d2015-05-28 14:54:13 +0530247 orr x0, x0, #1 << 49
Bhupesh Sharma80a7e352015-01-23 15:50:04 +0530248 /* Disable write streaming no L1-allocate threshold */
Bhupesh Sharma06a0f1d2015-05-28 14:54:13 +0530249 orr x0, x0, #3 << 25
Bhupesh Sharma80a7e352015-01-23 15:50:04 +0530250 /* Disable write streaming no-allocate threshold */
Bhupesh Sharma06a0f1d2015-05-28 14:54:13 +0530251 orr x0, x0, #3 << 27
Bhupesh Sharma80a7e352015-01-23 15:50:04 +0530252 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
Volodymyr Babchukb2b52252020-06-24 01:05:19 +0000253 isb
Bhupesh Sharma80a7e352015-01-23 15:50:04 +0530254#endif
255
256#ifdef CONFIG_ARM_ERRATA_826974
257 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
258 /* Disable speculative load execution ahead of a DMB */
Bhupesh Sharma06a0f1d2015-05-28 14:54:13 +0530259 orr x0, x0, #1 << 59
Bhupesh Sharma80a7e352015-01-23 15:50:04 +0530260 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
Volodymyr Babchukb2b52252020-06-24 01:05:19 +0000261 isb
Bhupesh Sharma80a7e352015-01-23 15:50:04 +0530262#endif
263
Ashish kumar9c6d33c2016-01-27 18:09:32 +0530264#ifdef CONFIG_ARM_ERRATA_833471
265 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
266 /* FPSCR write flush.
267 * Note that in some cases where a flush is unnecessary this
268 could impact performance. */
269 orr x0, x0, #1 << 38
270 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
Volodymyr Babchukb2b52252020-06-24 01:05:19 +0000271 isb
Ashish kumar9c6d33c2016-01-27 18:09:32 +0530272#endif
273
274#ifdef CONFIG_ARM_ERRATA_829520
275 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
276 /* Disable Indirect Predictor bit will prevent this erratum
277 from occurring
278 * Note that in some cases where a flush is unnecessary this
279 could impact performance. */
280 orr x0, x0, #1 << 4
281 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
Volodymyr Babchukb2b52252020-06-24 01:05:19 +0000282 isb
Ashish kumar9c6d33c2016-01-27 18:09:32 +0530283#endif
284
Bhupesh Sharma80a7e352015-01-23 15:50:04 +0530285#ifdef CONFIG_ARM_ERRATA_833069
286 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
287 /* Disable Enable Invalidates of BTB bit */
288 and x0, x0, #0xE
289 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
Volodymyr Babchukb2b52252020-06-24 01:05:19 +0000290 isb
Bhupesh Sharma80a7e352015-01-23 15:50:04 +0530291#endif
292 b 0b
293ENDPROC(apply_core_errata)
294
295/*-----------------------------------------------------------------------*/
296
David Feng85fd5f12013-12-14 11:47:35 +0800297WEAK(lowlevel_init)
David Feng85fd5f12013-12-14 11:47:35 +0800298 mov x29, lr /* Save LR */
David Feng85fd5f12013-12-14 11:47:35 +0800299
David Feng79bbde02014-03-14 14:26:27 +0800300#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
301 branch_if_slave x0, 1f
302 ldr x0, =GICD_BASE
303 bl gic_init_secure
3041:
305#if defined(CONFIG_GICV3)
306 ldr x0, =GICR_BASE
307 bl gic_init_secure_percpu
308#elif defined(CONFIG_GICV2)
309 ldr x0, =GICD_BASE
310 ldr x1, =GICC_BASE
311 bl gic_init_secure_percpu
312#endif
Stephen Warren73f47af2016-04-28 12:45:44 -0600313#endif
David Feng79bbde02014-03-14 14:26:27 +0800314
Masahiro Yamadae4ce25f2016-05-20 12:13:10 +0900315#ifdef CONFIG_ARMV8_MULTIENTRY
David Feng79bbde02014-03-14 14:26:27 +0800316 branch_if_master x0, x1, 2f
David Feng85fd5f12013-12-14 11:47:35 +0800317
318 /*
319 * Slave should wait for master clearing spin table.
320 * This sync prevent salves observing incorrect
321 * value of spin table and jumping to wrong place.
322 */
David Feng79bbde02014-03-14 14:26:27 +0800323#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
324#ifdef CONFIG_GICV2
325 ldr x0, =GICC_BASE
326#endif
327 bl gic_wait_for_interrupt
328#endif
David Feng85fd5f12013-12-14 11:47:35 +0800329
330 /*
David Feng79bbde02014-03-14 14:26:27 +0800331 * All slaves will enter EL2 and optionally EL1.
David Feng85fd5f12013-12-14 11:47:35 +0800332 */
Alison Wangeb2088d2017-01-17 09:39:17 +0800333 adr x4, lowlevel_in_el2
334 ldr x5, =ES_TO_AARCH64
David Feng85fd5f12013-12-14 11:47:35 +0800335 bl armv8_switch_to_el2
Alison Wang73818d52016-11-10 10:49:03 +0800336
337lowlevel_in_el2:
David Feng85fd5f12013-12-14 11:47:35 +0800338#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
Alison Wangeb2088d2017-01-17 09:39:17 +0800339 adr x4, lowlevel_in_el1
340 ldr x5, =ES_TO_AARCH64
David Feng85fd5f12013-12-14 11:47:35 +0800341 bl armv8_switch_to_el1
Alison Wang73818d52016-11-10 10:49:03 +0800342
343lowlevel_in_el1:
David Feng85fd5f12013-12-14 11:47:35 +0800344#endif
345
Linus Walleij74771392015-03-09 10:53:21 +0100346#endif /* CONFIG_ARMV8_MULTIENTRY */
347
David Feng79bbde02014-03-14 14:26:27 +08003482:
David Feng85fd5f12013-12-14 11:47:35 +0800349 mov lr, x29 /* Restore LR */
350 ret
351ENDPROC(lowlevel_init)
352
David Feng79bbde02014-03-14 14:26:27 +0800353WEAK(smp_kick_all_cpus)
354 /* Kick secondary cpus up by SGI 0 interrupt */
David Feng79bbde02014-03-14 14:26:27 +0800355#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
356 ldr x0, =GICD_BASE
Masahiro Yamadab9140092016-06-17 18:32:47 +0900357 b gic_kick_secondary_cpus
David Feng79bbde02014-03-14 14:26:27 +0800358#endif
David Feng79bbde02014-03-14 14:26:27 +0800359 ret
360ENDPROC(smp_kick_all_cpus)
361
David Feng85fd5f12013-12-14 11:47:35 +0800362/*-----------------------------------------------------------------------*/
363
364ENTRY(c_runtime_cpu_setup)
Alexander Grafb3e9dc62019-02-20 17:14:49 +0100365#if defined(CONFIG_ARMV8_SPL_EXCEPTION_VECTORS) || !defined(CONFIG_SPL_BUILD)
David Feng85fd5f12013-12-14 11:47:35 +0800366 /* Relocate vBAR */
367 adr x0, vectors
368 switch_el x1, 3f, 2f, 1f
3693: msr vbar_el3, x0
370 b 0f
3712: msr vbar_el2, x0
372 b 0f
3731: msr vbar_el1, x0
3740:
Andre Przywara4eecab72018-07-25 00:57:01 +0100375#endif
David Feng85fd5f12013-12-14 11:47:35 +0800376
377 ret
378ENDPROC(c_runtime_cpu_setup)
Stephen Warren100a4792016-07-18 17:01:50 -0600379
380WEAK(save_boot_params)
381 b save_boot_params_ret /* back to my caller */
382ENDPROC(save_boot_params)