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David Feng85fd5f12013-12-14 11:47:35 +08001/*
2 * (C) Copyright 2013
3 * David Feng <fenghua@phytium.com.cn>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8#include <asm-offsets.h>
9#include <config.h>
10#include <version.h>
11#include <linux/linkage.h>
12#include <asm/macro.h>
13#include <asm/armv8/mmu.h>
14
15/*************************************************************************
16 *
17 * Startup Code (reset vector)
18 *
19 *************************************************************************/
20
21.globl _start
22_start:
23 b reset
24
25 .align 3
26
27.globl _TEXT_BASE
28_TEXT_BASE:
29 .quad CONFIG_SYS_TEXT_BASE
30
31/*
32 * These are defined in the linker script.
33 */
34.globl _end_ofs
35_end_ofs:
36 .quad _end - _start
37
38.globl _bss_start_ofs
39_bss_start_ofs:
40 .quad __bss_start - _start
41
42.globl _bss_end_ofs
43_bss_end_ofs:
44 .quad __bss_end - _start
45
46reset:
47 /*
48 * Could be EL3/EL2/EL1, Initial State:
49 * Little Endian, MMU Disabled, i/dCache Disabled
50 */
51 adr x0, vectors
52 switch_el x1, 3f, 2f, 1f
533: msr vbar_el3, x0
54 msr cptr_el3, xzr /* Enable FP/SIMD */
55 ldr x0, =COUNTER_FREQUENCY
56 msr cntfrq_el0, x0 /* Initialize CNTFRQ */
57 b 0f
582: msr vbar_el2, x0
59 mov x0, #0x33ff
60 msr cptr_el2, x0 /* Enable FP/SIMD */
61 b 0f
621: msr vbar_el1, x0
63 mov x0, #3 << 20
64 msr cpacr_el1, x0 /* Enable FP/SIMD */
650:
66
York Sunef042012014-02-26 13:26:04 -080067 /*
68 * Cache/BPB/TLB Invalidate
69 * i-cache is invalidated before enabled in icache_enable()
70 * tlb is invalidated before mmu is enabled in dcache_enable()
71 * d-cache is invalidated before enabled in dcache_enable()
72 */
David Feng85fd5f12013-12-14 11:47:35 +080073
74 /* Processor specific initialization */
75 bl lowlevel_init
76
77 branch_if_master x0, x1, master_cpu
78
79 /*
80 * Slave CPUs
81 */
82slave_cpu:
83 wfe
84 ldr x1, =CPU_RELEASE_ADDR
85 ldr x0, [x1]
86 cbz x0, slave_cpu
87 br x0 /* branch to the given address */
88
89 /*
90 * Master CPU
91 */
92master_cpu:
93 bl _main
94
95/*-----------------------------------------------------------------------*/
96
97WEAK(lowlevel_init)
98 /* Initialize GIC Secure Bank Status */
99 mov x29, lr /* Save LR */
100 bl gic_init
101
102 branch_if_master x0, x1, 1f
103
104 /*
105 * Slave should wait for master clearing spin table.
106 * This sync prevent salves observing incorrect
107 * value of spin table and jumping to wrong place.
108 */
109 bl wait_for_wakeup
110
111 /*
112 * All processors will enter EL2 and optionally EL1.
113 */
114 bl armv8_switch_to_el2
115#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
116 bl armv8_switch_to_el1
117#endif
118
1191:
120 mov lr, x29 /* Restore LR */
121 ret
122ENDPROC(lowlevel_init)
123
124/*-----------------------------------------------------------------------*/
125
126ENTRY(c_runtime_cpu_setup)
David Feng85fd5f12013-12-14 11:47:35 +0800127 /* Relocate vBAR */
128 adr x0, vectors
129 switch_el x1, 3f, 2f, 1f
1303: msr vbar_el3, x0
131 b 0f
1322: msr vbar_el2, x0
133 b 0f
1341: msr vbar_el1, x0
1350:
136
137 ret
138ENDPROC(c_runtime_cpu_setup)