blob: 32ca242f35dd87258d9a6a71ffa91d6c0b5e1527 [file] [log] [blame]
Scott Wood865b8ae2007-04-16 14:54:15 -05001/*
Scott Wood3f53f1a2010-08-30 18:04:52 -05002 * Copyright (C) Freescale Semiconductor, Inc. 2006, 2010.
Scott Wood865b8ae2007-04-16 14:54:15 -05003 *
Wolfgang Denkbd8ec7e2013-10-07 13:07:26 +02004 * SPDX-License-Identifier: GPL-2.0+
Scott Wood865b8ae2007-04-16 14:54:15 -05005 */
6/*
7 * mpc8313epb board configuration file
8 */
9
10#ifndef __CONFIG_H
11#define __CONFIG_H
12
13/*
14 * High Level Configuration Options
15 */
16#define CONFIG_E300 1
Peter Tyser72f2d392009-05-22 17:23:25 -050017#define CONFIG_MPC831x 1
Scott Wood865b8ae2007-04-16 14:54:15 -050018#define CONFIG_MPC8313 1
19#define CONFIG_MPC8313ERDB 1
20
Scott Wood488af0d2012-12-06 13:33:18 +000021#ifdef CONFIG_NAND
Scott Wood488af0d2012-12-06 13:33:18 +000022#define CONFIG_SPL_INIT_MINIMAL
Scott Wood488af0d2012-12-06 13:33:18 +000023#define CONFIG_SPL_FLUSH_IMAGE
24#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
25#define CONFIG_SPL_MPC83XX_WAIT_FOR_NAND
26
27#ifdef CONFIG_SPL_BUILD
28#define CONFIG_NS16550_MIN_FUNCTIONS
29#endif
30
31#define CONFIG_SYS_TEXT_BASE 0x00100000 /* CONFIG_SYS_NAND_U_BOOT_DST */
32#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
33#define CONFIG_SPL_MAX_SIZE (4 * 1024)
Benoît Thébaudeauf0180722013-04-11 09:35:49 +000034#define CONFIG_SPL_PAD_TO 0x4000
Scott Wood488af0d2012-12-06 13:33:18 +000035
Scott Woodf60c06e2010-11-24 13:28:40 +000036#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
37#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
38#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
39#define CONFIG_SYS_NAND_U_BOOT_OFFS 16384
40#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
41#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
42
Scott Wood488af0d2012-12-06 13:33:18 +000043#ifdef CONFIG_SPL_BUILD
Scott Woodf60c06e2010-11-24 13:28:40 +000044#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
Scott Wood488af0d2012-12-06 13:33:18 +000045#endif
46
47#endif /* CONFIG_NAND */
Scott Woodf60c06e2010-11-24 13:28:40 +000048
Wolfgang Denk291ba1b2010-10-06 09:05:45 +020049#ifndef CONFIG_SYS_TEXT_BASE
50#define CONFIG_SYS_TEXT_BASE 0xFE000000
51#endif
52
Scott Woodf60c06e2010-11-24 13:28:40 +000053#ifndef CONFIG_SYS_MONITOR_BASE
54#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
55#endif
56
Gabor Juhosb4458732013-05-30 07:06:12 +000057#define CONFIG_PCI_INDIRECT_BRIDGE
Becky Brucedfe6e232010-06-17 11:37:18 -050058#define CONFIG_FSL_ELBC 1
Scott Wood865b8ae2007-04-16 14:54:15 -050059
Timur Tabi3e1d49a2008-02-08 13:15:55 -060060#define CONFIG_MISC_INIT_R
61
62/*
63 * On-board devices
York Sun224069c2008-05-15 15:26:27 -050064 *
65 * TSEC1 is VSC switch
66 * TSEC2 is SoC TSEC
Timur Tabi3e1d49a2008-02-08 13:15:55 -060067 */
68#define CONFIG_VSC7385_ENET
York Sun224069c2008-05-15 15:26:27 -050069#define CONFIG_TSEC2
Timur Tabi3e1d49a2008-02-08 13:15:55 -060070
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020071#ifdef CONFIG_SYS_66MHZ
Kim Phillipsffc21c02007-04-25 12:34:38 -050072#define CONFIG_83XX_CLKIN 66666667 /* in Hz */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020073#elif defined(CONFIG_SYS_33MHZ)
Kim Phillipsffc21c02007-04-25 12:34:38 -050074#define CONFIG_83XX_CLKIN 33333333 /* in Hz */
Scott Wood865b8ae2007-04-16 14:54:15 -050075#else
76#error Unknown oscillator frequency.
77#endif
78
79#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
80
Joe Hershberger37dabcc2011-11-11 15:55:38 -060081#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r */
Scott Wood865b8ae2007-04-16 14:54:15 -050082
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020083#define CONFIG_SYS_IMMR 0xE0000000
Scott Wood865b8ae2007-04-16 14:54:15 -050084
Scott Wood488af0d2012-12-06 13:33:18 +000085#if defined(CONFIG_NAND) && !defined(CONFIG_SPL_BUILD)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020086#define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR
Scott Woodb71689b2008-06-30 14:13:28 -050087#endif
88
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020089#define CONFIG_SYS_MEMTEST_START 0x00001000
90#define CONFIG_SYS_MEMTEST_END 0x07f00000
Scott Wood865b8ae2007-04-16 14:54:15 -050091
92/* Early revs of this board will lock up hard when attempting
93 * to access the PMC registers, unless a JTAG debugger is
94 * connected, or some resistor modifications are made.
95 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020096#define CONFIG_SYS_8313ERDB_BROKEN_PMC 1
Scott Wood865b8ae2007-04-16 14:54:15 -050097
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020098#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
99#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
Scott Wood865b8ae2007-04-16 14:54:15 -0500100
101/*
Timur Tabi3e1d49a2008-02-08 13:15:55 -0600102 * Device configurations
103 */
104
105/* Vitesse 7385 */
106
107#ifdef CONFIG_VSC7385_ENET
108
York Sun224069c2008-05-15 15:26:27 -0500109#define CONFIG_TSEC1
Timur Tabi3e1d49a2008-02-08 13:15:55 -0600110
111/* The flash address and size of the VSC7385 firmware image */
112#define CONFIG_VSC7385_IMAGE 0xFE7FE000
113#define CONFIG_VSC7385_IMAGE_SIZE 8192
114
115#endif
116
117/*
Scott Wood865b8ae2007-04-16 14:54:15 -0500118 * DDR Setup
119 */
Joe Hershbergerb263cae2011-10-11 23:57:10 -0500120#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200121#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
122#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
Scott Wood865b8ae2007-04-16 14:54:15 -0500123
124/*
125 * Manually set up DDR parameters, as this board does not
126 * seem to have the SPD connected to I2C.
127 */
Joe Hershbergerb263cae2011-10-11 23:57:10 -0500128#define CONFIG_SYS_DDR_SIZE 128 /* MB */
Joe Hershberger5ade3902011-10-11 23:57:31 -0500129#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
Joe Hershbergercc03b802011-10-11 23:57:29 -0500130 | CSCONFIG_ODT_RD_NEVER \
131 | CSCONFIG_ODT_WR_ONLY_CURRENT \
Joe Hershbergerb263cae2011-10-11 23:57:10 -0500132 | CSCONFIG_ROW_BIT_13 \
133 | CSCONFIG_COL_BIT_10)
Poonam Aggrwalff452842008-01-14 09:41:14 +0530134 /* 0x80010102 */
Scott Wood865b8ae2007-04-16 14:54:15 -0500135
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200136#define CONFIG_SYS_DDR_TIMING_3 0x00000000
Joe Hershbergerb263cae2011-10-11 23:57:10 -0500137#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
138 | (0 << TIMING_CFG0_WRT_SHIFT) \
139 | (0 << TIMING_CFG0_RRT_SHIFT) \
140 | (0 << TIMING_CFG0_WWT_SHIFT) \
141 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
142 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
143 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
144 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
Scott Wood865b8ae2007-04-16 14:54:15 -0500145 /* 0x00220802 */
Joe Hershbergerb263cae2011-10-11 23:57:10 -0500146#define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
147 | (8 << TIMING_CFG1_ACTTOPRE_SHIFT) \
148 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
149 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
150 | (10 << TIMING_CFG1_REFREC_SHIFT) \
151 | (3 << TIMING_CFG1_WRREC_SHIFT) \
152 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
153 | (2 << TIMING_CFG1_WRTORD_SHIFT))
Poonam Aggrwalff452842008-01-14 09:41:14 +0530154 /* 0x3835a322 */
Joe Hershbergerb263cae2011-10-11 23:57:10 -0500155#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
156 | (5 << TIMING_CFG2_CPO_SHIFT) \
157 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
158 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
159 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
160 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
161 | (6 << TIMING_CFG2_FOUR_ACT_SHIFT))
Poonam Aggrwalff452842008-01-14 09:41:14 +0530162 /* 0x129048c6 */ /* P9-45,may need tuning */
Joe Hershbergerb263cae2011-10-11 23:57:10 -0500163#define CONFIG_SYS_DDR_INTERVAL ((1296 << SDRAM_INTERVAL_REFINT_SHIFT) \
164 | (1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
Poonam Aggrwalff452842008-01-14 09:41:14 +0530165 /* 0x05100500 */
Scott Wood865b8ae2007-04-16 14:54:15 -0500166#if defined(CONFIG_DDR_2T_TIMING)
Joe Hershbergerb263cae2011-10-11 23:57:10 -0500167#define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \
Kim Phillips3b9c20f2007-08-16 22:52:48 -0500168 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
Joe Hershbergercc03b802011-10-11 23:57:29 -0500169 | SDRAM_CFG_DBW_32 \
170 | SDRAM_CFG_2T_EN)
171 /* 0x43088000 */
Scott Wood865b8ae2007-04-16 14:54:15 -0500172#else
Joe Hershbergerb263cae2011-10-11 23:57:10 -0500173#define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \
Kim Phillips3b9c20f2007-08-16 22:52:48 -0500174 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
Joe Hershbergercc03b802011-10-11 23:57:29 -0500175 | SDRAM_CFG_DBW_32)
Scott Wood865b8ae2007-04-16 14:54:15 -0500176 /* 0x43080000 */
177#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200178#define CONFIG_SYS_SDRAM_CFG2 0x00401000
Scott Wood865b8ae2007-04-16 14:54:15 -0500179/* set burst length to 8 for 32-bit data path */
Joe Hershbergerb263cae2011-10-11 23:57:10 -0500180#define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \
181 | (0x0632 << SDRAM_MODE_SD_SHIFT))
Poonam Aggrwalff452842008-01-14 09:41:14 +0530182 /* 0x44480632 */
Joe Hershbergerb263cae2011-10-11 23:57:10 -0500183#define CONFIG_SYS_DDR_MODE_2 0x8000C000
Scott Wood865b8ae2007-04-16 14:54:15 -0500184
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200185#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
Scott Wood865b8ae2007-04-16 14:54:15 -0500186 /*0x02000000*/
Joe Hershbergerb263cae2011-10-11 23:57:10 -0500187#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
Scott Wood865b8ae2007-04-16 14:54:15 -0500188 | DDRCDR_PZ_NOMZ \
189 | DDRCDR_NZ_NOMZ \
Joe Hershbergerb263cae2011-10-11 23:57:10 -0500190 | DDRCDR_M_ODR)
Scott Wood865b8ae2007-04-16 14:54:15 -0500191
192/*
193 * FLASH on the Local Bus
194 */
Joe Hershbergerb263cae2011-10-11 23:57:10 -0500195#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
196#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200197#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */
Joe Hershbergerb263cae2011-10-11 23:57:10 -0500198#define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */
199#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
200#define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */
201#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */
Scott Wood865b8ae2007-04-16 14:54:15 -0500202
Joe Hershbergerb263cae2011-10-11 23:57:10 -0500203#define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \
Joe Hershbergerf05b9332011-10-11 23:57:30 -0500204 | BR_PS_16 /* 16 bit port */ \
205 | BR_MS_GPCM /* MSEL = GPCM */ \
206 | BR_V) /* valid */
207#define CONFIG_SYS_NOR_OR_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
Scott Wood865b8ae2007-04-16 14:54:15 -0500208 | OR_GPCM_XACS \
209 | OR_GPCM_SCY_9 \
210 | OR_GPCM_EHTR \
Joe Hershbergerb263cae2011-10-11 23:57:10 -0500211 | OR_GPCM_EAD)
Scott Wood865b8ae2007-04-16 14:54:15 -0500212 /* 0xFF006FF7 TODO SLOW 16 MB flash size */
Joe Hershbergerb263cae2011-10-11 23:57:10 -0500213 /* window base at flash base */
214#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
Joe Hershbergerf05b9332011-10-11 23:57:30 -0500215 /* 16 MB window size */
216#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_16MB)
Scott Wood865b8ae2007-04-16 14:54:15 -0500217
Joe Hershbergerb263cae2011-10-11 23:57:10 -0500218#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
219#define CONFIG_SYS_MAX_FLASH_SECT 135 /* sectors per device */
Scott Wood865b8ae2007-04-16 14:54:15 -0500220
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200221#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
222#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
Scott Wood865b8ae2007-04-16 14:54:15 -0500223
Joe Hershbergerb263cae2011-10-11 23:57:10 -0500224#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && \
Scott Wood488af0d2012-12-06 13:33:18 +0000225 !defined(CONFIG_SPL_BUILD)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200226#define CONFIG_SYS_RAMBOOT
Scott Wood865b8ae2007-04-16 14:54:15 -0500227#endif
228
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200229#define CONFIG_SYS_INIT_RAM_LOCK 1
Joe Hershbergerb263cae2011-10-11 23:57:10 -0500230#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */
231#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
Scott Wood865b8ae2007-04-16 14:54:15 -0500232
Joe Hershbergerb263cae2011-10-11 23:57:10 -0500233#define CONFIG_SYS_GBL_DATA_OFFSET \
234 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200235#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Scott Wood865b8ae2007-04-16 14:54:15 -0500236
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200237/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
Kevin Hao349a0152016-07-08 11:25:14 +0800238#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
Joe Hershbergerb263cae2011-10-11 23:57:10 -0500239#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
Scott Wood865b8ae2007-04-16 14:54:15 -0500240
241/*
242 * Local Bus LCRR and LBCR regs
243 */
Kim Phillips328040a2009-09-25 18:19:44 -0500244#define CONFIG_SYS_LCRR_EADC LCRR_EADC_1
245#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
Joe Hershbergerb263cae2011-10-11 23:57:10 -0500246#define CONFIG_SYS_LBC_LBCR (0x00040000 /* TODO */ \
247 | (0xFF << LBCR_BMT_SHIFT) \
248 | 0xF) /* 0x0004ff0f */
Scott Wood865b8ae2007-04-16 14:54:15 -0500249
Joe Hershbergerb263cae2011-10-11 23:57:10 -0500250 /* LB refresh timer prescal, 266MHz/32 */
251#define CONFIG_SYS_LBC_MRTPR 0x20000000 /*TODO */
Scott Wood865b8ae2007-04-16 14:54:15 -0500252
Marcel Ziswileraea68562007-12-30 03:30:46 +0100253/* drivers/mtd/nand/nand.c */
Scott Wood488af0d2012-12-06 13:33:18 +0000254#if defined(CONFIG_NAND) && defined(CONFIG_SPL_BUILD)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200255#define CONFIG_SYS_NAND_BASE 0xFFF00000
Scott Woodb71689b2008-06-30 14:13:28 -0500256#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200257#define CONFIG_SYS_NAND_BASE 0xE2800000
Scott Woodb71689b2008-06-30 14:13:28 -0500258#endif
259
Scott Wood3f53f1a2010-08-30 18:04:52 -0500260#define CONFIG_MTD_DEVICE
261#define CONFIG_MTD_PARTITION
262#define CONFIG_CMD_MTDPARTS
263#define MTDIDS_DEFAULT "nand0=e2800000.flash"
Joe Hershbergerb263cae2011-10-11 23:57:10 -0500264#define MTDPARTS_DEFAULT \
Kevin Hao9c747962016-07-08 11:25:15 +0800265 "mtdparts=e2800000.flash:512k(uboot),128k(env),6m@1m(kernel),-(fs)"
Scott Wood3f53f1a2010-08-30 18:04:52 -0500266
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200267#define CONFIG_SYS_MAX_NAND_DEVICE 1
Scott Woodb7dac212008-06-26 14:06:52 -0500268#define CONFIG_CMD_NAND 1
269#define CONFIG_NAND_FSL_ELBC 1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200270#define CONFIG_SYS_NAND_BLOCK_SIZE 16384
Joe Hershbergerf05b9332011-10-11 23:57:30 -0500271#define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024)
Scott Woodb71689b2008-06-30 14:13:28 -0500272
Joe Hershbergerb263cae2011-10-11 23:57:10 -0500273#define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \
Joe Hershbergerf05b9332011-10-11 23:57:30 -0500274 | BR_DECC_CHK_GEN /* Use HW ECC */ \
Joe Hershbergerb263cae2011-10-11 23:57:10 -0500275 | BR_PS_8 /* 8 bit port */ \
Wolfgang Denk48923392007-05-16 01:16:53 +0200276 | BR_MS_FCM /* MSEL = FCM */ \
Joe Hershbergerb263cae2011-10-11 23:57:10 -0500277 | BR_V) /* valid */
Joe Hershbergerf05b9332011-10-11 23:57:30 -0500278#define CONFIG_SYS_NAND_OR_PRELIM \
279 (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \
Scott Wood865b8ae2007-04-16 14:54:15 -0500280 | OR_FCM_CSCT \
281 | OR_FCM_CST \
282 | OR_FCM_CHT \
283 | OR_FCM_SCY_1 \
284 | OR_FCM_TRLX \
Joe Hershbergerb263cae2011-10-11 23:57:10 -0500285 | OR_FCM_EHTR)
Scott Wood865b8ae2007-04-16 14:54:15 -0500286 /* 0xFFFF8396 */
Scott Woodb71689b2008-06-30 14:13:28 -0500287
Scott Wood488af0d2012-12-06 13:33:18 +0000288#ifdef CONFIG_NAND
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200289#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM
290#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM
291#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NOR_BR_PRELIM
292#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NOR_OR_PRELIM
Scott Woodb71689b2008-06-30 14:13:28 -0500293#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200294#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM
295#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM
296#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
297#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
Scott Woodb71689b2008-06-30 14:13:28 -0500298#endif
299
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200300#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
Joe Hershbergerf05b9332011-10-11 23:57:30 -0500301#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
Scott Wood865b8ae2007-04-16 14:54:15 -0500302
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200303#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
304#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
Scott Woodb71689b2008-06-30 14:13:28 -0500305
Joe Hershbergerf05b9332011-10-11 23:57:30 -0500306/* local bus write LED / read status buffer (BCSR) mapping */
307#define CONFIG_SYS_BCSR_ADDR 0xFA000000
308#define CONFIG_SYS_BCSR_SIZE (32 * 1024) /* 0x00008000 */
309 /* map at 0xFA000000 on LCS3 */
310#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_BCSR_ADDR \
311 | BR_PS_8 /* 8 bit port */ \
312 | BR_MS_GPCM /* MSEL = GPCM */ \
313 | BR_V) /* valid */
314 /* 0xFA000801 */
315#define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(CONFIG_SYS_BCSR_SIZE) \
316 | OR_GPCM_CSNT \
317 | OR_GPCM_ACS_DIV2 \
318 | OR_GPCM_XACS \
319 | OR_GPCM_SCY_15 \
320 | OR_GPCM_TRLX_SET \
321 | OR_GPCM_EHTR_SET \
322 | OR_GPCM_EAD)
323 /* 0xFFFF8FF7 */
324#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_BCSR_ADDR
325#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
Timur Tabi3e1d49a2008-02-08 13:15:55 -0600326
327/* Vitesse 7385 */
328
Timur Tabi3e1d49a2008-02-08 13:15:55 -0600329#ifdef CONFIG_VSC7385_ENET
330
Joe Hershbergerf05b9332011-10-11 23:57:30 -0500331 /* VSC7385 Base address on LCS2 */
332#define CONFIG_SYS_VSC7385_BASE 0xF0000000
333#define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */
334
335#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE \
336 | BR_PS_8 /* 8 bit port */ \
337 | BR_MS_GPCM /* MSEL = GPCM */ \
338 | BR_V) /* valid */
339#define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \
340 | OR_GPCM_CSNT \
341 | OR_GPCM_XACS \
342 | OR_GPCM_SCY_15 \
343 | OR_GPCM_SETA \
344 | OR_GPCM_TRLX_SET \
345 | OR_GPCM_EHTR_SET \
346 | OR_GPCM_EAD)
347 /* 0xFFFE09FF */
348
Joe Hershbergerb263cae2011-10-11 23:57:10 -0500349 /* Access window base at VSC7385 base */
350#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE
Joe Hershbergerf05b9332011-10-11 23:57:30 -0500351#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB)
Scott Wood865b8ae2007-04-16 14:54:15 -0500352
Timur Tabi3e1d49a2008-02-08 13:15:55 -0600353#endif
Scott Wood865b8ae2007-04-16 14:54:15 -0500354
Joe Hershberger37dabcc2011-11-11 15:55:38 -0600355#define CONFIG_MPC83XX_GPIO 1
Joe Hershberger37dabcc2011-11-11 15:55:38 -0600356
Scott Wood865b8ae2007-04-16 14:54:15 -0500357/*
358 * Serial Port
359 */
360#define CONFIG_CONS_INDEX 1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200361#define CONFIG_SYS_NS16550_SERIAL
362#define CONFIG_SYS_NS16550_REG_SIZE 1
Scott Wood865b8ae2007-04-16 14:54:15 -0500363
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200364#define CONFIG_SYS_BAUDRATE_TABLE \
Scott Wood865b8ae2007-04-16 14:54:15 -0500365 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
366
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200367#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
368#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
Scott Wood865b8ae2007-04-16 14:54:15 -0500369
Scott Wood865b8ae2007-04-16 14:54:15 -0500370/* I2C */
Heiko Schocherf2850742012-10-24 13:48:22 +0200371#define CONFIG_SYS_I2C
372#define CONFIG_SYS_I2C_FSL
373#define CONFIG_SYS_FSL_I2C_SPEED 400000
374#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
375#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
376#define CONFIG_SYS_FSL_I2C2_SPEED 400000
377#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
378#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
379#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
Scott Wood865b8ae2007-04-16 14:54:15 -0500380
Scott Wood865b8ae2007-04-16 14:54:15 -0500381/*
382 * General PCI
383 * Addresses are mapped 1-1.
384 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200385#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
386#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
387#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
388#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
389#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
390#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
391#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
392#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
393#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
Scott Wood865b8ae2007-04-16 14:54:15 -0500394
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200395#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
Scott Wood865b8ae2007-04-16 14:54:15 -0500396
397/*
Timur Tabi3e1d49a2008-02-08 13:15:55 -0600398 * TSEC
Scott Wood865b8ae2007-04-16 14:54:15 -0500399 */
400#define CONFIG_TSEC_ENET /* TSEC ethernet support */
401
Timur Tabi3e1d49a2008-02-08 13:15:55 -0600402#define CONFIG_GMII /* MII PHY management */
Scott Wood865b8ae2007-04-16 14:54:15 -0500403
Timur Tabi3e1d49a2008-02-08 13:15:55 -0600404#ifdef CONFIG_TSEC1
405#define CONFIG_HAS_ETH0
Kim Phillips177e58f2007-05-16 16:52:19 -0500406#define CONFIG_TSEC1_NAME "TSEC0"
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200407#define CONFIG_SYS_TSEC1_OFFSET 0x24000
Timur Tabi3e1d49a2008-02-08 13:15:55 -0600408#define TSEC1_PHY_ADDR 0x1c
409#define TSEC1_FLAGS TSEC_GIGABIT
410#define TSEC1_PHYIDX 0
411#endif
412
413#ifdef CONFIG_TSEC2
414#define CONFIG_HAS_ETH1
Kim Phillips177e58f2007-05-16 16:52:19 -0500415#define CONFIG_TSEC2_NAME "TSEC1"
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200416#define CONFIG_SYS_TSEC2_OFFSET 0x25000
Timur Tabi3e1d49a2008-02-08 13:15:55 -0600417#define TSEC2_PHY_ADDR 4
418#define TSEC2_FLAGS TSEC_GIGABIT
419#define TSEC2_PHYIDX 0
420#endif
421
Scott Wood865b8ae2007-04-16 14:54:15 -0500422/* Options are: TSEC[0-1] */
423#define CONFIG_ETHPRIME "TSEC1"
424
425/*
426 * Configure on-board RTC
427 */
428#define CONFIG_RTC_DS1337
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200429#define CONFIG_SYS_I2C_RTC_ADDR 0x68
Scott Wood865b8ae2007-04-16 14:54:15 -0500430
431/*
432 * Environment
433 */
Scott Wood488af0d2012-12-06 13:33:18 +0000434#if defined(CONFIG_NAND)
Jean-Christophe PLAGNIOL-VILLARDdda84dd2008-09-10 22:47:58 +0200435 #define CONFIG_ENV_IS_IN_NAND 1
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200436 #define CONFIG_ENV_OFFSET (512 * 1024)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200437 #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200438 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
439 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
440 #define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4)
Joe Hershbergerb263cae2011-10-11 23:57:10 -0500441 #define CONFIG_ENV_OFFSET_REDUND \
442 (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200443#elif !defined(CONFIG_SYS_RAMBOOT)
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +0200444 #define CONFIG_ENV_IS_IN_FLASH 1
Joe Hershbergerb263cae2011-10-11 23:57:10 -0500445 #define CONFIG_ENV_ADDR \
446 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200447 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
448 #define CONFIG_ENV_SIZE 0x2000
Scott Wood865b8ae2007-04-16 14:54:15 -0500449
450/* Address and size of Redundant Environment Sector */
451#else
Jean-Christophe PLAGNIOL-VILLARD68a87562008-09-10 22:48:00 +0200452 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200453 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200454 #define CONFIG_ENV_SIZE 0x2000
Scott Wood865b8ae2007-04-16 14:54:15 -0500455#endif
456
457#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200458#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Scott Wood865b8ae2007-04-16 14:54:15 -0500459
Jon Loeliger3b7116d2007-07-04 22:30:06 -0500460/*
Jon Loeliger5c4ddae2007-07-10 10:12:10 -0500461 * BOOTP options
462 */
463#define CONFIG_BOOTP_BOOTFILESIZE
464#define CONFIG_BOOTP_BOOTPATH
465#define CONFIG_BOOTP_GATEWAY
466#define CONFIG_BOOTP_HOSTNAME
467
Jon Loeliger5c4ddae2007-07-10 10:12:10 -0500468/*
Jon Loeliger3b7116d2007-07-04 22:30:06 -0500469 * Command line configuration.
470 */
Jon Loeliger3b7116d2007-07-04 22:30:06 -0500471#define CONFIG_CMD_DATE
472#define CONFIG_CMD_PCI
Scott Wood865b8ae2007-04-16 14:54:15 -0500473
Jon Loeliger3b7116d2007-07-04 22:30:06 -0500474#define CONFIG_CMDLINE_EDITING 1
Kim Phillips26c16d82010-04-15 17:36:05 -0500475#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Scott Wood865b8ae2007-04-16 14:54:15 -0500476
477/*
478 * Miscellaneous configurable options
479 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200480#define CONFIG_SYS_LONGHELP /* undef to save memory */
481#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200482#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Scott Wood865b8ae2007-04-16 14:54:15 -0500483
Joe Hershbergerb263cae2011-10-11 23:57:10 -0500484 /* Print Buffer Size */
485#define CONFIG_SYS_PBSIZE \
486 (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
487#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
488 /* Boot Argument Buffer Size */
489#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
Scott Wood865b8ae2007-04-16 14:54:15 -0500490
491/*
492 * For booting Linux, the board info and command line data
Ira W. Snyderc5a22d02010-09-10 15:42:32 -0700493 * have to be in the first 256 MB of memory, since this is
Scott Wood865b8ae2007-04-16 14:54:15 -0500494 * the maximum mapped by the Linux kernel during initialization.
495 */
Joe Hershbergerb263cae2011-10-11 23:57:10 -0500496 /* Initial Memory map for Linux*/
497#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
Kevin Hao9c747962016-07-08 11:25:15 +0800498#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
Scott Wood865b8ae2007-04-16 14:54:15 -0500499
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200500#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
Scott Wood865b8ae2007-04-16 14:54:15 -0500501
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200502#ifdef CONFIG_SYS_66MHZ
Scott Wood865b8ae2007-04-16 14:54:15 -0500503
504/* 66MHz IN, 133MHz CSB, 266 DDR, 266 CORE */
505/* 0x62040000 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200506#define CONFIG_SYS_HRCW_LOW (\
Scott Wood865b8ae2007-04-16 14:54:15 -0500507 0x20000000 /* reserved, must be set */ |\
508 HRCWL_DDRCM |\
509 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
510 HRCWL_DDR_TO_SCB_CLK_2X1 |\
511 HRCWL_CSB_TO_CLKIN_2X1 |\
512 HRCWL_CORE_TO_CSB_2X1)
513
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200514#define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2)
Scott Woodb71689b2008-06-30 14:13:28 -0500515
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200516#elif defined(CONFIG_SYS_33MHZ)
Scott Wood865b8ae2007-04-16 14:54:15 -0500517
518/* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */
519/* 0x65040000 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200520#define CONFIG_SYS_HRCW_LOW (\
Scott Wood865b8ae2007-04-16 14:54:15 -0500521 0x20000000 /* reserved, must be set */ |\
522 HRCWL_DDRCM |\
523 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
524 HRCWL_DDR_TO_SCB_CLK_2X1 |\
525 HRCWL_CSB_TO_CLKIN_5X1 |\
526 HRCWL_CORE_TO_CSB_2X1)
527
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200528#define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 5)
Scott Woodb71689b2008-06-30 14:13:28 -0500529
Scott Wood865b8ae2007-04-16 14:54:15 -0500530#endif
531
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200532#define CONFIG_SYS_HRCW_HIGH_BASE (\
Scott Wood865b8ae2007-04-16 14:54:15 -0500533 HRCWH_PCI_HOST |\
534 HRCWH_PCI1_ARBITER_ENABLE |\
535 HRCWH_CORE_ENABLE |\
Scott Wood865b8ae2007-04-16 14:54:15 -0500536 HRCWH_BOOTSEQ_DISABLE |\
537 HRCWH_SW_WATCHDOG_DISABLE |\
Scott Wood865b8ae2007-04-16 14:54:15 -0500538 HRCWH_TSEC1M_IN_RGMII |\
539 HRCWH_TSEC2M_IN_RGMII |\
Scott Woodb71689b2008-06-30 14:13:28 -0500540 HRCWH_BIG_ENDIAN)
541
Scott Wood488af0d2012-12-06 13:33:18 +0000542#ifdef CONFIG_NAND
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200543#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
Wolfgang Denk74e0dde2008-08-14 14:41:06 +0200544 HRCWH_FROM_0XFFF00100 |\
545 HRCWH_ROM_LOC_NAND_SP_8BIT |\
546 HRCWH_RL_EXT_NAND)
Scott Woodb71689b2008-06-30 14:13:28 -0500547#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200548#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
Wolfgang Denk74e0dde2008-08-14 14:41:06 +0200549 HRCWH_FROM_0X00000100 |\
550 HRCWH_ROM_LOC_LOCAL_16BIT |\
551 HRCWH_RL_EXT_LEGACY)
Scott Woodb71689b2008-06-30 14:13:28 -0500552#endif
Scott Wood865b8ae2007-04-16 14:54:15 -0500553
554/* System IO Config */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200555#define CONFIG_SYS_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */
Joe Hershberger37dabcc2011-11-11 15:55:38 -0600556 /* Enable Internal USB Phy and GPIO on LCD Connector */
557#define CONFIG_SYS_SICRL (SICRL_USBDR_10 | SICRL_LBC)
Scott Wood865b8ae2007-04-16 14:54:15 -0500558
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200559#define CONFIG_SYS_HID0_INIT 0x000000000
560#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
Kim Phillipsf3c7cd92010-04-20 19:37:54 -0500561 HID0_ENABLE_INSTRUCTION_CACHE | \
562 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
Scott Wood865b8ae2007-04-16 14:54:15 -0500563
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200564#define CONFIG_SYS_HID2 HID2_HBE
Scott Wood865b8ae2007-04-16 14:54:15 -0500565
Becky Bruce03ea1be2008-05-08 19:02:12 -0500566#define CONFIG_HIGH_BATS 1 /* High BATs supported */
567
Scott Wood865b8ae2007-04-16 14:54:15 -0500568/* DDR @ 0x00000000 */
Joe Hershbergerbfd89732011-10-11 23:57:28 -0500569#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW)
Joe Hershbergerb263cae2011-10-11 23:57:10 -0500570#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
571 | BATU_BL_256M \
572 | BATU_VS \
573 | BATU_VP)
Scott Wood865b8ae2007-04-16 14:54:15 -0500574
575/* PCI @ 0x80000000 */
Joe Hershbergerbfd89732011-10-11 23:57:28 -0500576#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW)
Joe Hershbergerb263cae2011-10-11 23:57:10 -0500577#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \
578 | BATU_BL_256M \
579 | BATU_VS \
580 | BATU_VP)
581#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \
Joe Hershbergerbfd89732011-10-11 23:57:28 -0500582 | BATL_PP_RW \
Joe Hershbergerb263cae2011-10-11 23:57:10 -0500583 | BATL_CACHEINHIBIT \
584 | BATL_GUARDEDSTORAGE)
585#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \
586 | BATU_BL_256M \
587 | BATU_VS \
588 | BATU_VP)
Scott Wood865b8ae2007-04-16 14:54:15 -0500589
590/* PCI2 not supported on 8313 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200591#define CONFIG_SYS_IBAT3L (0)
592#define CONFIG_SYS_IBAT3U (0)
593#define CONFIG_SYS_IBAT4L (0)
594#define CONFIG_SYS_IBAT4U (0)
Scott Wood865b8ae2007-04-16 14:54:15 -0500595
596/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
Joe Hershbergerb263cae2011-10-11 23:57:10 -0500597#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
Joe Hershbergerbfd89732011-10-11 23:57:28 -0500598 | BATL_PP_RW \
Joe Hershbergerb263cae2011-10-11 23:57:10 -0500599 | BATL_CACHEINHIBIT \
600 | BATL_GUARDEDSTORAGE)
601#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
602 | BATU_BL_256M \
603 | BATU_VS \
604 | BATU_VP)
Scott Wood865b8ae2007-04-16 14:54:15 -0500605
606/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
Joe Hershbergerbfd89732011-10-11 23:57:28 -0500607#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200608#define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
Scott Wood865b8ae2007-04-16 14:54:15 -0500609
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200610#define CONFIG_SYS_IBAT7L (0)
611#define CONFIG_SYS_IBAT7U (0)
Scott Wood865b8ae2007-04-16 14:54:15 -0500612
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200613#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
614#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
615#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
616#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
617#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
618#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
619#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
620#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
621#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
622#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
623#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
624#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
625#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
626#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
627#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
628#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
Scott Wood865b8ae2007-04-16 14:54:15 -0500629
630/*
Scott Wood865b8ae2007-04-16 14:54:15 -0500631 * Environment Configuration
632 */
633#define CONFIG_ENV_OVERWRITE
634
Joe Hershbergerb263cae2011-10-11 23:57:10 -0500635#define CONFIG_NETDEV "eth1"
Scott Wood865b8ae2007-04-16 14:54:15 -0500636
637#define CONFIG_HOSTNAME mpc8313erdb
Joe Hershberger257ff782011-10-13 13:03:47 +0000638#define CONFIG_ROOTPATH "/nfs/root/path"
Joe Hershbergere4da2482011-10-13 13:03:48 +0000639#define CONFIG_BOOTFILE "uImage"
Joe Hershbergerb263cae2011-10-11 23:57:10 -0500640 /* U-Boot image on TFTP server */
641#define CONFIG_UBOOTPATH "u-boot.bin"
642#define CONFIG_FDTFILE "mpc8313erdb.dtb"
Scott Wood865b8ae2007-04-16 14:54:15 -0500643
Joe Hershbergerb263cae2011-10-11 23:57:10 -0500644 /* default location for tftp and bootm */
645#define CONFIG_LOADADDR 800000
Scott Wood865b8ae2007-04-16 14:54:15 -0500646
Scott Wood865b8ae2007-04-16 14:54:15 -0500647#define CONFIG_EXTRA_ENV_SETTINGS \
Joe Hershbergerb263cae2011-10-11 23:57:10 -0500648 "netdev=" CONFIG_NETDEV "\0" \
Scott Wood865b8ae2007-04-16 14:54:15 -0500649 "ethprime=TSEC1\0" \
Joe Hershbergerb263cae2011-10-11 23:57:10 -0500650 "uboot=" CONFIG_UBOOTPATH "\0" \
Wolfgang Denka1be4762008-05-20 16:00:29 +0200651 "tftpflash=tftpboot $loadaddr $uboot; " \
Marek Vasut0b3176c2012-09-23 17:41:24 +0200652 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
653 " +$filesize; " \
654 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
655 " +$filesize; " \
656 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
657 " $filesize; " \
658 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
659 " +$filesize; " \
660 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
661 " $filesize\0" \
Kim Phillipsfd3a3fc2009-08-21 16:34:38 -0500662 "fdtaddr=780000\0" \
Joe Hershbergerb263cae2011-10-11 23:57:10 -0500663 "fdtfile=" CONFIG_FDTFILE "\0" \
Scott Wood865b8ae2007-04-16 14:54:15 -0500664 "console=ttyS0\0" \
665 "setbootargs=setenv bootargs " \
666 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
Wolfgang Denka1be4762008-05-20 16:00:29 +0200667 "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
Joe Hershbergerb263cae2011-10-11 23:57:10 -0500668 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
669 "$netdev:off " \
Scott Wood865b8ae2007-04-16 14:54:15 -0500670 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
671
672#define CONFIG_NFSBOOTCOMMAND \
673 "setenv rootdev /dev/nfs;" \
Wolfgang Denka1be4762008-05-20 16:00:29 +0200674 "run setbootargs;" \
675 "run setipargs;" \
Scott Wood865b8ae2007-04-16 14:54:15 -0500676 "tftp $loadaddr $bootfile;" \
677 "tftp $fdtaddr $fdtfile;" \
678 "bootm $loadaddr - $fdtaddr"
679
680#define CONFIG_RAMBOOTCOMMAND \
681 "setenv rootdev /dev/ram;" \
682 "run setbootargs;" \
683 "tftp $ramdiskaddr $ramdiskfile;" \
684 "tftp $loadaddr $bootfile;" \
685 "tftp $fdtaddr $fdtfile;" \
686 "bootm $loadaddr $ramdiskaddr $fdtaddr"
687
Scott Wood865b8ae2007-04-16 14:54:15 -0500688#endif /* __CONFIG_H */