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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0 */
Vladimir Barinovc8c1a3e2015-01-12 19:17:07 +03002/*
3 * include/configs/silk.h
4 * This file is silk board configuration.
5 *
6 * Copyright (C) 2015 Renesas Electronics Corporation
7 * Copyright (C) 2015 Cogent Embedded, Inc.
Vladimir Barinovc8c1a3e2015-01-12 19:17:07 +03008 */
9
10#ifndef __SILK_H
11#define __SILK_H
12
Vladimir Barinovc8c1a3e2015-01-12 19:17:07 +030013#include "rcar-gen2-common.h"
14
Marek Vasut52e0ee32018-04-21 16:19:56 +020015#define STACK_AREA_SIZE 0x00100000
Vladimir Barinovc8c1a3e2015-01-12 19:17:07 +030016#define LOW_LEVEL_MERAM_STACK \
Tom Rini4ddbade2022-05-25 12:16:03 -040017 (SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
Vladimir Barinovc8c1a3e2015-01-12 19:17:07 +030018
19/* MEMORY */
20#define RCAR_GEN2_SDRAM_BASE 0x40000000
21#define RCAR_GEN2_SDRAM_SIZE (1024u * 1024 * 1024)
22#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024)
23
Vladimir Barinovc8c1a3e2015-01-12 19:17:07 +030024/* FLASH */
Vladimir Barinovc8c1a3e2015-01-12 19:17:07 +030025#define CONFIG_SPI_FLASH_QUAD
Vladimir Barinovc8c1a3e2015-01-12 19:17:07 +030026
27/* SH Ether */
Vladimir Barinovc8c1a3e2015-01-12 19:17:07 +030028#define CONFIG_SH_ETHER_USE_PORT 0
29#define CONFIG_SH_ETHER_PHY_ADDR 0x1
30#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
31#define CONFIG_SH_ETHER_CACHE_WRITEBACK
32#define CONFIG_SH_ETHER_CACHE_INVALIDATE
33#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
Vladimir Barinovc8c1a3e2015-01-12 19:17:07 +030034
35/* Board Clock */
Vladimir Barinovc8c1a3e2015-01-12 19:17:07 +030036
Marek Vasut52e0ee32018-04-21 16:19:56 +020037#define CONFIG_EXTRA_ENV_SETTINGS \
Marek Vasut4f34a4b2018-11-27 00:19:03 +010038 "bootm_size=0x10000000\0"
Vladimir Barinovc8c1a3e2015-01-12 19:17:07 +030039
Marek Vasut52e0ee32018-04-21 16:19:56 +020040/* SPL support */
Vladimir Barinovc8c1a3e2015-01-12 19:17:07 +030041
42#endif /* __SILK_H */