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Vladimir Barinovc8c1a3e2015-01-12 19:17:07 +03001/*
2 * include/configs/silk.h
3 * This file is silk board configuration.
4 *
5 * Copyright (C) 2015 Renesas Electronics Corporation
6 * Copyright (C) 2015 Cogent Embedded, Inc.
7 *
8 * SPDX-License-Identifier: GPL-2.0
9 */
10
11#ifndef __SILK_H
12#define __SILK_H
13
14#undef DEBUG
Nobuhiro Iwamatsu7c112732015-10-10 05:58:28 +090015#define CONFIG_ARCH_RMOBILE_BOARD_STRING "Silk"
Vladimir Barinovc8c1a3e2015-01-12 19:17:07 +030016
17#include "rcar-gen2-common.h"
18
Marek Vasut52e0ee32018-04-21 16:19:56 +020019#define CONFIG_SYS_INIT_SP_ADDR 0x4f000000
20#define STACK_AREA_SIZE 0x00100000
Vladimir Barinovc8c1a3e2015-01-12 19:17:07 +030021#define LOW_LEVEL_MERAM_STACK \
22 (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
23
24/* MEMORY */
25#define RCAR_GEN2_SDRAM_BASE 0x40000000
26#define RCAR_GEN2_SDRAM_SIZE (1024u * 1024 * 1024)
27#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024)
28
29/* SCIF */
Vladimir Barinovc8c1a3e2015-01-12 19:17:07 +030030
31/* FLASH */
32#define CONFIG_SPI
Vladimir Barinovc8c1a3e2015-01-12 19:17:07 +030033#define CONFIG_SPI_FLASH_QUAD
Vladimir Barinovc8c1a3e2015-01-12 19:17:07 +030034
35/* SH Ether */
Vladimir Barinovc8c1a3e2015-01-12 19:17:07 +030036#define CONFIG_SH_ETHER_USE_PORT 0
37#define CONFIG_SH_ETHER_PHY_ADDR 0x1
38#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
39#define CONFIG_SH_ETHER_CACHE_WRITEBACK
40#define CONFIG_SH_ETHER_CACHE_INVALIDATE
41#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
Vladimir Barinovc8c1a3e2015-01-12 19:17:07 +030042#define CONFIG_BITBANGMII
43#define CONFIG_BITBANGMII_MULTI
44
45/* Board Clock */
46#define RMOBILE_XTAL_CLK 20000000u
47#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
Marek Vasut52e0ee32018-04-21 16:19:56 +020048#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2)
Vladimir Barinovc8c1a3e2015-01-12 19:17:07 +030049
Marek Vasut52e0ee32018-04-21 16:19:56 +020050#define CONFIG_SYS_TMU_CLK_DIV 4
Vladimir Barinovc8c1a3e2015-01-12 19:17:07 +030051
Marek Vasut52e0ee32018-04-21 16:19:56 +020052#define CONFIG_EXTRA_ENV_SETTINGS \
53 "fdt_high=0xffffffff\0" \
54 "initrd_high=0xffffffff\0"
Vladimir Barinovc8c1a3e2015-01-12 19:17:07 +030055
Marek Vasut52e0ee32018-04-21 16:19:56 +020056/* SPL support */
57#define CONFIG_SPL_TEXT_BASE 0xe6300000
58#define CONFIG_SPL_STACK 0xe6340000
59#define CONFIG_SPL_MAX_SIZE 0x4000
60#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x140000
61#ifdef CONFIG_SPL_BUILD
62#define CONFIG_CONS_SCIF2
63#define CONFIG_SH_SCIF_CLK_FREQ 65000000
64#endif
Vladimir Barinovc8c1a3e2015-01-12 19:17:07 +030065
66#endif /* __SILK_H */