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git01.mediatek.com / filogic / uboot / a1fa5cbbc00b663f074408045fc0460b0d04603d / . / arch / arm / dts / imx8mm-data-modul-edm-sbc-u-boot.dtsi
blob: 3a4f7d01b9e9917ac57a96fa51b2ccbe36afd126 [file] [log] [blame]
Marek Vasut0b16ba52022-04-12 17:26:01 +0200[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2022 Marek Vasut <marex@denx.de>
4 */
5
6#include "imx8mm-u-boot.dtsi"
7
8/ {
9 aliases {
10 eeprom0 = &eeprom;
11 mmc0 = &usdhc3; /* eMMC */
12 mmc1 = &usdhc2; /* MicroSD */
13 };
14
15 config {
16 dmo,ram-coding-gpios = <&gpio2 8 0>, <&gpio2 1 0>, <&gpio2 0 0>;
17 };
18
Marek Vasut97327e32024-11-29 01:35:43 +0100[diff] [blame]19 clk_pcie100: clk-pcie100 {
20 compatible = "fixed-clock";
21 #clock-cells = <0>;
22 clock-frequency = <100000000>;
23 };
24
Marek Vasut0b16ba52022-04-12 17:26:01 +0200[diff] [blame]25 wdt-reboot {
26 compatible = "wdt-reboot";
27 wdt = <&wdog1>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]28 bootph-pre-ram;
Marek Vasut0b16ba52022-04-12 17:26:01 +0200[diff] [blame]29 };
30};
31
32&buck4_reg {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]33 bootph-pre-ram;
Marek Vasut0b16ba52022-04-12 17:26:01 +0200[diff] [blame]34};
35
36&buck5_reg {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]37 bootph-pre-ram;
Marek Vasut0b16ba52022-04-12 17:26:01 +0200[diff] [blame]38};
39
40&i2c1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]41 bootph-pre-ram;
Marek Vasut0b16ba52022-04-12 17:26:01 +0200[diff] [blame]42};
43
Marek Vasut97327e32024-11-29 01:35:43 +0100[diff] [blame]44&pcie_phy {
45 clocks = <&clk_pcie100>;
46};
47
48&pcie0 {
49 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
50 <&clk_pcie100>;
51};
52
Marek Vasut0b16ba52022-04-12 17:26:01 +0200[diff] [blame]53&pinctrl_hog_sbc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]54 bootph-pre-ram;
Marek Vasut0b16ba52022-04-12 17:26:01 +0200[diff] [blame]55};
56
57&pinctrl_i2c1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]58 bootph-pre-ram;
Marek Vasut0b16ba52022-04-12 17:26:01 +0200[diff] [blame]59};
60
61&pinctrl_i2c1_gpio {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]62 bootph-pre-ram;
Marek Vasut0b16ba52022-04-12 17:26:01 +0200[diff] [blame]63};
64
65&pinctrl_pmic {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]66 bootph-pre-ram;
Marek Vasut0b16ba52022-04-12 17:26:01 +0200[diff] [blame]67};
68
69&pinctrl_uart3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]70 bootph-pre-ram;
Marek Vasut0b16ba52022-04-12 17:26:01 +0200[diff] [blame]71};
72
73&pinctrl_usdhc2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]74 bootph-pre-ram;
Marek Vasut0b16ba52022-04-12 17:26:01 +0200[diff] [blame]75};
76
77&pinctrl_usdhc3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]78 bootph-pre-ram;
Marek Vasut0b16ba52022-04-12 17:26:01 +0200[diff] [blame]79};
80
81&pmic {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]82 bootph-pre-ram;
Marek Vasut0b16ba52022-04-12 17:26:01 +0200[diff] [blame]83
84 regulators {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]85 bootph-pre-ram;
Marek Vasut0b16ba52022-04-12 17:26:01 +0200[diff] [blame]86 };
87};
88
89&gpio1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]90 bootph-pre-ram;
Marek Vasut0b16ba52022-04-12 17:26:01 +0200[diff] [blame]91};
92
93&gpio2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]94 bootph-pre-ram;
Marek Vasutd6e46182024-11-29 01:13:53 +0100[diff] [blame]95 bootph-some-ram;
Marek Vasut602accd2023-12-18 19:02:14 +0100[diff] [blame]96
97 dsi-reset-hog {
98 bootph-pre-ram;
99 gpio-hog;
100 output-high;
101 gpios = <2 GPIO_ACTIVE_LOW>;
102 line-name = "DSI_RESET_1V8#";
103 };
104
105
106 dsi-irq-hog {
107 bootph-pre-ram;
108 gpio-hog;
109 input;
110 gpios = <3 GPIO_ACTIVE_LOW>;
111 line-name = "DSI_IRQ_1V8#";
112 };
113
114 graphics-prsnt-hog {
115 bootph-pre-ram;
116 gpio-hog;
117 input;
118 gpios = <7 GPIO_ACTIVE_LOW>;
119 line-name = "GRAPHICS_PRSNT_1V8#";
120 };
Marek Vasut0b16ba52022-04-12 17:26:01 +0200[diff] [blame]121};
122
123&gpio3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]124 bootph-pre-ram;
Marek Vasut602accd2023-12-18 19:02:14 +0100[diff] [blame]125
126 bl-enable-hog {
127 bootph-pre-ram;
128 gpio-hog;
129 output-low;
130 gpios = <0 GPIO_ACTIVE_HIGH>;
131 line-name = "BL_ENABLE_1V8";
132 };
133
134 tft-enable-hog {
135 bootph-pre-ram;
136 gpio-hog;
137 output-low;
138 gpios = <6 GPIO_ACTIVE_HIGH>;
139 line-name = "TFT_ENABLE_1V8";
140 };
141
142 graphics-gpio0-hog {
143 bootph-pre-ram;
144 gpio-hog;
145 input;
146 gpios = <7 GPIO_ACTIVE_HIGH>;
147 line-name = "GRAPHICS_GPIO0_1V8";
148 };
Marek Vasut0b16ba52022-04-12 17:26:01 +0200[diff] [blame]149};
150
151&gpio4 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]152 bootph-pre-ram;
Marek Vasut0b16ba52022-04-12 17:26:01 +0200[diff] [blame]153};
154
155&gpio5 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]156 bootph-pre-ram;
Marek Vasut0b16ba52022-04-12 17:26:01 +0200[diff] [blame]157};
158
159&uart3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]160 bootph-pre-ram;
Marek Vasut0b16ba52022-04-12 17:26:01 +0200[diff] [blame]161};
162
Marek Vasut61e60002024-11-29 03:41:47 +0100[diff] [blame]163&usbmisc1 {
164 bootph-pre-ram;
165};
166
167&usbphynop1 {
168 bootph-pre-ram;
169};
170
Marek Vasut0b16ba52022-04-12 17:26:01 +0200[diff] [blame]171&usbotg1 {
172 dr_mode = "peripheral";
Marek Vasut61e60002024-11-29 03:41:47 +0100[diff] [blame]173 bootph-pre-ram;
Marek Vasut0b16ba52022-04-12 17:26:01 +0200[diff] [blame]174};
175
176&usdhc2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]177 bootph-pre-ram;
Marek Vasut0b16ba52022-04-12 17:26:01 +0200[diff] [blame]178 sd-uhs-sdr104;
179 sd-uhs-ddr50;
180};
181
182&usdhc3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]183 bootph-pre-ram;
Marek Vasut0b16ba52022-04-12 17:26:01 +0200[diff] [blame]184 mmc-hs400-1_8v;
185 mmc-hs400-enhanced-strobe;
186};
187
188&wdog1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]189 bootph-pre-ram;
Marek Vasut0b16ba52022-04-12 17:26:01 +0200[diff] [blame]190};