Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / d6e46184315d4e8ef401645ecab57715729dda91 / . / arch / arm / dts / imx8mm-data-modul-edm-sbc-u-boot.dtsi
blob: fb6951026d960aefd45b97318ddc074a76361f93 [file] [log] [blame]
Marek Vasut0b16ba52022-04-12 17:26:01 +0200[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2022 Marek Vasut <marex@denx.de>
4 */
5
6#include "imx8mm-u-boot.dtsi"
7
8/ {
9 aliases {
10 eeprom0 = &eeprom;
11 mmc0 = &usdhc3; /* eMMC */
12 mmc1 = &usdhc2; /* MicroSD */
13 };
14
15 config {
16 dmo,ram-coding-gpios = <&gpio2 8 0>, <&gpio2 1 0>, <&gpio2 0 0>;
17 };
18
19 wdt-reboot {
20 compatible = "wdt-reboot";
21 wdt = <&wdog1>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]22 bootph-pre-ram;
Marek Vasut0b16ba52022-04-12 17:26:01 +0200[diff] [blame]23 };
24};
25
26&buck4_reg {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]27 bootph-pre-ram;
Marek Vasut0b16ba52022-04-12 17:26:01 +0200[diff] [blame]28};
29
30&buck5_reg {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]31 bootph-pre-ram;
Marek Vasut0b16ba52022-04-12 17:26:01 +0200[diff] [blame]32};
33
34&i2c1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]35 bootph-pre-ram;
Marek Vasut0b16ba52022-04-12 17:26:01 +0200[diff] [blame]36};
37
38&pinctrl_hog_sbc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]39 bootph-pre-ram;
Marek Vasut0b16ba52022-04-12 17:26:01 +0200[diff] [blame]40};
41
42&pinctrl_i2c1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]43 bootph-pre-ram;
Marek Vasut0b16ba52022-04-12 17:26:01 +0200[diff] [blame]44};
45
46&pinctrl_i2c1_gpio {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]47 bootph-pre-ram;
Marek Vasut0b16ba52022-04-12 17:26:01 +0200[diff] [blame]48};
49
50&pinctrl_pmic {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]51 bootph-pre-ram;
Marek Vasut0b16ba52022-04-12 17:26:01 +0200[diff] [blame]52};
53
54&pinctrl_uart3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]55 bootph-pre-ram;
Marek Vasut0b16ba52022-04-12 17:26:01 +0200[diff] [blame]56};
57
58&pinctrl_usdhc2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]59 bootph-pre-ram;
Marek Vasut0b16ba52022-04-12 17:26:01 +0200[diff] [blame]60};
61
62&pinctrl_usdhc3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]63 bootph-pre-ram;
Marek Vasut0b16ba52022-04-12 17:26:01 +0200[diff] [blame]64};
65
66&pmic {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]67 bootph-pre-ram;
Marek Vasut0b16ba52022-04-12 17:26:01 +0200[diff] [blame]68
69 regulators {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]70 bootph-pre-ram;
Marek Vasut0b16ba52022-04-12 17:26:01 +0200[diff] [blame]71 };
72};
73
74&gpio1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]75 bootph-pre-ram;
Marek Vasut0b16ba52022-04-12 17:26:01 +0200[diff] [blame]76};
77
78&gpio2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]79 bootph-pre-ram;
Marek Vasutd6e46182024-11-29 01:13:53 +0100[diff] [blame^]80 bootph-some-ram;
Marek Vasut602accd2023-12-18 19:02:14 +0100[diff] [blame]81
82 dsi-reset-hog {
83 bootph-pre-ram;
84 gpio-hog;
85 output-high;
86 gpios = <2 GPIO_ACTIVE_LOW>;
87 line-name = "DSI_RESET_1V8#";
88 };
89
90
91 dsi-irq-hog {
92 bootph-pre-ram;
93 gpio-hog;
94 input;
95 gpios = <3 GPIO_ACTIVE_LOW>;
96 line-name = "DSI_IRQ_1V8#";
97 };
98
99 graphics-prsnt-hog {
100 bootph-pre-ram;
101 gpio-hog;
102 input;
103 gpios = <7 GPIO_ACTIVE_LOW>;
104 line-name = "GRAPHICS_PRSNT_1V8#";
105 };
Marek Vasut0b16ba52022-04-12 17:26:01 +0200[diff] [blame]106};
107
108&gpio3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]109 bootph-pre-ram;
Marek Vasut602accd2023-12-18 19:02:14 +0100[diff] [blame]110
111 bl-enable-hog {
112 bootph-pre-ram;
113 gpio-hog;
114 output-low;
115 gpios = <0 GPIO_ACTIVE_HIGH>;
116 line-name = "BL_ENABLE_1V8";
117 };
118
119 tft-enable-hog {
120 bootph-pre-ram;
121 gpio-hog;
122 output-low;
123 gpios = <6 GPIO_ACTIVE_HIGH>;
124 line-name = "TFT_ENABLE_1V8";
125 };
126
127 graphics-gpio0-hog {
128 bootph-pre-ram;
129 gpio-hog;
130 input;
131 gpios = <7 GPIO_ACTIVE_HIGH>;
132 line-name = "GRAPHICS_GPIO0_1V8";
133 };
Marek Vasut0b16ba52022-04-12 17:26:01 +0200[diff] [blame]134};
135
136&gpio4 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]137 bootph-pre-ram;
Marek Vasut0b16ba52022-04-12 17:26:01 +0200[diff] [blame]138};
139
140&gpio5 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]141 bootph-pre-ram;
Marek Vasut0b16ba52022-04-12 17:26:01 +0200[diff] [blame]142};
143
144&uart3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]145 bootph-pre-ram;
Marek Vasut0b16ba52022-04-12 17:26:01 +0200[diff] [blame]146};
147
148&usbotg1 {
149 dr_mode = "peripheral";
150};
151
152&usdhc2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]153 bootph-pre-ram;
Marek Vasut0b16ba52022-04-12 17:26:01 +0200[diff] [blame]154 sd-uhs-sdr104;
155 sd-uhs-ddr50;
156};
157
158&usdhc3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]159 bootph-pre-ram;
Marek Vasut0b16ba52022-04-12 17:26:01 +0200[diff] [blame]160 mmc-hs400-1_8v;
161 mmc-hs400-enhanced-strobe;
162};
163
164&wdog1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]165 bootph-pre-ram;
Marek Vasut0b16ba52022-04-12 17:26:01 +0200[diff] [blame]166};