arch/arm/dts/socfpga_agilex5.dtsi

// SPDX-License-Identifier:     GPL-2.0
/*
 * Copyright (C) 2024 Intel Corporation <www.intel.com>
 * Copyright (C) 2025 Altera Corporation <www.altera.com>
 */

/dts-v1/;
#include <dt-bindings/reset/altr,rst-mgr-agx5.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/agilex5-clock.h>

/ {
	compatible = "intel,socfpga-agilex";
	#address-cells = <2>;
	#size-cells = <2>;

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		service_reserved: svcbuffer@0 {
			compatible = "shared-dma-pool";
			reg = <0x0 0x0 0x0 0x1000000>;
			alignment = <0x1000>;
			no-map;
		};
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			compatible = "arm,cortex-a55";
			device_type = "cpu";
			enable-method = "psci";
			reg = <0x0>;
		};

		cpu1: cpu@1 {
			compatible = "arm,cortex-a55";
			device_type = "cpu";
			enable-method = "psci";
			reg = <0x1>;
		};

		cpu2: cpu@2 {
			compatible = "arm,cortex-a76";
			device_type = "cpu";
			enable-method = "psci";
			reg = <0x2>;
		};

		cpu3: cpu@3 {
			compatible = "arm,cortex-a76";
			device_type = "cpu";
			enable-method = "psci";
			reg = <0x3>;
		};
	};

	pmu {
		compatible = "arm,armv8-pmuv3";
		interrupts = <0 170 4>,
			     <0 171 4>,
			     <0 172 4>,
			     <0 173 4>;
		interrupt-affinity = <&cpu0>,
				     <&cpu1>,
				     <&cpu2>,
				     <&cpu3>;
		interrupt-parent = <&intc>;
	};

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	intc: intc@fffc1000 {
		compatible = "arm,gic-400", "arm,cortex-a15-gic";
		#interrupt-cells = <3>;
		interrupt-controller;
		reg = <0x0 0x1d000000 0x0 0x10000>;
	};

	soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		device_type = "soc";
		interrupt-parent = <&intc>;
		ranges = <0 0 0 0xffffffff>;

		base_fpga_region {
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			compatible = "fpga-region";
			fpga-mgr = <&fpga_mgr>;
		};

		clkmgr: clock-controller@10d10000 {
			compatible = "intel,agilex5-clkmgr";
			reg = <0x10d10000 0x1000>;
			#clock-cells = <1>;
		};

		clocks {
			cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk {
				#clock-cells = <0>;
				compatible = "fixed-clock";
			};

			cb_intosc_ls_clk: cb-intosc-ls-clk {
				#clock-cells = <0>;
				compatible = "fixed-clock";
			};

			f2s_free_clk: f2s-free-clk {
				#clock-cells = <0>;
				compatible = "fixed-clock";
			};

			osc1: osc1 {
				#clock-cells = <0>;
				compatible = "fixed-clock";
			};

			qspi_clk: qspi-clk {
				#clock-cells = <0>;
				compatible = "fixed-clock";
				clock-frequency = <200000000>;
			};
		};
		gmac0: ethernet@10810000 {
			compatible = "intel,socfpga-dwxgmac", "snps,dwxgmac-2.10", "snps,dwxgmac";
			reg = <0x10810000 0x3500>;
			interrupts = <0 190 4>;
			interrupt-names = "macirq";
			mac-address = [00 00 00 00 00 00];
			resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
			reset-names = "stmmaceth", "stmmaceth-ocp";
			tx-fifo-depth = <32768>;
			rx-fifo-depth = <16384>;
			iommus = <&smmu 1>;
			altr,sysmgr-syscon = <&sysmgr 0x44 0>;
			clocks = <&clkmgr AGILEX5_EMAC0_CLK>;
			clock-names = "stmmaceth";
			status = "disabled";
		};

		gmac1: ethernet@10820000 {
			compatible = "intel,socfpga-dwxgmac", "snps,dwxgmac-2.10", "snps,dwxgmac";
			reg = <0x10820000 0x3500>;
			interrupts = <0 207 4>;
			interrupt-names = "macirq";
			mac-address = [00 00 00 00 00 00];
			resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
			reset-names = "stmmaceth", "stmmaceth-ocp";
			tx-fifo-depth = <32768>;
			rx-fifo-depth = <16384>;
			iommus = <&smmu 2>;
			altr,sysmgr-syscon = <&sysmgr 0x48 0>;
			clocks = <&clkmgr AGILEX5_EMAC1_CLK>;
			clock-names = "stmmaceth";
			status = "disabled";
		};

		gmac2: ethernet@10830000 {
			compatible = "intel,socfpga-dwxgmac", "snps,dwxgmac-2.10", "snps,dwxgmac";
			reg = <0x10830000 0x3500>;
			interrupts = <0 224 4>;
			interrupt-names = "macirq";
			mac-address = [00 00 00 00 00 00];
			resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
			reset-names = "stmmaceth", "stmmaceth-ocp";
			tx-fifo-depth = <32768>;
			rx-fifo-depth = <16384>;
			iommus = <&smmu 3>;
			altr,sysmgr-syscon = <&sysmgr 0x4c 0>;
			clocks = <&clkmgr AGILEX5_EMAC2_CLK>;
			clock-names = "stmmaceth";
			status = "disabled";
		};

		gpio0: gpio@10c03200 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,dw-apb-gpio";
			reg = <0x10c03200 0x80>;
			resets = <&rst GPIO0_RESET>;
			status = "disabled";

			porta: gpio-controller@0 {
				compatible = "snps,dw-apb-gpio-port";
				gpio-controller;
				#gpio-cells = <2>;
				snps,nr-gpios = <24>;
				reg = <0>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <0 110 4>;
			};
		};

		gpio1: gpio@10c03300 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,dw-apb-gpio";
			reg = <0x10c03300 0x80>;
			resets = <&rst GPIO1_RESET>;
			status = "disabled";

			portb: gpio-controller@0 {
				compatible = "snps,dw-apb-gpio-port";
				gpio-controller;
				#gpio-cells = <2>;
				snps,nr-gpios = <24>;
				reg = <0>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <0 111 4>;
			};
		};

		i2c0: i2c@10c02800 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,designware-i2c";
			reg = <0x10c02800 0x100>;
			interrupts = <0 103 4>;
			resets = <&rst I2C0_RESET>;
			clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
			status = "disabled";
		};

		i2c1: i2c@10c02900 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,designware-i2c";
			reg = <0x10c02900 0x100>;
			interrupts = <0 104 4>;
			resets = <&rst I2C1_RESET>;
			clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
			status = "disabled";
		};

		i2c2: i2c@10c02a00 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,designware-i2c";
			reg = <0x10c02a00 0x100>;
			interrupts = <0 105 4>;
			resets = <&rst I2C2_RESET>;
			clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
			status = "disabled";
		};

		i2c3: i2c@10c02b00 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,designware-i2c";
			reg = <0x10c02b00 0x100>;
			interrupts = <0 106 4>;
			resets = <&rst I2C3_RESET>;
			clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
			status = "disabled";
		};

		i2c4: i2c@10c02c00 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,designware-i2c";
			reg = <0x10c02c00 0x100>;
			interrupts = <0 107 4>;
			resets = <&rst I2C4_RESET>;
			clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
			status = "disabled";
		};

		i3c0: i3c@10da0000 {
			compatible = "snps,dw-i3c-master-1.00a";
			reg = <0x10da0000 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 164 4>;
			resets = <&rst I3C0_RESET>;
			max_devices = <11>;
			clocks = <&clkmgr AGILEX5_L4_MP_CLK>;
			status = "disabled";
		};

		i3c1: i3c@10da1000 {
			compatible = "snps,dw-i3c-master-1.00a";
			reg = <0x10da1000 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 165 4>;
			resets = <&rst I3C1_RESET>;
			clocks = <&clkmgr AGILEX5_L4_MP_CLK>;
			max_devices = <11>;
			status = "disabled";
		};

		combophy0: combophy@0 {
			#phy-cells = <0>;
			phy-type = <1>;
			compatible = "cdns,combophy";
			reg = <0x10808000 0x1000>;
			resets = <&rst COMBOPHY_RESET>;
			reset-names = "reset";
			status = "disabled";
		};

		mmc: mmc0@10808000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "cdns,sd4hc";
			reg = <0x10808000 0x1000>;
			interrupts = <0 96 4>;
			phys = <&combophy0>;
			phy-names = "combo-phy";
			clocks = <&clkmgr AGILEX5_L4_MP_CLK>,
				 <&clkmgr AGILEX5_SDMMC_CLK>;
			clock-names = "biu", "ciu";
			fifo-depth = <0x800>;
			resets = <&rst SDMMC_RESET>;
			reset-names = "reset";
			iommus = <&smmu 5>;
			status = "disabled";
		};

		ocram: sram@00000000 {
			compatible = "mmio-sram";
			reg = <0x00000000 0x200000>;
		};

		rst: rstmgr@10d11000 {
			#reset-cells = <1>;
			compatible = "altr,stratix10-rst-mgr";
			reg = <0x10d11000 0x1000>;
		};

		smmu: iommu@16000000 {
			compatible = "arm,mmu-500", "arm,smmu-v2";
			reg = <0x16000000 0x40000>;
			#global-interrupts = <2>;
			#iommu-cells = <1>;
			interrupt-parent = <&intc>;
			interrupts = <0 128 4>,	/* Global Secure Fault */
				<0 129 4>, /* Global Non-secure Fault */
				/* Non-secure Context Interrupts (32) */
				<0 138 4>, <0 139 4>, <0 140 4>, <0 141 4>,
				<0 142 4>, <0 143 4>, <0 144 4>, <0 145 4>,
				<0 146 4>, <0 147 4>, <0 148 4>, <0 149 4>,
				<0 150 4>, <0 151 4>, <0 152 4>, <0 153 4>,
				<0 154 4>, <0 155 4>, <0 156 4>, <0 157 4>,
				<0 158 4>, <0 159 4>, <0 160 4>, <0 161 4>,
				<0 162 4>, <0 163 4>, <0 164 4>, <0 165 4>,
				<0 166 4>, <0 167 4>, <0 168 4>, <0 169 4>;
			stream-match-mask = <0x7ff0>;
			status = "disabled";
		};

		spi0: spi@10da4000 {
			compatible = "intel,agilex-spi",
				     "snps,dw-apb-ssi-4.00a", "snps,dw-apb-ssi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x10da4000 0x1000>;
			interrupts = <0 99 4>;
			resets = <&rst SPIM0_RESET>;
			reg-io-width = <4>;
			num-cs = <4>;
			clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>;
			status = "disabled";
		};

		spi1: spi@10da5000 {
			compatible = "intel,agilex-spi",
				     "snps,dw-apb-ssi-4.00a", "snps,dw-apb-ssi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x10da5000 0x1000>;
			interrupts = <0 100 4>;
			resets = <&rst SPIM1_RESET>;
			reg-io-width = <4>;
			num-cs = <4>;
			clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>;
			status = "disabled";
		};

		sysmgr: sysmgr@10d12000 {
			compatible = "altr,sys-mgr-s10","altr,sys-mgr";
			reg = <0x10d12000 0x500>;
		};

		/* Local timer */
		timer {
			compatible = "arm,armv8-timer";
			interrupts = <1 13 0xf08>,
				     <1 14 0xf08>,
				     <1 11 0xf08>,
				     <1 10 0xf08>;
		};

		timer0: timer0@10c03000 {
			compatible = "snps,dw-apb-timer";
			interrupts = <0 113 4>;
			reg = <0x10c03000 0x100>;
			resets = <&rst SPTIMER0_RESET>;
			clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
			clock-names = "timer";
			status = "disabled";
		};

		timer1: timer1@10c03100 {
			compatible = "snps,dw-apb-timer";
			interrupts = <0 114 4>;
			reg = <0x10c03100 0x100>;
			resets = <&rst SPTIMER1_RESET>;
			clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
			clock-names = "timer";
			status = "disabled";
		};

		timer2: timer2@10d00000 {
			compatible = "snps,dw-apb-timer";
			interrupts = <0 115 4>;
			reg = <0x10d00000 0x100>;
			resets = <&rst L4SYSTIMER0_RESET>;
			clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>;
			clock-names = "timer";
			status = "disabled";
		};

		timer3: timer3@10d00100 {
			compatible = "snps,dw-apb-timer";
			interrupts = <0 116 4>;
			reg = <0x10d00100 0x100>;
			resets = <&rst L4SYSTIMER1_RESET>;
			clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>;
			clock-names = "timer";
			status = "disabled";
		};

		uart0: serial0@10c02000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x10c02000 0x100>;
			interrupts = <0 108 4>;
			reg-shift = <2>;
			reg-io-width = <4>;
			resets = <&rst UART0_RESET>;
			status = "disabled";
			clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
			clock-frequency = <100000000>;
		};

		uart1: serial1@10c02100 {
			compatible = "snps,dw-apb-uart";
			reg = <0x10c02100 0x100>;
			interrupts = <0 109 4>;
			reg-shift = <2>;
			reg-io-width = <4>;
			resets = <&rst UART1_RESET>;
			clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
			status = "disabled";
		};

		usbphy0: usbphy@0 {
			#phy-cells = <0>;
			compatible = "usb-nop-xceiv";
			clocks = <&clkmgr AGILEX5_USB_CLK>;
			status = "disabled";
		};

		usb0: usb@10b00000 {
			compatible = "snps,dwc2";
			reg = <0x10b00000 0x40000>;
			interrupts = <0 93 4>;
			phys = <&usbphy0>;
			phy-names = "usb2-phy";
			resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>;
			reset-names = "dwc2", "dwc2-ecc";
			clocks = <&clkmgr AGILEX5_USB_CLK>;
			iommus = <&smmu 6>;
			status = "disabled";
		};

		usb31: usb31@11000000 {
			compatible = "snps,dwc3";
			reg = <0x11000000 0x100000>;
			resets = <&rst USB1_RESET>;
			phys = <&usbphy0>, <&usbphy0>;
			phy-names = "usb2-phy", "usb3-phy";
			dr_mode = "host";
			maximum-speed = "super-speed";
			snps,dis_u2_susphy_quirk;
			status = "disabled";
		};

		watchdog0: watchdog@10d00200 {
			compatible = "snps,dw-wdt";
			reg = <0x10d00200 0x100>;
			interrupts = <0 117 4>;
			resets = <&rst WATCHDOG0_RESET>;
			clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>;
			status = "disabled";
		};

		watchdog1: watchdog@10d00300 {
			compatible = "snps,dw-wdt";
			reg = <0x10d00300 0x100>;
			interrupts = <0 118 4>;
			resets = <&rst WATCHDOG1_RESET>;
			clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>;
			status = "disabled";
		};

		watchdog2: watchdog@10d00400 {
			compatible = "snps,dw-wdt";
			reg = <0x10d00400 0x100>;
			interrupts = <0 125 4>;
			resets = <&rst WATCHDOG2_RESET>;
			clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>;
			status = "disabled";
		};

		watchdog3: watchdog@10d00500 {
			compatible = "snps,dw-wdt";
			reg = <0x10d00500 0x100>;
			interrupts = <0 126 4>;
			resets = <&rst WATCHDOG3_RESET>;
			clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>;
			status = "disabled";
		};

		watchdog4: watchdog@10d00600 {
			compatible = "snps,dw-wdt";
			reg = <0x10d00600 0x100>;
			interrupts = <0 175 4>;
			resets = <&rst WATCHDOG4_RESET>;
			clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>;
			status = "disabled";
		};

		sdr: sdr@18000000 {
			compatible = "intel,sdr-ctl-agilex5";
			reg = <0x18000000 0x400000>;
			resets = <&rst DDRSCH_RESET>;
			bootph-all;
		};

		/* QSPI address not available yet */
		qspi: spi@108d2000 {
			compatible = "cdns,qspi-nor";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x108d2000 0x100>,
			      <0x10900000 0x100000>;
			interrupts = <0 3 4>;
			cdns,fifo-depth = <128>;
			cdns,fifo-width = <4>;
			cdns,trigger-address = <0x00000000>;
			clocks = <&qspi_clk>;

			status = "disabled";
		};

		firmware {
			svc {
				compatible = "intel,stratix10-svc";
				method = "smc";
				memory-region = <&service_reserved>;

				fpga_mgr: fpga-mgr {
					compatible = "intel,stratix10-soc-fpga-mgr";
				};
			};
		};
	};
};