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git01.mediatek.com / filogic / uboot / a03cb92688346145a51229f3467fe208c0ad6d9e / . / dts / upstream / src / arm / nxp / imx / imx6qdl.dtsi
blob: d2200c9db25aec90dbd348dedee4bfef47eb3ee7 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2//
3// Copyright 2011 Freescale Semiconductor, Inc.
4// Copyright 2011 Linaro Ltd.
5
6#include <dt-bindings/clock/imx6qdl-clock.h>
7#include <dt-bindings/input/input.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9
10/ {
11 #address-cells = <1>;
12 #size-cells = <1>;
13 /*
14 * The decompressor and also some bootloaders rely on a
15 * pre-existing /chosen node to be available to insert the
16 * command line and merge other ATAGS info.
17 */
18 chosen {};
19
20 aliases {
21 ethernet0 = &fec;
22 can0 = &can1;
23 can1 = &can2;
24 gpio0 = &gpio1;
25 gpio1 = &gpio2;
26 gpio2 = &gpio3;
27 gpio3 = &gpio4;
28 gpio4 = &gpio5;
29 gpio5 = &gpio6;
30 gpio6 = &gpio7;
31 i2c0 = &i2c1;
32 i2c1 = &i2c2;
33 i2c2 = &i2c3;
34 ipu0 = &ipu1;
35 mmc0 = &usdhc1;
36 mmc1 = &usdhc2;
37 mmc2 = &usdhc3;
38 mmc3 = &usdhc4;
39 serial0 = &uart1;
40 serial1 = &uart2;
41 serial2 = &uart3;
42 serial3 = &uart4;
43 serial4 = &uart5;
44 spi0 = &ecspi1;
45 spi1 = &ecspi2;
46 spi2 = &ecspi3;
47 spi3 = &ecspi4;
48 usb0 = &usbotg;
49 usb1 = &usbh1;
50 usb2 = &usbh2;
51 usb3 = &usbh3;
52 usbphy0 = &usbphy1;
53 usbphy1 = &usbphy2;
54 };
55
56 clocks {
57 ckil {
58 compatible = "fixed-clock";
59 #clock-cells = <0>;
60 clock-frequency = <32768>;
61 };
62
63 ckih1 {
64 compatible = "fixed-clock";
65 #clock-cells = <0>;
66 clock-frequency = <0>;
67 };
68
69 osc {
70 compatible = "fixed-clock";
71 #clock-cells = <0>;
72 clock-frequency = <24000000>;
73 };
74 };
75
76 ldb: ldb {
77 #address-cells = <1>;
78 #size-cells = <0>;
79 compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
80 gpr = <&gpr>;
81 status = "disabled";
82
83 lvds-channel@0 {
84 #address-cells = <1>;
85 #size-cells = <0>;
86 reg = <0>;
87 status = "disabled";
88
89 port@0 {
90 reg = <0>;
91
92 lvds0_mux_0: endpoint {
93 remote-endpoint = <&ipu1_di0_lvds0>;
94 };
95 };
96
97 port@1 {
98 reg = <1>;
99
100 lvds0_mux_1: endpoint {
101 remote-endpoint = <&ipu1_di1_lvds0>;
102 };
103 };
104 };
105
106 lvds-channel@1 {
107 #address-cells = <1>;
108 #size-cells = <0>;
109 reg = <1>;
110 status = "disabled";
111
112 port@0 {
113 reg = <0>;
114
115 lvds1_mux_0: endpoint {
116 remote-endpoint = <&ipu1_di0_lvds1>;
117 };
118 };
119
120 port@1 {
121 reg = <1>;
122
123 lvds1_mux_1: endpoint {
124 remote-endpoint = <&ipu1_di1_lvds1>;
125 };
126 };
127 };
128 };
129
130 pmu: pmu {
131 compatible = "arm,cortex-a9-pmu";
132 interrupt-parent = <&gpc>;
133 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
134 };
135
136 usbphynop1: usbphynop1 {
137 compatible = "usb-nop-xceiv";
138 #phy-cells = <0>;
139 };
140
141 usbphynop2: usbphynop2 {
142 compatible = "usb-nop-xceiv";
143 #phy-cells = <0>;
144 };
145
146 soc: soc {
147 #address-cells = <1>;
148 #size-cells = <1>;
149 compatible = "simple-bus";
150 interrupt-parent = <&gpc>;
151 ranges;
152
153 dma_apbh: dma-controller@110000 {
154 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
155 reg = <0x00110000 0x2000>;
156 interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
157 <0 13 IRQ_TYPE_LEVEL_HIGH>,
158 <0 13 IRQ_TYPE_LEVEL_HIGH>,
159 <0 13 IRQ_TYPE_LEVEL_HIGH>;
160 #dma-cells = <1>;
161 dma-channels = <4>;
162 clocks = <&clks IMX6QDL_CLK_APBH_DMA>;
163 };
164
165 gpmi: nand-controller@112000 {
166 compatible = "fsl,imx6q-gpmi-nand";
167 reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
168 reg-names = "gpmi-nand", "bch";
169 interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
170 interrupt-names = "bch";
171 clocks = <&clks IMX6QDL_CLK_GPMI_IO>,
172 <&clks IMX6QDL_CLK_GPMI_APB>,
173 <&clks IMX6QDL_CLK_GPMI_BCH>,
174 <&clks IMX6QDL_CLK_GPMI_BCH_APB>,
175 <&clks IMX6QDL_CLK_PER1_BCH>;
176 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
177 "gpmi_bch_apb", "per1_bch";
178 dmas = <&dma_apbh 0>;
179 dma-names = "rx-tx";
180 status = "disabled";
181 };
182
183 hdmi: hdmi@120000 {
184 reg = <0x00120000 0x9000>;
185 interrupts = <0 115 0x04>;
186 gpr = <&gpr>;
187 clocks = <&clks IMX6QDL_CLK_HDMI_IAHB>,
188 <&clks IMX6QDL_CLK_HDMI_ISFR>;
189 clock-names = "iahb", "isfr";
190 status = "disabled";
191
192 ports {
193 #address-cells = <1>;
194 #size-cells = <0>;
195
196 port@0 {
197 reg = <0>;
198
199 hdmi_mux_0: endpoint {
200 remote-endpoint = <&ipu1_di0_hdmi>;
201 };
202 };
203
204 port@1 {
205 reg = <1>;
206
207 hdmi_mux_1: endpoint {
208 remote-endpoint = <&ipu1_di1_hdmi>;
209 };
210 };
211 };
212 };
213
214 gpu_3d: gpu@130000 {
215 compatible = "vivante,gc";
216 reg = <0x00130000 0x4000>;
217 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
218 clocks = <&clks IMX6QDL_CLK_GPU3D_AXI>,
219 <&clks IMX6QDL_CLK_GPU3D_CORE>,
220 <&clks IMX6QDL_CLK_GPU3D_SHADER>;
221 clock-names = "bus", "core", "shader";
222 power-domains = <&pd_pu>;
223 #cooling-cells = <2>;
224 };
225
226 gpu_2d: gpu@134000 {
227 compatible = "vivante,gc";
228 reg = <0x00134000 0x4000>;
229 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
230 clocks = <&clks IMX6QDL_CLK_GPU2D_AXI>,
231 <&clks IMX6QDL_CLK_GPU2D_CORE>;
232 clock-names = "bus", "core";
233 power-domains = <&pd_pu>;
234 #cooling-cells = <2>;
235 };
236
237 timer@a00600 {
238 compatible = "arm,cortex-a9-twd-timer";
239 reg = <0x00a00600 0x20>;
240 interrupts = <1 13 0xf01>;
241 interrupt-parent = <&intc>;
242 clocks = <&clks IMX6QDL_CLK_TWD>;
243 };
244
245 intc: interrupt-controller@a01000 {
246 compatible = "arm,cortex-a9-gic";
247 #interrupt-cells = <3>;
248 interrupt-controller;
249 reg = <0x00a01000 0x1000>,
250 <0x00a00100 0x100>;
251 interrupt-parent = <&intc>;
252 };
253
254 L2: cache-controller@a02000 {
255 compatible = "arm,pl310-cache";
256 reg = <0x00a02000 0x1000>;
257 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
258 cache-unified;
259 cache-level = <2>;
260 arm,tag-latency = <4 2 3>;
261 arm,data-latency = <4 2 3>;
262 arm,shared-override;
263 };
264
265 pcie: pcie@1ffc000 {
266 compatible = "fsl,imx6q-pcie";
267 reg = <0x01ffc000 0x04000>,
268 <0x01f00000 0x80000>;
269 reg-names = "dbi", "config";
270 #address-cells = <3>;
271 #size-cells = <2>;
272 device_type = "pci";
273 bus-range = <0x00 0xff>;
274 ranges = <0x81000000 0 0 0x01f80000 0 0x00010000>, /* downstream I/O */
275 <0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
276 num-lanes = <1>;
277 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
278 interrupt-names = "msi";
279 #interrupt-cells = <1>;
280 interrupt-map-mask = <0 0 0 0x7>;
281 interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
282 <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
283 <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
284 <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
285 clocks = <&clks IMX6QDL_CLK_PCIE_AXI>,
286 <&clks IMX6QDL_CLK_LVDS1_GATE>,
287 <&clks IMX6QDL_CLK_PCIE_REF_125M>;
288 clock-names = "pcie", "pcie_bus", "pcie_phy";
289 status = "disabled";
290 };
291
292 aips1: bus@2000000 { /* AIPS1 */
293 compatible = "fsl,aips-bus", "simple-bus";
294 #address-cells = <1>;
295 #size-cells = <1>;
296 reg = <0x02000000 0x100000>;
297 ranges;
298
299 spba-bus@2000000 {
300 compatible = "fsl,spba-bus", "simple-bus";
301 #address-cells = <1>;
302 #size-cells = <1>;
303 reg = <0x02000000 0x40000>;
304 ranges;
305
306 spdif: spdif@2004000 {
307 compatible = "fsl,imx35-spdif";
308 reg = <0x02004000 0x4000>;
309 interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
310 dmas = <&sdma 14 18 0>,
311 <&sdma 15 18 0>;
312 dma-names = "rx", "tx";
313 clocks = <&clks IMX6QDL_CLK_SPDIF_GCLK>, <&clks IMX6QDL_CLK_OSC>,
314 <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_ASRC>,
315 <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_ESAI_EXTAL>,
316 <&clks IMX6QDL_CLK_IPG>, <&clks IMX6QDL_CLK_DUMMY>,
317 <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_SPBA>;
318 clock-names = "core", "rxtx0",
319 "rxtx1", "rxtx2",
320 "rxtx3", "rxtx4",
321 "rxtx5", "rxtx6",
322 "rxtx7", "spba";
323 status = "disabled";
324 };
325
326 ecspi1: spi@2008000 {
327 #address-cells = <1>;
328 #size-cells = <0>;
329 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
330 reg = <0x02008000 0x4000>;
331 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
332 clocks = <&clks IMX6QDL_CLK_ECSPI1>,
333 <&clks IMX6QDL_CLK_ECSPI1>;
334 clock-names = "ipg", "per";
335 dmas = <&sdma 3 7 1>, <&sdma 4 7 2>;
336 dma-names = "rx", "tx";
337 status = "disabled";
338 };
339
340 ecspi2: spi@200c000 {
341 #address-cells = <1>;
342 #size-cells = <0>;
343 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
344 reg = <0x0200c000 0x4000>;
345 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
346 clocks = <&clks IMX6QDL_CLK_ECSPI2>,
347 <&clks IMX6QDL_CLK_ECSPI2>;
348 clock-names = "ipg", "per";
349 dmas = <&sdma 5 7 1>, <&sdma 6 7 2>;
350 dma-names = "rx", "tx";
351 status = "disabled";
352 };
353
354 ecspi3: spi@2010000 {
355 #address-cells = <1>;
356 #size-cells = <0>;
357 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
358 reg = <0x02010000 0x4000>;
359 interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
360 clocks = <&clks IMX6QDL_CLK_ECSPI3>,
361 <&clks IMX6QDL_CLK_ECSPI3>;
362 clock-names = "ipg", "per";
363 dmas = <&sdma 7 7 1>, <&sdma 8 7 2>;
364 dma-names = "rx", "tx";
365 status = "disabled";
366 };
367
368 ecspi4: spi@2014000 {
369 #address-cells = <1>;
370 #size-cells = <0>;
371 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
372 reg = <0x02014000 0x4000>;
373 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
374 clocks = <&clks IMX6QDL_CLK_ECSPI4>,
375 <&clks IMX6QDL_CLK_ECSPI4>;
376 clock-names = "ipg", "per";
377 dmas = <&sdma 9 7 1>, <&sdma 10 7 2>;
378 dma-names = "rx", "tx";
379 status = "disabled";
380 };
381
382 uart1: serial@2020000 {
383 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
384 reg = <0x02020000 0x4000>;
385 interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
386 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
387 <&clks IMX6QDL_CLK_UART_SERIAL>;
388 clock-names = "ipg", "per";
389 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
390 dma-names = "rx", "tx";
391 status = "disabled";
392 };
393
394 esai: esai@2024000 {
395 #sound-dai-cells = <0>;
396 compatible = "fsl,imx35-esai";
397 reg = <0x02024000 0x4000>;
398 interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
399 clocks = <&clks IMX6QDL_CLK_ESAI_IPG>,
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]400 <&clks IMX6QDL_CLK_ESAI_EXTAL>,
401 <&clks IMX6QDL_CLK_ESAI_IPG>,
402 <&clks IMX6QDL_CLK_SPBA>;
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]403 clock-names = "core", "extal", "fsys", "spba";
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]404 dmas = <&sdma 23 21 0>, <&sdma 24 21 0>;
405 dma-names = "rx", "tx";
406 status = "disabled";
407 };
408
409 ssi1: ssi@2028000 {
410 #sound-dai-cells = <0>;
411 compatible = "fsl,imx6q-ssi",
412 "fsl,imx51-ssi";
413 reg = <0x02028000 0x4000>;
414 interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
415 clocks = <&clks IMX6QDL_CLK_SSI1_IPG>,
416 <&clks IMX6QDL_CLK_SSI1>;
417 clock-names = "ipg", "baud";
418 dmas = <&sdma 37 1 0>,
419 <&sdma 38 1 0>;
420 dma-names = "rx", "tx";
421 fsl,fifo-depth = <15>;
422 status = "disabled";
423 };
424
425 ssi2: ssi@202c000 {
426 #sound-dai-cells = <0>;
427 compatible = "fsl,imx6q-ssi",
428 "fsl,imx51-ssi";
429 reg = <0x0202c000 0x4000>;
430 interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
431 clocks = <&clks IMX6QDL_CLK_SSI2_IPG>,
432 <&clks IMX6QDL_CLK_SSI2>;
433 clock-names = "ipg", "baud";
434 dmas = <&sdma 41 1 0>,
435 <&sdma 42 1 0>;
436 dma-names = "rx", "tx";
437 fsl,fifo-depth = <15>;
438 status = "disabled";
439 };
440
441 ssi3: ssi@2030000 {
442 #sound-dai-cells = <0>;
443 compatible = "fsl,imx6q-ssi",
444 "fsl,imx51-ssi";
445 reg = <0x02030000 0x4000>;
446 interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
447 clocks = <&clks IMX6QDL_CLK_SSI3_IPG>,
448 <&clks IMX6QDL_CLK_SSI3>;
449 clock-names = "ipg", "baud";
450 dmas = <&sdma 45 1 0>,
451 <&sdma 46 1 0>;
452 dma-names = "rx", "tx";
453 fsl,fifo-depth = <15>;
454 status = "disabled";
455 };
456
457 asrc: asrc@2034000 {
458 compatible = "fsl,imx53-asrc";
459 reg = <0x02034000 0x4000>;
460 interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
461 clocks = <&clks IMX6QDL_CLK_ASRC_IPG>,
462 <&clks IMX6QDL_CLK_ASRC_MEM>, <&clks 0>,
463 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
464 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
465 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
466 <&clks IMX6QDL_CLK_ASRC>, <&clks 0>, <&clks 0>,
467 <&clks IMX6QDL_CLK_SPBA>;
468 clock-names = "mem", "ipg", "asrck_0",
469 "asrck_1", "asrck_2", "asrck_3", "asrck_4",
470 "asrck_5", "asrck_6", "asrck_7", "asrck_8",
471 "asrck_9", "asrck_a", "asrck_b", "asrck_c",
472 "asrck_d", "asrck_e", "asrck_f", "spba";
473 dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>,
474 <&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>;
475 dma-names = "rxa", "rxb", "rxc",
476 "txa", "txb", "txc";
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]477 fsl,asrc-rate = <48000>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]478 fsl,asrc-width = <16>;
479 status = "okay";
480 };
481
482 spba-bus@203c000 {
483 reg = <0x0203c000 0x4000>;
484 };
485 };
486
487 vpu: vpu@2040000 {
488 compatible = "cnm,coda960";
489 reg = <0x02040000 0x3c000>;
490 interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>,
491 <0 3 IRQ_TYPE_LEVEL_HIGH>;
492 interrupt-names = "bit", "jpeg";
493 clocks = <&clks IMX6QDL_CLK_VPU_AXI>,
494 <&clks IMX6QDL_CLK_MMDC_CH0_AXI>;
495 clock-names = "per", "ahb";
496 power-domains = <&pd_pu>;
497 resets = <&src 1>;
498 iram = <&ocram>;
499 };
500
501 aipstz@207c000 { /* AIPSTZ1 */
502 reg = <0x0207c000 0x4000>;
503 };
504
505 pwm1: pwm@2080000 {
506 #pwm-cells = <3>;
507 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
508 reg = <0x02080000 0x4000>;
509 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
510 clocks = <&clks IMX6QDL_CLK_IPG>,
511 <&clks IMX6QDL_CLK_PWM1>;
512 clock-names = "ipg", "per";
513 status = "disabled";
514 };
515
516 pwm2: pwm@2084000 {
517 #pwm-cells = <3>;
518 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
519 reg = <0x02084000 0x4000>;
520 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
521 clocks = <&clks IMX6QDL_CLK_IPG>,
522 <&clks IMX6QDL_CLK_PWM2>;
523 clock-names = "ipg", "per";
524 status = "disabled";
525 };
526
527 pwm3: pwm@2088000 {
528 #pwm-cells = <3>;
529 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
530 reg = <0x02088000 0x4000>;
531 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
532 clocks = <&clks IMX6QDL_CLK_IPG>,
533 <&clks IMX6QDL_CLK_PWM3>;
534 clock-names = "ipg", "per";
535 status = "disabled";
536 };
537
538 pwm4: pwm@208c000 {
539 #pwm-cells = <3>;
540 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
541 reg = <0x0208c000 0x4000>;
542 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
543 clocks = <&clks IMX6QDL_CLK_IPG>,
544 <&clks IMX6QDL_CLK_PWM4>;
545 clock-names = "ipg", "per";
546 status = "disabled";
547 };
548
549 can1: can@2090000 {
550 compatible = "fsl,imx6q-flexcan";
551 reg = <0x02090000 0x4000>;
552 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
553 clocks = <&clks IMX6QDL_CLK_CAN1_IPG>,
554 <&clks IMX6QDL_CLK_CAN1_SERIAL>;
555 clock-names = "ipg", "per";
556 fsl,stop-mode = <&gpr 0x34 28>;
557 status = "disabled";
558 };
559
560 can2: can@2094000 {
561 compatible = "fsl,imx6q-flexcan";
562 reg = <0x02094000 0x4000>;
563 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
564 clocks = <&clks IMX6QDL_CLK_CAN2_IPG>,
565 <&clks IMX6QDL_CLK_CAN2_SERIAL>;
566 clock-names = "ipg", "per";
567 fsl,stop-mode = <&gpr 0x34 29>;
568 status = "disabled";
569 };
570
571 gpt: timer@2098000 {
572 compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt";
573 reg = <0x02098000 0x4000>;
574 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
575 clocks = <&clks IMX6QDL_CLK_GPT_IPG>,
576 <&clks IMX6QDL_CLK_GPT_IPG_PER>,
577 <&clks IMX6QDL_CLK_GPT_3M>;
578 clock-names = "ipg", "per", "osc_per";
579 };
580
581 gpio1: gpio@209c000 {
582 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
583 reg = <0x0209c000 0x4000>;
584 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
585 <0 67 IRQ_TYPE_LEVEL_HIGH>;
586 gpio-controller;
587 #gpio-cells = <2>;
588 interrupt-controller;
589 #interrupt-cells = <2>;
590 };
591
592 gpio2: gpio@20a0000 {
593 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
594 reg = <0x020a0000 0x4000>;
595 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
596 <0 69 IRQ_TYPE_LEVEL_HIGH>;
597 gpio-controller;
598 #gpio-cells = <2>;
599 interrupt-controller;
600 #interrupt-cells = <2>;
601 };
602
603 gpio3: gpio@20a4000 {
604 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
605 reg = <0x020a4000 0x4000>;
606 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
607 <0 71 IRQ_TYPE_LEVEL_HIGH>;
608 gpio-controller;
609 #gpio-cells = <2>;
610 interrupt-controller;
611 #interrupt-cells = <2>;
612 };
613
614 gpio4: gpio@20a8000 {
615 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
616 reg = <0x020a8000 0x4000>;
617 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
618 <0 73 IRQ_TYPE_LEVEL_HIGH>;
619 gpio-controller;
620 #gpio-cells = <2>;
621 interrupt-controller;
622 #interrupt-cells = <2>;
623 };
624
625 gpio5: gpio@20ac000 {
626 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
627 reg = <0x020ac000 0x4000>;
628 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
629 <0 75 IRQ_TYPE_LEVEL_HIGH>;
630 gpio-controller;
631 #gpio-cells = <2>;
632 interrupt-controller;
633 #interrupt-cells = <2>;
634 };
635
636 gpio6: gpio@20b0000 {
637 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
638 reg = <0x020b0000 0x4000>;
639 interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>,
640 <0 77 IRQ_TYPE_LEVEL_HIGH>;
641 gpio-controller;
642 #gpio-cells = <2>;
643 interrupt-controller;
644 #interrupt-cells = <2>;
645 };
646
647 gpio7: gpio@20b4000 {
648 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
649 reg = <0x020b4000 0x4000>;
650 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>,
651 <0 79 IRQ_TYPE_LEVEL_HIGH>;
652 gpio-controller;
653 #gpio-cells = <2>;
654 interrupt-controller;
655 #interrupt-cells = <2>;
656 };
657
658 kpp: keypad@20b8000 {
659 compatible = "fsl,imx6q-kpp", "fsl,imx21-kpp";
660 reg = <0x020b8000 0x4000>;
661 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
662 clocks = <&clks IMX6QDL_CLK_IPG>;
663 status = "disabled";
664 };
665
666 wdog1: watchdog@20bc000 {
667 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
668 reg = <0x020bc000 0x4000>;
669 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
670 clocks = <&clks IMX6QDL_CLK_IPG>;
671 };
672
673 wdog2: watchdog@20c0000 {
674 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
675 reg = <0x020c0000 0x4000>;
676 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
677 clocks = <&clks IMX6QDL_CLK_IPG>;
678 status = "disabled";
679 };
680
681 clks: clock-controller@20c4000 {
682 compatible = "fsl,imx6q-ccm";
683 reg = <0x020c4000 0x4000>;
684 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
685 <0 88 IRQ_TYPE_LEVEL_HIGH>;
686 #clock-cells = <1>;
687 };
688
689 anatop: anatop@20c8000 {
690 compatible = "fsl,imx6q-anatop", "syscon", "simple-mfd";
691 reg = <0x020c8000 0x1000>;
692 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
693 <0 54 IRQ_TYPE_LEVEL_HIGH>,
694 <0 127 IRQ_TYPE_LEVEL_HIGH>;
695
696 reg_vdd1p1: regulator-1p1 {
697 compatible = "fsl,anatop-regulator";
698 regulator-name = "vdd1p1";
699 regulator-min-microvolt = <1000000>;
700 regulator-max-microvolt = <1200000>;
701 regulator-always-on;
702 anatop-reg-offset = <0x110>;
703 anatop-vol-bit-shift = <8>;
704 anatop-vol-bit-width = <5>;
705 anatop-min-bit-val = <4>;
706 anatop-min-voltage = <800000>;
707 anatop-max-voltage = <1375000>;
708 anatop-enable-bit = <0>;
709 };
710
711 reg_vdd3p0: regulator-3p0 {
712 compatible = "fsl,anatop-regulator";
713 regulator-name = "vdd3p0";
714 regulator-min-microvolt = <2800000>;
715 regulator-max-microvolt = <3150000>;
716 regulator-always-on;
717 anatop-reg-offset = <0x120>;
718 anatop-vol-bit-shift = <8>;
719 anatop-vol-bit-width = <5>;
720 anatop-min-bit-val = <0>;
721 anatop-min-voltage = <2625000>;
722 anatop-max-voltage = <3400000>;
723 anatop-enable-bit = <0>;
724 };
725
726 reg_vdd2p5: regulator-2p5 {
727 compatible = "fsl,anatop-regulator";
728 regulator-name = "vdd2p5";
729 regulator-min-microvolt = <2250000>;
730 regulator-max-microvolt = <2750000>;
731 regulator-always-on;
732 anatop-reg-offset = <0x130>;
733 anatop-vol-bit-shift = <8>;
734 anatop-vol-bit-width = <5>;
735 anatop-min-bit-val = <0>;
736 anatop-min-voltage = <2100000>;
737 anatop-max-voltage = <2875000>;
738 anatop-enable-bit = <0>;
739 };
740
741 reg_arm: regulator-vddcore {
742 compatible = "fsl,anatop-regulator";
743 regulator-name = "vddarm";
744 regulator-min-microvolt = <725000>;
745 regulator-max-microvolt = <1450000>;
746 regulator-always-on;
747 anatop-reg-offset = <0x140>;
748 anatop-vol-bit-shift = <0>;
749 anatop-vol-bit-width = <5>;
750 anatop-delay-reg-offset = <0x170>;
751 anatop-delay-bit-shift = <24>;
752 anatop-delay-bit-width = <2>;
753 anatop-min-bit-val = <1>;
754 anatop-min-voltage = <725000>;
755 anatop-max-voltage = <1450000>;
756 };
757
758 reg_pu: regulator-vddpu {
759 compatible = "fsl,anatop-regulator";
760 regulator-name = "vddpu";
761 regulator-min-microvolt = <725000>;
762 regulator-max-microvolt = <1450000>;
763 regulator-enable-ramp-delay = <380>;
764 anatop-reg-offset = <0x140>;
765 anatop-vol-bit-shift = <9>;
766 anatop-vol-bit-width = <5>;
767 anatop-delay-reg-offset = <0x170>;
768 anatop-delay-bit-shift = <26>;
769 anatop-delay-bit-width = <2>;
770 anatop-min-bit-val = <1>;
771 anatop-min-voltage = <725000>;
772 anatop-max-voltage = <1450000>;
773 };
774
775 reg_soc: regulator-vddsoc {
776 compatible = "fsl,anatop-regulator";
777 regulator-name = "vddsoc";
778 regulator-min-microvolt = <725000>;
779 regulator-max-microvolt = <1450000>;
780 regulator-always-on;
781 anatop-reg-offset = <0x140>;
782 anatop-vol-bit-shift = <18>;
783 anatop-vol-bit-width = <5>;
784 anatop-delay-reg-offset = <0x170>;
785 anatop-delay-bit-shift = <28>;
786 anatop-delay-bit-width = <2>;
787 anatop-min-bit-val = <1>;
788 anatop-min-voltage = <725000>;
789 anatop-max-voltage = <1450000>;
790 };
791
792 tempmon: tempmon {
793 compatible = "fsl,imx6q-tempmon";
794 interrupt-parent = <&gpc>;
795 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
796 fsl,tempmon = <&anatop>;
797 nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
798 nvmem-cell-names = "calib", "temp_grade";
799 clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
800 #thermal-sensor-cells = <0>;
801 };
802 };
803
804 usbphy1: usbphy@20c9000 {
805 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
806 reg = <0x020c9000 0x1000>;
807 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
808 clocks = <&clks IMX6QDL_CLK_USBPHY1>;
809 fsl,anatop = <&anatop>;
810 };
811
812 usbphy2: usbphy@20ca000 {
813 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
814 reg = <0x020ca000 0x1000>;
815 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
816 clocks = <&clks IMX6QDL_CLK_USBPHY2>;
817 fsl,anatop = <&anatop>;
818 };
819
820 snvs: snvs@20cc000 {
821 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
822 reg = <0x020cc000 0x4000>;
823
824 snvs_rtc: snvs-rtc-lp {
825 compatible = "fsl,sec-v4.0-mon-rtc-lp";
826 regmap = <&snvs>;
827 offset = <0x34>;
828 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
829 <0 20 IRQ_TYPE_LEVEL_HIGH>;
830 };
831
832 snvs_poweroff: snvs-poweroff {
833 compatible = "syscon-poweroff";
834 regmap = <&snvs>;
835 offset = <0x38>;
836 value = <0x60>;
837 mask = <0x60>;
838 status = "disabled";
839 };
840
841 snvs_pwrkey: snvs-powerkey {
842 compatible = "fsl,sec-v4.0-pwrkey";
843 regmap = <&snvs>;
844 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
845 linux,keycode = <KEY_POWER>;
846 wakeup-source;
847 status = "disabled";
848 };
849
850 snvs_lpgpr: snvs-lpgpr {
851 compatible = "fsl,imx6q-snvs-lpgpr";
852 };
853 };
854
855 epit1: epit@20d0000 { /* EPIT1 */
856 reg = <0x020d0000 0x4000>;
857 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
858 };
859
860 epit2: epit@20d4000 { /* EPIT2 */
861 reg = <0x020d4000 0x4000>;
862 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
863 };
864
865 src: reset-controller@20d8000 {
866 compatible = "fsl,imx6q-src", "fsl,imx51-src";
867 reg = <0x020d8000 0x4000>;
868 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
869 <0 96 IRQ_TYPE_LEVEL_HIGH>;
870 #reset-cells = <1>;
871 };
872
873 gpc: gpc@20dc000 {
874 compatible = "fsl,imx6q-gpc";
875 reg = <0x020dc000 0x4000>;
876 interrupt-controller;
877 #interrupt-cells = <3>;
878 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
879 interrupt-parent = <&intc>;
880 clocks = <&clks IMX6QDL_CLK_IPG>;
881 clock-names = "ipg";
882
883 pgc {
884 #address-cells = <1>;
885 #size-cells = <0>;
886
887 power-domain@0 {
888 reg = <0>;
889 #power-domain-cells = <0>;
890 };
891 pd_pu: power-domain@1 {
892 reg = <1>;
893 #power-domain-cells = <0>;
894 power-supply = <&reg_pu>;
895 clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>,
896 <&clks IMX6QDL_CLK_GPU3D_SHADER>,
897 <&clks IMX6QDL_CLK_GPU2D_CORE>,
898 <&clks IMX6QDL_CLK_GPU2D_AXI>,
899 <&clks IMX6QDL_CLK_OPENVG_AXI>,
900 <&clks IMX6QDL_CLK_VPU_AXI>;
901 };
902 };
903 };
904
905 gpr: iomuxc-gpr@20e0000 {
906 compatible = "fsl,imx6q-iomuxc-gpr", "syscon", "simple-mfd";
907 reg = <0x20e0000 0x38>;
908
909 mux: mux-controller {
910 compatible = "mmio-mux";
911 #mux-control-cells = <1>;
912 };
913 };
914
915 iomuxc: pinctrl@20e0000 {
916 compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
917 reg = <0x20e0000 0x4000>;
918 };
919
920 dcic1: dcic@20e4000 {
921 reg = <0x020e4000 0x4000>;
922 interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
923 };
924
925 dcic2: dcic@20e8000 {
926 reg = <0x020e8000 0x4000>;
927 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
928 };
929
930 sdma: dma-controller@20ec000 {
931 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
932 reg = <0x020ec000 0x4000>;
933 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
934 clocks = <&clks IMX6QDL_CLK_IPG>,
935 <&clks IMX6QDL_CLK_SDMA>;
936 clock-names = "ipg", "ahb";
937 #dma-cells = <3>;
938 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
939 };
940 };
941
942 aips2: bus@2100000 { /* AIPS2 */
943 compatible = "fsl,aips-bus", "simple-bus";
944 #address-cells = <1>;
945 #size-cells = <1>;
946 reg = <0x02100000 0x100000>;
947 ranges;
948
949 crypto: crypto@2100000 {
950 compatible = "fsl,sec-v4.0";
951 #address-cells = <1>;
952 #size-cells = <1>;
953 reg = <0x2100000 0x10000>;
954 ranges = <0 0x2100000 0x10000>;
955 clocks = <&clks IMX6QDL_CLK_CAAM_MEM>,
956 <&clks IMX6QDL_CLK_CAAM_ACLK>,
957 <&clks IMX6QDL_CLK_CAAM_IPG>,
958 <&clks IMX6QDL_CLK_EIM_SLOW>;
959 clock-names = "mem", "aclk", "ipg", "emi_slow";
960
961 sec_jr0: jr@1000 {
962 compatible = "fsl,sec-v4.0-job-ring";
963 reg = <0x1000 0x1000>;
964 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
965 };
966
967 sec_jr1: jr@2000 {
968 compatible = "fsl,sec-v4.0-job-ring";
969 reg = <0x2000 0x1000>;
970 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
971 };
972 };
973
974 aipstz@217c000 { /* AIPSTZ2 */
975 reg = <0x0217c000 0x4000>;
976 };
977
978 usbotg: usb@2184000 {
979 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
980 reg = <0x02184000 0x200>;
981 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
982 clocks = <&clks IMX6QDL_CLK_USBOH3>;
983 fsl,usbphy = <&usbphy1>;
984 fsl,usbmisc = <&usbmisc 0>;
985 ahb-burst-config = <0x0>;
986 tx-burst-size-dword = <0x10>;
987 rx-burst-size-dword = <0x10>;
988 status = "disabled";
989 };
990
991 usbh1: usb@2184200 {
992 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
993 reg = <0x02184200 0x200>;
994 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
995 clocks = <&clks IMX6QDL_CLK_USBOH3>;
996 fsl,usbphy = <&usbphy2>;
997 fsl,usbmisc = <&usbmisc 1>;
998 dr_mode = "host";
999 ahb-burst-config = <0x0>;
1000 tx-burst-size-dword = <0x10>;
1001 rx-burst-size-dword = <0x10>;
1002 status = "disabled";
1003 };
1004
1005 usbh2: usb@2184400 {
1006 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
1007 reg = <0x02184400 0x200>;
1008 interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
1009 clocks = <&clks IMX6QDL_CLK_USBOH3>;
1010 fsl,usbphy = <&usbphynop1>;
1011 phy_type = "hsic";
1012 fsl,usbmisc = <&usbmisc 2>;
1013 dr_mode = "host";
1014 ahb-burst-config = <0x0>;
1015 tx-burst-size-dword = <0x10>;
1016 rx-burst-size-dword = <0x10>;
1017 status = "disabled";
1018 };
1019
1020 usbh3: usb@2184600 {
1021 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
1022 reg = <0x02184600 0x200>;
1023 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
1024 clocks = <&clks IMX6QDL_CLK_USBOH3>;
1025 fsl,usbphy = <&usbphynop2>;
1026 phy_type = "hsic";
1027 fsl,usbmisc = <&usbmisc 3>;
1028 dr_mode = "host";
1029 ahb-burst-config = <0x0>;
1030 tx-burst-size-dword = <0x10>;
1031 rx-burst-size-dword = <0x10>;
1032 status = "disabled";
1033 };
1034
1035 usbmisc: usbmisc@2184800 {
1036 #index-cells = <1>;
1037 compatible = "fsl,imx6q-usbmisc";
1038 reg = <0x02184800 0x200>;
1039 clocks = <&clks IMX6QDL_CLK_USBOH3>;
1040 };
1041
1042 fec: ethernet@2188000 {
1043 compatible = "fsl,imx6q-fec";
1044 reg = <0x02188000 0x4000>;
1045 interrupt-names = "int0", "pps";
1046 interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>,
1047 <0 119 IRQ_TYPE_LEVEL_HIGH>;
1048 clocks = <&clks IMX6QDL_CLK_ENET>,
1049 <&clks IMX6QDL_CLK_ENET>,
1050 <&clks IMX6QDL_CLK_ENET_REF>,
1051 <&clks IMX6QDL_CLK_ENET_REF_SEL>;
1052 clock-names = "ipg", "ahb", "ptp", "enet_clk_ref";
1053 fsl,stop-mode = <&gpr 0x34 27>;
1054 nvmem-cells = <&fec_mac_addr>;
1055 nvmem-cell-names = "mac-address";
1056 status = "disabled";
1057 };
1058
1059 mlb@218c000 {
1060 reg = <0x0218c000 0x4000>;
1061 interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>,
1062 <0 117 IRQ_TYPE_LEVEL_HIGH>,
1063 <0 126 IRQ_TYPE_LEVEL_HIGH>;
1064 };
1065
1066 usdhc1: mmc@2190000 {
1067 compatible = "fsl,imx6q-usdhc";
1068 reg = <0x02190000 0x4000>;
1069 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
1070 clocks = <&clks IMX6QDL_CLK_USDHC1>,
1071 <&clks IMX6QDL_CLK_USDHC1>,
1072 <&clks IMX6QDL_CLK_USDHC1>;
1073 clock-names = "ipg", "ahb", "per";
1074 bus-width = <4>;
1075 status = "disabled";
1076 };
1077
1078 usdhc2: mmc@2194000 {
1079 compatible = "fsl,imx6q-usdhc";
1080 reg = <0x02194000 0x4000>;
1081 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
1082 clocks = <&clks IMX6QDL_CLK_USDHC2>,
1083 <&clks IMX6QDL_CLK_USDHC2>,
1084 <&clks IMX6QDL_CLK_USDHC2>;
1085 clock-names = "ipg", "ahb", "per";
1086 bus-width = <4>;
1087 status = "disabled";
1088 };
1089
1090 usdhc3: mmc@2198000 {
1091 compatible = "fsl,imx6q-usdhc";
1092 reg = <0x02198000 0x4000>;
1093 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
1094 clocks = <&clks IMX6QDL_CLK_USDHC3>,
1095 <&clks IMX6QDL_CLK_USDHC3>,
1096 <&clks IMX6QDL_CLK_USDHC3>;
1097 clock-names = "ipg", "ahb", "per";
1098 bus-width = <4>;
1099 status = "disabled";
1100 };
1101
1102 usdhc4: mmc@219c000 {
1103 compatible = "fsl,imx6q-usdhc";
1104 reg = <0x0219c000 0x4000>;
1105 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
1106 clocks = <&clks IMX6QDL_CLK_USDHC4>,
1107 <&clks IMX6QDL_CLK_USDHC4>,
1108 <&clks IMX6QDL_CLK_USDHC4>;
1109 clock-names = "ipg", "ahb", "per";
1110 bus-width = <4>;
1111 status = "disabled";
1112 };
1113
1114 i2c1: i2c@21a0000 {
1115 #address-cells = <1>;
1116 #size-cells = <0>;
1117 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1118 reg = <0x021a0000 0x4000>;
1119 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
1120 clocks = <&clks IMX6QDL_CLK_I2C1>;
1121 status = "disabled";
1122 };
1123
1124 i2c2: i2c@21a4000 {
1125 #address-cells = <1>;
1126 #size-cells = <0>;
1127 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1128 reg = <0x021a4000 0x4000>;
1129 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
1130 clocks = <&clks IMX6QDL_CLK_I2C2>;
1131 status = "disabled";
1132 };
1133
1134 i2c3: i2c@21a8000 {
1135 #address-cells = <1>;
1136 #size-cells = <0>;
1137 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1138 reg = <0x021a8000 0x4000>;
1139 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
1140 clocks = <&clks IMX6QDL_CLK_I2C3>;
1141 status = "disabled";
1142 };
1143
1144 romcp@21ac000 {
1145 reg = <0x021ac000 0x4000>;
1146 };
1147
1148 mmdc0: memory-controller@21b0000 { /* MMDC0 */
1149 compatible = "fsl,imx6q-mmdc";
1150 reg = <0x021b0000 0x4000>;
1151 clocks = <&clks IMX6QDL_CLK_MMDC_P0_IPG>;
1152 };
1153
1154 mmdc1: memory-controller@21b4000 { /* MMDC1 */
1155 compatible = "fsl,imx6q-mmdc";
1156 reg = <0x021b4000 0x4000>;
1157 status = "disabled";
1158 };
1159
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]1160 weim: memory-controller@21b8000 {
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1161 #address-cells = <2>;
1162 #size-cells = <1>;
1163 compatible = "fsl,imx6q-weim";
1164 reg = <0x021b8000 0x4000>;
1165 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
1166 clocks = <&clks IMX6QDL_CLK_EIM_SLOW>;
1167 fsl,weim-cs-gpr = <&gpr>;
1168 status = "disabled";
1169 };
1170
1171 ocotp: efuse@21bc000 {
1172 compatible = "fsl,imx6q-ocotp", "syscon";
1173 reg = <0x021bc000 0x4000>;
1174 clocks = <&clks IMX6QDL_CLK_IIM>;
1175 #address-cells = <1>;
1176 #size-cells = <1>;
1177
1178 cpu_speed_grade: speed-grade@10 {
1179 reg = <0x10 4>;
1180 };
1181
1182 tempmon_calib: calib@38 {
1183 reg = <0x38 4>;
1184 };
1185
1186 tempmon_temp_grade: temp-grade@20 {
1187 reg = <0x20 4>;
1188 };
1189
1190 fec_mac_addr: mac-addr@88 {
1191 reg = <0x88 6>;
1192 };
1193 };
1194
1195 tzasc@21d0000 { /* TZASC1 */
1196 reg = <0x021d0000 0x4000>;
1197 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
1198 };
1199
1200 tzasc@21d4000 { /* TZASC2 */
1201 reg = <0x021d4000 0x4000>;
1202 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
1203 };
1204
1205 audmux: audmux@21d8000 {
1206 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
1207 reg = <0x021d8000 0x4000>;
1208 status = "disabled";
1209 };
1210
1211 mipi_csi: mipi@21dc000 {
1212 compatible = "fsl,imx6-mipi-csi2";
1213 reg = <0x021dc000 0x4000>;
1214 #address-cells = <1>;
1215 #size-cells = <0>;
1216 interrupts = <0 100 0x04>, <0 101 0x04>;
1217 clocks = <&clks IMX6QDL_CLK_HSI_TX>,
1218 <&clks IMX6QDL_CLK_VIDEO_27M>,
1219 <&clks IMX6QDL_CLK_EIM_PODF>;
1220 clock-names = "dphy", "ref", "pix";
1221 status = "disabled";
1222 };
1223
1224 mipi_dsi: mipi@21e0000 {
1225 reg = <0x021e0000 0x4000>;
1226 status = "disabled";
1227
1228 ports {
1229 #address-cells = <1>;
1230 #size-cells = <0>;
1231
1232 port@0 {
1233 reg = <0>;
1234
1235 mipi_mux_0: endpoint {
1236 remote-endpoint = <&ipu1_di0_mipi>;
1237 };
1238 };
1239
1240 port@1 {
1241 reg = <1>;
1242
1243 mipi_mux_1: endpoint {
1244 remote-endpoint = <&ipu1_di1_mipi>;
1245 };
1246 };
1247 };
1248 };
1249
1250 vdoa@21e4000 {
1251 compatible = "fsl,imx6q-vdoa";
1252 reg = <0x021e4000 0x4000>;
1253 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
1254 clocks = <&clks IMX6QDL_CLK_VDOA>;
1255 };
1256
1257 uart2: serial@21e8000 {
1258 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1259 reg = <0x021e8000 0x4000>;
1260 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
1261 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1262 <&clks IMX6QDL_CLK_UART_SERIAL>;
1263 clock-names = "ipg", "per";
1264 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1265 dma-names = "rx", "tx";
1266 status = "disabled";
1267 };
1268
1269 uart3: serial@21ec000 {
1270 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1271 reg = <0x021ec000 0x4000>;
1272 interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
1273 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1274 <&clks IMX6QDL_CLK_UART_SERIAL>;
1275 clock-names = "ipg", "per";
1276 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1277 dma-names = "rx", "tx";
1278 status = "disabled";
1279 };
1280
1281 uart4: serial@21f0000 {
1282 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1283 reg = <0x021f0000 0x4000>;
1284 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
1285 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1286 <&clks IMX6QDL_CLK_UART_SERIAL>;
1287 clock-names = "ipg", "per";
1288 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1289 dma-names = "rx", "tx";
1290 status = "disabled";
1291 };
1292
1293 uart5: serial@21f4000 {
1294 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1295 reg = <0x021f4000 0x4000>;
1296 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
1297 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1298 <&clks IMX6QDL_CLK_UART_SERIAL>;
1299 clock-names = "ipg", "per";
1300 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1301 dma-names = "rx", "tx";
1302 status = "disabled";
1303 };
1304 };
1305
1306 ipu1: ipu@2400000 {
1307 #address-cells = <1>;
1308 #size-cells = <0>;
1309 compatible = "fsl,imx6q-ipu";
1310 reg = <0x02400000 0x400000>;
1311 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>,
1312 <0 5 IRQ_TYPE_LEVEL_HIGH>;
1313 clocks = <&clks IMX6QDL_CLK_IPU1>,
1314 <&clks IMX6QDL_CLK_IPU1_DI0>,
1315 <&clks IMX6QDL_CLK_IPU1_DI1>;
1316 clock-names = "bus", "di0", "di1";
1317 resets = <&src 2>;
1318
1319 ipu1_csi0: port@0 {
1320 reg = <0>;
1321
1322 ipu1_csi0_from_ipu1_csi0_mux: endpoint {
1323 remote-endpoint = <&ipu1_csi0_mux_to_ipu1_csi0>;
1324 };
1325 };
1326
1327 ipu1_csi1: port@1 {
1328 reg = <1>;
1329 };
1330
1331 ipu1_di0: port@2 {
1332 #address-cells = <1>;
1333 #size-cells = <0>;
1334 reg = <2>;
1335
1336 ipu1_di0_disp0: endpoint@0 {
1337 reg = <0>;
1338 };
1339
1340 ipu1_di0_hdmi: endpoint@1 {
1341 reg = <1>;
1342 remote-endpoint = <&hdmi_mux_0>;
1343 };
1344
1345 ipu1_di0_mipi: endpoint@2 {
1346 reg = <2>;
1347 remote-endpoint = <&mipi_mux_0>;
1348 };
1349
1350 ipu1_di0_lvds0: endpoint@3 {
1351 reg = <3>;
1352 remote-endpoint = <&lvds0_mux_0>;
1353 };
1354
1355 ipu1_di0_lvds1: endpoint@4 {
1356 reg = <4>;
1357 remote-endpoint = <&lvds1_mux_0>;
1358 };
1359 };
1360
1361 ipu1_di1: port@3 {
1362 #address-cells = <1>;
1363 #size-cells = <0>;
1364 reg = <3>;
1365
1366 ipu1_di1_disp1: endpoint@0 {
1367 reg = <0>;
1368 };
1369
1370 ipu1_di1_hdmi: endpoint@1 {
1371 reg = <1>;
1372 remote-endpoint = <&hdmi_mux_1>;
1373 };
1374
1375 ipu1_di1_mipi: endpoint@2 {
1376 reg = <2>;
1377 remote-endpoint = <&mipi_mux_1>;
1378 };
1379
1380 ipu1_di1_lvds0: endpoint@3 {
1381 reg = <3>;
1382 remote-endpoint = <&lvds0_mux_1>;
1383 };
1384
1385 ipu1_di1_lvds1: endpoint@4 {
1386 reg = <4>;
1387 remote-endpoint = <&lvds1_mux_1>;
1388 };
1389 };
1390 };
1391 };
1392};