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git01.mediatek.com / filogic / uboot / a03cb92688346145a51229f3467fe208c0ad6d9e / . / dts / upstream / Bindings / i2c / qcom,i2c-cci.yaml
blob: c33ae7b63b84f23fe1f53a092b169396e7e444b0 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/i2c/qcom,i2c-cci.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Camera Control Interface (CCI) I2C controller
8
9maintainers:
10 - Loic Poulain <loic.poulain@linaro.org>
11 - Robert Foss <robert.foss@linaro.org>
12
13properties:
14 compatible:
15 oneOf:
16 - enum:
17 - qcom,msm8226-cci
18 - qcom,msm8974-cci
19 - qcom,msm8996-cci
20
21 - items:
22 - enum:
23 - qcom,msm8916-cci
24 - const: qcom,msm8226-cci # CCI v1
25
26 - items:
27 - enum:
28 - qcom,sc7280-cci
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]29 - qcom,sc8280xp-cci
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]30 - qcom,sdm845-cci
31 - qcom,sm6350-cci
32 - qcom,sm8250-cci
33 - qcom,sm8450-cci
Tom Rini6b642ac2024-10-01 12:20:28 -0600[diff] [blame]34 - qcom,sm8550-cci
35 - qcom,sm8650-cci
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]36 - const: qcom,msm8996-cci # CCI v2
37
38 "#address-cells":
39 const: 1
40
41 "#size-cells":
42 const: 0
43
44 clocks:
45 minItems: 3
46 maxItems: 6
47
48 clock-names:
49 minItems: 3
50 maxItems: 6
51
52 interrupts:
53 maxItems: 1
54
55 power-domains:
56 maxItems: 1
57
58 reg:
59 maxItems: 1
60
61patternProperties:
62 "^i2c-bus@[01]$":
63 $ref: /schemas/i2c/i2c-controller.yaml#
64 unevaluatedProperties: false
65
66 properties:
67 reg:
68 maxItems: 1
69
70 clock-frequency:
71 default: 100000
72
73required:
74 - compatible
75 - clock-names
76 - clocks
77 - interrupts
78 - reg
79
80allOf:
81 - if:
82 properties:
83 compatible:
84 contains:
85 enum:
86 - qcom,msm8996-cci
87 then:
88 required:
89 - power-domains
90
91 - if:
92 properties:
93 compatible:
94 contains:
95 enum:
96 - qcom,msm8226-cci
97 - qcom,msm8916-cci
98 then:
99 properties:
100 i2c-bus@1: false
101
102 - if:
103 properties:
104 compatible:
105 oneOf:
106 - contains:
107 enum:
108 - qcom,msm8974-cci
109
110 - const: qcom,msm8226-cci
111 then:
112 properties:
113 clocks:
114 maxItems: 3
115 clock-names:
116 items:
117 - const: camss_top_ahb
118 - const: cci_ahb
119 - const: cci
120
121 - if:
122 properties:
123 compatible:
124 oneOf:
125 - contains:
126 enum:
127 - qcom,msm8916-cci
128
129 - const: qcom,msm8996-cci
130 then:
131 properties:
132 clocks:
133 maxItems: 4
134 clock-names:
135 items:
136 - const: camss_top_ahb
137 - const: cci_ahb
138 - const: cci
139 - const: camss_ahb
140
141 - if:
142 properties:
143 compatible:
144 contains:
145 enum:
146 - qcom,sdm845-cci
147 - qcom,sm6350-cci
148 then:
149 properties:
150 clocks:
151 minItems: 6
152 clock-names:
153 items:
154 - const: camnoc_axi
155 - const: soc_ahb
156 - const: slow_ahb_src
157 - const: cpas_ahb
158 - const: cci
159 - const: cci_src
160
161 - if:
162 properties:
163 compatible:
164 contains:
165 enum:
166 - qcom,sc7280-cci
167 - qcom,sm8250-cci
168 - qcom,sm8450-cci
169 then:
170 properties:
171 clocks:
172 minItems: 5
173 maxItems: 5
174 clock-names:
175 items:
176 - const: camnoc_axi
177 - const: slow_ahb_src
178 - const: cpas_ahb
179 - const: cci
180 - const: cci_src
181
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]182 - if:
183 properties:
184 compatible:
185 contains:
186 enum:
187 - qcom,sc8280xp-cci
188 then:
189 properties:
190 clocks:
191 minItems: 4
192 maxItems: 4
193 clock-names:
194 items:
195 - const: camnoc_axi
196 - const: slow_ahb_src
197 - const: cpas_ahb
198 - const: cci
199
Tom Rini6b642ac2024-10-01 12:20:28 -0600[diff] [blame]200 - if:
201 properties:
202 compatible:
203 contains:
204 enum:
205 - qcom,sm8550-cci
206 - qcom,sm8650-cci
207 then:
208 properties:
209 clocks:
210 minItems: 3
211 maxItems: 3
212 clock-names:
213 items:
214 - const: camnoc_axi
215 - const: cpas_ahb
216 - const: cci
217
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]218additionalProperties: false
219
220examples:
221 - |
222 #include <dt-bindings/clock/qcom,camcc-sdm845.h>
223 #include <dt-bindings/gpio/gpio.h>
224 #include <dt-bindings/interrupt-controller/arm-gic.h>
225
226 cci@ac4a000 {
227 reg = <0x0ac4a000 0x4000>;
228 compatible = "qcom,sdm845-cci", "qcom,msm8996-cci";
229 #address-cells = <1>;
230 #size-cells = <0>;
231
232 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
233 power-domains = <&clock_camcc TITAN_TOP_GDSC>;
234
235 clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
236 <&clock_camcc CAM_CC_SOC_AHB_CLK>,
237 <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
238 <&clock_camcc CAM_CC_CPAS_AHB_CLK>,
239 <&clock_camcc CAM_CC_CCI_CLK>,
240 <&clock_camcc CAM_CC_CCI_CLK_SRC>;
241 clock-names = "camnoc_axi",
242 "soc_ahb",
243 "slow_ahb_src",
244 "cpas_ahb",
245 "cci",
246 "cci_src";
247
248 assigned-clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
249 <&clock_camcc CAM_CC_CCI_CLK>;
250 assigned-clock-rates = <80000000>,
251 <37500000>;
252
253 pinctrl-names = "default", "sleep";
254 pinctrl-0 = <&cci0_default &cci1_default>;
255 pinctrl-1 = <&cci0_sleep &cci1_sleep>;
256
257 i2c-bus@0 {
258 reg = <0>;
259 clock-frequency = <1000000>;
260 #address-cells = <1>;
261 #size-cells = <0>;
262
263 camera@10 {
264 compatible = "ovti,ov8856";
265 reg = <0x10>;
266
267 reset-gpios = <&tlmm 9 GPIO_ACTIVE_LOW>;
268 pinctrl-names = "default";
269 pinctrl-0 = <&cam0_default>;
270
271 clocks = <&clock_camcc CAM_CC_MCLK0_CLK>;
272 clock-names = "xvclk";
273 clock-frequency = <19200000>;
274
275 dovdd-supply = <&vreg_lvs1a_1p8>;
276 avdd-supply = <&cam0_avdd_2v8>;
277 dvdd-supply = <&cam0_dvdd_1v2>;
278
279 port {
280 ov8856_ep: endpoint {
281 link-frequencies = /bits/ 64 <360000000 180000000>;
282 data-lanes = <1 2 3 4>;
283 remote-endpoint = <&csiphy0_ep>;
284 };
285 };
286 };
287 };
288
289 cci_i2c1: i2c-bus@1 {
290 reg = <1>;
291 clock-frequency = <1000000>;
292 #address-cells = <1>;
293 #size-cells = <0>;
294
295 camera@60 {
296 compatible = "ovti,ov7251";
297 reg = <0x60>;
298
299 enable-gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>;
300 pinctrl-names = "default";
301 pinctrl-0 = <&cam3_default>;
302
303 clocks = <&clock_camcc CAM_CC_MCLK3_CLK>;
304 clock-names = "xclk";
305 clock-frequency = <24000000>;
306
307 vdddo-supply = <&vreg_lvs1a_1p8>;
308 vdda-supply = <&cam3_avdd_2v8>;
309
310 port {
311 ov7251_ep: endpoint {
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]312 data-lanes = <0>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]313 link-frequencies = /bits/ 64 <240000000 319200000>;
314 remote-endpoint = <&csiphy3_ep>;
315 };
316 };
317 };
318 };
319 };