Dinh Nguyen | ad51f7c | 2012-10-04 06:46:02 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2012 Altera Corporation <www.altera.com> |
| 3 | * |
Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 4 | * SPDX-License-Identifier: GPL-2.0+ |
Dinh Nguyen | ad51f7c | 2012-10-04 06:46:02 +0000 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #include <common.h> |
| 8 | #include <asm/io.h> |
| 9 | #include <asm/arch/reset_manager.h> |
| 10 | |
| 11 | DECLARE_GLOBAL_DATA_PTR; |
| 12 | |
| 13 | static const struct socfpga_reset_manager *reset_manager_base = |
| 14 | (void *)SOCFPGA_RSTMGR_ADDRESS; |
| 15 | |
| 16 | /* |
| 17 | * Write the reset manager register to cause reset |
| 18 | */ |
| 19 | void reset_cpu(ulong addr) |
| 20 | { |
| 21 | /* request a warm reset */ |
| 22 | writel(RSTMGR_CTRL_SWWARMRSTREQ_LSB, &reset_manager_base->ctrl); |
| 23 | /* |
| 24 | * infinite loop here as watchdog will trigger and reset |
| 25 | * the processor |
| 26 | */ |
| 27 | while (1) |
| 28 | ; |
| 29 | } |
| 30 | |
| 31 | /* |
| 32 | * Release peripherals from reset based on handoff |
| 33 | */ |
| 34 | void reset_deassert_peripherals_handoff(void) |
| 35 | { |
| 36 | writel(0, &reset_manager_base->per_mod_reset); |
| 37 | } |
| 38 | |
| 39 | int dram_init(void) |
| 40 | { |
| 41 | gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); |
| 42 | return 0; |
| 43 | } |