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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Alexey Brodkin511ab042014-02-04 12:56:19 +04002/*
3 * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
Alexey Brodkin511ab042014-02-04 12:56:19 +04004 */
5
Simon Glass370382c2019-11-14 12:57:35 -07006#include <cpu_func.h>
Alexey Brodkin511ab042014-02-04 12:56:19 +04007#include <dwmmc.h>
Simon Glass97589732020-05-10 11:40:02 -06008#include <init.h>
Alexey Brodkin511ab042014-02-04 12:56:19 +04009#include <malloc.h>
Alexey Brodkin323dad42017-03-31 11:14:35 +030010#include <asm/arcregs.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060011#include <asm/global_data.h>
Alexey Brodkinf8f13b12015-04-09 19:50:58 +030012#include "axs10x.h"
Simon Glass274e0b02020-05-10 11:39:56 -060013#include <asm/cache.h>
Alexey Brodkin511ab042014-02-04 12:56:19 +040014
15DECLARE_GLOBAL_DATA_PTR;
16
Alexey Brodkinf8f13b12015-04-09 19:50:58 +030017#define AXS_MB_CREG 0xE0011000
18
19int board_early_init_f(void)
20{
21 if (readl((void __iomem *)AXS_MB_CREG + 0x234) & (1 << 28))
22 gd->board_type = AXS_MB_V3;
23 else
24 gd->board_type = AXS_MB_V2;
25
26 return 0;
27}
Alexey Brodkincf9cafd2015-04-13 13:37:05 +030028
29#ifdef CONFIG_ISA_ARCV2
Eugeniy Paltsev01f45cc2018-03-23 15:35:03 +030030
31void board_jump_and_run(ulong entry, int zero, int arch, uint params)
32{
33 void (*kernel_entry)(int zero, int arch, uint params);
34
35 kernel_entry = (void (*)(int, int, uint))entry;
36
37 smp_set_core_boot_addr(entry, -1);
38 smp_kick_all_cpus();
39 kernel_entry(zero, arch, params);
40}
41
Alexey Brodkincf9cafd2015-04-13 13:37:05 +030042#define RESET_VECTOR_ADDR 0x0
43
44void smp_set_core_boot_addr(unsigned long addr, int corenr)
45{
46 /* All cores have reset vector pointing to 0 */
47 writel(addr, (void __iomem *)RESET_VECTOR_ADDR);
48
49 /* Make sure other cores see written value in memory */
Alexey Brodkin0fda9642016-06-08 08:19:33 +030050 flush_dcache_all();
Alexey Brodkincf9cafd2015-04-13 13:37:05 +030051}
52
53void smp_kick_all_cpus(void)
54{
55/* CPU start CREG */
56#define AXC003_CREG_CPU_START 0xF0001400
Alexey Brodkincf9cafd2015-04-13 13:37:05 +030057/* Bits positions in CPU start CREG */
58#define BITS_START 0
Alexey Brodkinef5b5172017-03-30 19:18:30 +030059#define BITS_START_MODE 4
Alexey Brodkincf9cafd2015-04-13 13:37:05 +030060#define BITS_CORE_SEL 9
Alexey Brodkincf9cafd2015-04-13 13:37:05 +030061
Alexey Brodkin323dad42017-03-31 11:14:35 +030062/*
63 * In axs103 v1.1 START bits semantics has changed quite a bit.
64 * We used to have a generic START bit for all cores selected by CORE_SEL mask.
65 * But now we don't touch CORE_SEL at all because we have a dedicated START bit
66 * for each core:
67 * bit 0: Core 0 (master)
68 * bit 1: Core 1 (slave)
69 */
70#define BITS_START_CORE1 1
71
72#define ARCVER_HS38_3_0 0x53
73
74 int core_family = read_aux_reg(ARC_AUX_IDENTITY) & 0xff;
Alexey Brodkinef5b5172017-03-30 19:18:30 +030075 int cmd = readl((void __iomem *)AXC003_CREG_CPU_START);
Alexey Brodkin323dad42017-03-31 11:14:35 +030076
77 if (core_family < ARCVER_HS38_3_0) {
78 cmd |= (1 << BITS_CORE_SEL) | (1 << BITS_START);
79 cmd &= ~(1 << BITS_START_MODE);
80 } else {
81 cmd |= (1 << BITS_START_CORE1);
82 }
Alexey Brodkinef5b5172017-03-30 19:18:30 +030083 writel(cmd, (void __iomem *)AXC003_CREG_CPU_START);
Alexey Brodkincf9cafd2015-04-13 13:37:05 +030084}
85#endif
Alexey Brodkindbf9fa22018-11-27 09:47:01 +030086
87int checkboard(void)
88{
89 printf("Board: ARC Software Development Platform AXS%s\n",
90 is_isa_arcv2() ? "103" : "101");
91
92 return 0;
93};