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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Alexey Brodkin511ab042014-02-04 12:56:19 +04002/*
3 * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
Alexey Brodkin511ab042014-02-04 12:56:19 +04004 */
5
6#include <common.h>
Simon Glass370382c2019-11-14 12:57:35 -07007#include <cpu_func.h>
Alexey Brodkin511ab042014-02-04 12:56:19 +04008#include <dwmmc.h>
9#include <malloc.h>
Alexey Brodkin323dad42017-03-31 11:14:35 +030010#include <asm/arcregs.h>
Alexey Brodkinf8f13b12015-04-09 19:50:58 +030011#include "axs10x.h"
Alexey Brodkin511ab042014-02-04 12:56:19 +040012
13DECLARE_GLOBAL_DATA_PTR;
14
Alexey Brodkinf8f13b12015-04-09 19:50:58 +030015#define AXS_MB_CREG 0xE0011000
16
17int board_early_init_f(void)
18{
19 if (readl((void __iomem *)AXS_MB_CREG + 0x234) & (1 << 28))
20 gd->board_type = AXS_MB_V3;
21 else
22 gd->board_type = AXS_MB_V2;
23
24 return 0;
25}
Alexey Brodkincf9cafd2015-04-13 13:37:05 +030026
27#ifdef CONFIG_ISA_ARCV2
Eugeniy Paltsev01f45cc2018-03-23 15:35:03 +030028
29void board_jump_and_run(ulong entry, int zero, int arch, uint params)
30{
31 void (*kernel_entry)(int zero, int arch, uint params);
32
33 kernel_entry = (void (*)(int, int, uint))entry;
34
35 smp_set_core_boot_addr(entry, -1);
36 smp_kick_all_cpus();
37 kernel_entry(zero, arch, params);
38}
39
Alexey Brodkincf9cafd2015-04-13 13:37:05 +030040#define RESET_VECTOR_ADDR 0x0
41
42void smp_set_core_boot_addr(unsigned long addr, int corenr)
43{
44 /* All cores have reset vector pointing to 0 */
45 writel(addr, (void __iomem *)RESET_VECTOR_ADDR);
46
47 /* Make sure other cores see written value in memory */
Alexey Brodkin0fda9642016-06-08 08:19:33 +030048 flush_dcache_all();
Alexey Brodkincf9cafd2015-04-13 13:37:05 +030049}
50
51void smp_kick_all_cpus(void)
52{
53/* CPU start CREG */
54#define AXC003_CREG_CPU_START 0xF0001400
Alexey Brodkincf9cafd2015-04-13 13:37:05 +030055/* Bits positions in CPU start CREG */
56#define BITS_START 0
Alexey Brodkinef5b5172017-03-30 19:18:30 +030057#define BITS_START_MODE 4
Alexey Brodkincf9cafd2015-04-13 13:37:05 +030058#define BITS_CORE_SEL 9
Alexey Brodkincf9cafd2015-04-13 13:37:05 +030059
Alexey Brodkin323dad42017-03-31 11:14:35 +030060/*
61 * In axs103 v1.1 START bits semantics has changed quite a bit.
62 * We used to have a generic START bit for all cores selected by CORE_SEL mask.
63 * But now we don't touch CORE_SEL at all because we have a dedicated START bit
64 * for each core:
65 * bit 0: Core 0 (master)
66 * bit 1: Core 1 (slave)
67 */
68#define BITS_START_CORE1 1
69
70#define ARCVER_HS38_3_0 0x53
71
72 int core_family = read_aux_reg(ARC_AUX_IDENTITY) & 0xff;
Alexey Brodkinef5b5172017-03-30 19:18:30 +030073 int cmd = readl((void __iomem *)AXC003_CREG_CPU_START);
Alexey Brodkin323dad42017-03-31 11:14:35 +030074
75 if (core_family < ARCVER_HS38_3_0) {
76 cmd |= (1 << BITS_CORE_SEL) | (1 << BITS_START);
77 cmd &= ~(1 << BITS_START_MODE);
78 } else {
79 cmd |= (1 << BITS_START_CORE1);
80 }
Alexey Brodkinef5b5172017-03-30 19:18:30 +030081 writel(cmd, (void __iomem *)AXC003_CREG_CPU_START);
Alexey Brodkincf9cafd2015-04-13 13:37:05 +030082}
83#endif
Alexey Brodkindbf9fa22018-11-27 09:47:01 +030084
85int checkboard(void)
86{
87 printf("Board: ARC Software Development Platform AXS%s\n",
88 is_isa_arcv2() ? "103" : "101");
89
90 return 0;
91};