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git01.mediatek.com / filogic / uboot / 9ed4e81f4748cc7cdf8b8dba0c4019240617d4d8 / . / arch / arm / dts / tegra20-colibri.dts
blob: 9171319d98b996b1c601c524c7af2b07089cc635 [file] [log] [blame]
Lucas Stach85990a92012-10-07 11:36:06 +0000[diff] [blame]1/dts-v1/;
2
Tom Warrenf6236152013-02-21 12:31:27 +0000[diff] [blame]3#include "tegra20.dtsi"
Lucas Stach85990a92012-10-07 11:36:06 +0000[diff] [blame]4
5/ {
6 model = "Toradex Colibri T20";
Marcel Ziswiler2ec89a82015-08-06 00:47:01 +0200[diff] [blame]7 compatible = "toradex,colibri_t20", "nvidia,tegra20";
Lucas Stach85990a92012-10-07 11:36:06 +0000[diff] [blame]8
Simon Glass0c24f372014-09-04 16:27:35 -0600[diff] [blame]9 chosen {
10 stdout-path = &uarta;
11 };
12
Lucas Stach85990a92012-10-07 11:36:06 +0000[diff] [blame]13 aliases {
Marcel Ziswiler9a520202015-08-06 00:47:03 +0200[diff] [blame]14 i2c0 = "/i2c@7000d000";
15 i2c1 = "/i2c@7000c000";
16 i2c2 = "/i2c@7000c400";
Stephen Warrend55aadc2016-09-13 10:45:43 -0600[diff] [blame]17 mmc0 = "/sdhci@c8000600";
Marcel Ziswilercd873872016-09-28 11:24:09 +0200[diff] [blame]18 usb0 = "/usb@c5000000";
Marcel Ziswiler47065242016-12-19 15:38:07 +0100[diff] [blame]19 usb1 = "/usb@c5004000"; /* On-module only, for ASIX */
Marcel Ziswilercd873872016-09-28 11:24:09 +0200[diff] [blame]20 usb2 = "/usb@c5008000";
Lucas Stach85990a92012-10-07 11:36:06 +0000[diff] [blame]21 };
22
Simon Glasse31a2a52016-01-30 16:37:52 -0700[diff] [blame]23 host1x@50000000 {
Marcel Ziswilercbd2b512015-08-06 00:47:02 +0200[diff] [blame]24 dc@54200000 {
Marcel Ziswilercbd2b512015-08-06 00:47:02 +0200[diff] [blame]25 rgb {
26 status = "okay";
27 nvidia,panel = <&lcd_panel>;
Marcel Ziswiler6a3abf02016-09-28 11:24:08 +0200[diff] [blame]28 display-timings {
29 timing@0 {
30 /* VESA VGA */
31 clock-frequency = <25175000>;
32 hactive = <640>;
33 vactive = <480>;
34 hback-porch = <48>;
35 hfront-porch = <16>;
36 hsync-len = <96>;
37 vback-porch = <31>;
38 vfront-porch = <11>;
39 vsync-len = <2>;
40 };
41 };
Marcel Ziswilercbd2b512015-08-06 00:47:02 +0200[diff] [blame]42 };
43 };
44 };
45
Lucas Stach85990a92012-10-07 11:36:06 +0000[diff] [blame]46 nand-controller@70008000 {
Simon Glass3112fd52015-01-05 20:05:41 -0700[diff] [blame]47 nvidia,wp-gpios = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_HIGH>;
Lucas Stach85990a92012-10-07 11:36:06 +0000[diff] [blame]48 nvidia,width = <8>;
49 nvidia,timing = <15 100 25 80 25 10 15 10 100>;
50
51 nand@0 {
52 reg = <0>;
53 compatible = "nand-flash";
54 };
55 };
Tom Warrened955272013-02-21 12:31:29 +0000[diff] [blame]56
Marcel Ziswiler6a3abf02016-09-28 11:24:08 +0200[diff] [blame]57 pwm@7000a000 {
58 status = "okay";
59 };
60
Marcel Ziswiler9a520202015-08-06 00:47:03 +0200[diff] [blame]61 /*
62 * GEN1_I2C: I2C_SDA/SCL on SODIMM pin 194/196 (e.g. RTC on carrier
63 * board)
64 */
65 i2c@7000c000 {
66 status = "okay";
67 clock-frequency = <100000>;
68 };
69
70 /* GEN2_I2C: unused */
71
72 /* DDC_CLOCK/DATA on X3 pin 15/16 (e.g. display EDID) */
73 i2c@7000c400 {
74 status = "okay";
75 clock-frequency = <100000>;
76 };
77
78 /*
79 * PWR_I2C: power I2C to PMIC and temperature sensor
80 */
81 i2c@7000d000 {
82 status = "okay";
83 clock-frequency = <100000>;
84 };
85
Marcel Ziswilercd873872016-09-28 11:24:09 +0200[diff] [blame]86 /* EHCI instance 0: USB1_DP/N -> USBC_P/N */
87 usb@c5000000 {
88 status = "okay";
89 dr_mode = "otg";
90 };
91
92 /* EHCI instance 1: ULPI -> USB3340 -> AX88772B */
93 usb@c5004000 {
94 status = "okay";
Marcel Ziswiler47065242016-12-19 15:38:07 +0100[diff] [blame]95 /* ULPI_RESET */
96 nvidia,phy-reset-gpio =
97 <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_LOW>;
Marcel Ziswilercd873872016-09-28 11:24:09 +0200[diff] [blame]98 /* VBUS_LAN */
Marcel Ziswilercd873872016-09-28 11:24:09 +0200[diff] [blame]99 nvidia,vbus-gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>;
100 };
101
102 /* EHCI instance 2: USB3_DP/N -> USBH_P/N */
103 usb@c5008000 {
104 status = "okay";
105 /* USBH_PEN */
106 nvidia,vbus-gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
107 };
108
Tom Warrened955272013-02-21 12:31:29 +0000[diff] [blame]109 sdhci@c8000600 {
110 status = "okay";
Tom Warrened955272013-02-21 12:31:29 +0000[diff] [blame]111 bus-width = <4>;
Marcel Ziswiler764d4122015-08-06 00:47:10 +0200[diff] [blame]112 cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>;
Tom Warrened955272013-02-21 12:31:29 +0000[diff] [blame]113 };
Marcel Ziswilercbd2b512015-08-06 00:47:02 +0200[diff] [blame]114
Marcel Ziswiler6a3abf02016-09-28 11:24:08 +0200[diff] [blame]115 backlight: backlight {
116 compatible = "pwm-backlight";
117
118 brightness-levels = <255 128 64 32 16 8 4 0>;
119 default-brightness-level = <6>;
120 /* BL_ON */
121 enable-gpios = <&gpio TEGRA_GPIO(T, 4) GPIO_ACTIVE_HIGH>;
122 power-supply = <&reg_3v3>;
123 /* PWM<A> */
124 pwms = <&pwm 0 5000000>;
125 };
126
Simon Glasse31a2a52016-01-30 16:37:52 -0700[diff] [blame]127 clocks {
128 compatible = "simple-bus";
129 #address-cells = <1>;
130 #size-cells = <0>;
131
132 clk32k_in: clock@0 {
133 compatible = "fixed-clock";
134 reg=<0>;
135 #clock-cells = <0>;
136 clock-frequency = <32768>;
137 };
138 };
139
Marcel Ziswiler6a3abf02016-09-28 11:24:08 +0200[diff] [blame]140 lcd_panel: panel {
141 /*
142 * edt,et057090dhu: EDT 5.7" LCD TFT
143 * edt,et070080dh6: EDT 7.0" LCD TFT
144 */
145 compatible = "edt,et057090dhu", "simple-panel";
146
147 backlight = <&backlight>;
Simon Glassd8af3c92016-01-30 16:38:01 -0700[diff] [blame]148 };
149
Marcel Ziswiler6a3abf02016-09-28 11:24:08 +0200[diff] [blame]150 regulators {
151 compatible = "simple-bus";
152 #address-cells = <1>;
153 #size-cells = <0>;
154
155 reg_3v3: regulator@0 {
156 compatible = "regulator-fixed";
157 reg = <0>;
158 regulator-name = "+V3.3";
159 regulator-min-microvolt = <3300000>;
160 regulator-max-microvolt = <3300000>;
161 regulator-always-on;
162 };
Marcel Ziswilercbd2b512015-08-06 00:47:02 +0200[diff] [blame]163 };
Lucas Stach85990a92012-10-07 11:36:06 +0000[diff] [blame]164};
Simon Glass2a00cc92017-06-12 06:22:01 -0600[diff] [blame]165
166&uarta {
167 status = "okay";
168};