Lokesh Vutla | c7bfb85 | 2018-08-27 15:57:11 +0530 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 2 | /* |
Nishanth Menon | eaa39c6 | 2023-11-01 15:56:03 -0500 | [diff] [blame] | 3 | * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/ |
Lokesh Vutla | c7bfb85 | 2018-08-27 15:57:11 +0530 | [diff] [blame] | 4 | * Lokesh Vutla <lokeshvutla@ti.com> |
| 5 | */ |
| 6 | #ifndef _ASM_ARCH_HARDWARE_H_ |
| 7 | #define _ASM_ARCH_HARDWARE_H_ |
| 8 | |
Andrew Davis | 7d194c9 | 2023-04-06 11:38:11 -0500 | [diff] [blame] | 9 | #include <asm/io.h> |
| 10 | |
Andrew Davis | 1be5e97 | 2022-07-15 10:25:27 -0500 | [diff] [blame] | 11 | #ifdef CONFIG_SOC_K3_AM654 |
Lokesh Vutla | c7bfb85 | 2018-08-27 15:57:11 +0530 | [diff] [blame] | 12 | #include "am6_hardware.h" |
| 13 | #endif |
Lokesh Vutla | 6edde29 | 2019-06-13 10:29:43 +0530 | [diff] [blame] | 14 | |
| 15 | #ifdef CONFIG_SOC_K3_J721E |
| 16 | #include "j721e_hardware.h" |
| 17 | #endif |
Lokesh Vutla | a04cf3b | 2019-09-27 13:32:11 +0530 | [diff] [blame] | 18 | |
David Huang | 6109820 | 2022-01-25 20:56:31 +0530 | [diff] [blame] | 19 | #ifdef CONFIG_SOC_K3_J721S2 |
| 20 | #include "j721s2_hardware.h" |
| 21 | #endif |
| 22 | |
Keerthy | 05d670e | 2021-04-23 11:27:33 -0500 | [diff] [blame] | 23 | #ifdef CONFIG_SOC_K3_AM642 |
| 24 | #include "am64_hardware.h" |
| 25 | #endif |
| 26 | |
Suman Anna | 27fa412 | 2022-05-25 13:38:42 +0530 | [diff] [blame] | 27 | #ifdef CONFIG_SOC_K3_AM625 |
| 28 | #include "am62_hardware.h" |
| 29 | #endif |
| 30 | |
Bryan Brattlof | daa39a6 | 2022-11-03 19:13:55 -0500 | [diff] [blame] | 31 | #ifdef CONFIG_SOC_K3_AM62A7 |
| 32 | #include "am62a_hardware.h" |
Aradhya Bhatia | 94024e9 | 2023-04-14 12:57:25 +0530 | [diff] [blame] | 33 | #include "am62a_qos.h" |
Bryan Brattlof | daa39a6 | 2022-11-03 19:13:55 -0500 | [diff] [blame] | 34 | #endif |
| 35 | |
Lokesh Vutla | a04cf3b | 2019-09-27 13:32:11 +0530 | [diff] [blame] | 36 | /* Assuming these addresses and definitions stay common across K3 devices */ |
Andrew Davis | 990ec70 | 2022-10-07 14:22:05 -0500 | [diff] [blame] | 37 | #define CTRLMMR_WKUP_JTAG_ID (WKUP_CTRL_MMR0_BASE + 0x14) |
Lokesh Vutla | a04cf3b | 2019-09-27 13:32:11 +0530 | [diff] [blame] | 38 | #define JTAG_ID_VARIANT_SHIFT 28 |
| 39 | #define JTAG_ID_VARIANT_MASK (0xf << 28) |
| 40 | #define JTAG_ID_PARTNO_SHIFT 12 |
Lokesh Vutla | b407587 | 2020-04-17 13:43:53 +0530 | [diff] [blame] | 41 | #define JTAG_ID_PARTNO_MASK (0xffff << 12) |
Andrew Davis | 7d194c9 | 2023-04-06 11:38:11 -0500 | [diff] [blame] | 42 | #define JTAG_ID_PARTNO_AM65X 0xbb5a |
| 43 | #define JTAG_ID_PARTNO_J721E 0xbb64 |
| 44 | #define JTAG_ID_PARTNO_J7200 0xbb6d |
| 45 | #define JTAG_ID_PARTNO_AM64X 0xbb38 |
| 46 | #define JTAG_ID_PARTNO_J721S2 0xbb75 |
| 47 | #define JTAG_ID_PARTNO_AM62X 0xbb7e |
| 48 | #define JTAG_ID_PARTNO_AM62AX 0xbb8d |
| 49 | |
| 50 | #define K3_SOC_ID(id, ID) \ |
| 51 | static inline bool soc_is_##id(void) \ |
| 52 | { \ |
| 53 | u32 soc = (readl(CTRLMMR_WKUP_JTAG_ID) & \ |
| 54 | JTAG_ID_PARTNO_MASK) >> JTAG_ID_PARTNO_SHIFT; \ |
| 55 | return soc == JTAG_ID_PARTNO_##ID; \ |
| 56 | } |
| 57 | K3_SOC_ID(am65x, AM65X) |
| 58 | K3_SOC_ID(j721e, J721E) |
| 59 | K3_SOC_ID(j7200, J7200) |
| 60 | K3_SOC_ID(am64x, AM64X) |
| 61 | K3_SOC_ID(j721s2, J721S2) |
| 62 | K3_SOC_ID(am62x, AM62X) |
| 63 | K3_SOC_ID(am62ax, AM62AX) |
| 64 | |
Andrew Davis | f8c9836 | 2022-07-15 11:34:32 -0500 | [diff] [blame] | 65 | #define K3_SEC_MGR_SYS_STATUS 0x44234100 |
| 66 | #define SYS_STATUS_DEV_TYPE_SHIFT 0 |
| 67 | #define SYS_STATUS_DEV_TYPE_MASK (0xf) |
| 68 | #define SYS_STATUS_DEV_TYPE_GP 0x3 |
| 69 | #define SYS_STATUS_DEV_TYPE_TEST 0x5 |
| 70 | #define SYS_STATUS_DEV_TYPE_EMU 0x9 |
| 71 | #define SYS_STATUS_DEV_TYPE_HS 0xa |
| 72 | #define SYS_STATUS_SUB_TYPE_SHIFT 8 |
| 73 | #define SYS_STATUS_SUB_TYPE_MASK (0xf << 8) |
| 74 | #define SYS_STATUS_SUB_TYPE_VAL_FS 0xa |
Lokesh Vutla | a04cf3b | 2019-09-27 13:32:11 +0530 | [diff] [blame] | 75 | |
Andrew Davis | 990ec70 | 2022-10-07 14:22:05 -0500 | [diff] [blame] | 76 | /* |
| 77 | * The CTRL_MMR0 memory space is divided into several equally-spaced |
| 78 | * partitions, so defining the partition size allows us to determine |
| 79 | * register addresses common to those partitions. |
| 80 | */ |
| 81 | #define CTRL_MMR0_PARTITION_SIZE 0x4000 |
| 82 | |
| 83 | /* |
| 84 | * CTRL_MMR0, WKUP_CTRL_MMR0, and MCU_CTRL_MMR0 lock/kick-mechanism |
| 85 | * shared register definitions. The same registers are also used for |
| 86 | * PADCFG_MMR lock/kick-mechanism. |
| 87 | */ |
| 88 | #define CTRLMMR_LOCK_KICK0 0x1008 |
| 89 | #define CTRLMMR_LOCK_KICK0_UNLOCK_VAL 0x68ef3490 |
| 90 | #define CTRLMMR_LOCK_KICK1 0x100c |
| 91 | #define CTRLMMR_LOCK_KICK1_UNLOCK_VAL 0xd172bc5a |
| 92 | |
Lokesh Vutla | 8e7bd01 | 2020-08-05 22:44:22 +0530 | [diff] [blame] | 93 | #define K3_ROM_BOOT_HEADER_MAGIC "EXTBOOT" |
| 94 | |
| 95 | struct rom_extended_boot_data { |
| 96 | char header[8]; |
| 97 | u32 num_components; |
| 98 | }; |
| 99 | |
Aradhya Bhatia | 94024e9 | 2023-04-14 12:57:25 +0530 | [diff] [blame] | 100 | struct k3_qos_data { |
| 101 | u32 reg; |
| 102 | u32 val; |
| 103 | }; |
| 104 | |
| 105 | extern struct k3_qos_data am62a_qos_data[]; |
| 106 | extern u32 am62a_qos_count; |
| 107 | |
Lokesh Vutla | c7bfb85 | 2018-08-27 15:57:11 +0530 | [diff] [blame] | 108 | #endif /* _ASM_ARCH_HARDWARE_H_ */ |