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git01.mediatek.com / filogic / uboot / 9d6652c16bb33ce018e7ae1f169b1258cf318c36 / . / arch / arm / mach-socfpga / Kconfig
blob: 1a43c7bc9a70ba5025117b53511f2248a739549c [file] [log] [blame]
Masahiro Yamada144a3e02015-04-21 20:38:20 +0900[diff] [blame]1if ARCH_SOCFPGA
2
Marek Vasut822e7952015-08-02 21:57:57 +0200[diff] [blame]3config TARGET_SOCFPGA_ARRIA5
4 bool
Dinh Nguyen677a16f2015-12-02 13:31:25 -0600[diff] [blame]5 select TARGET_SOCFPGA_GEN5
Marek Vasut822e7952015-08-02 21:57:57 +0200[diff] [blame]6
7config TARGET_SOCFPGA_CYCLONE5
8 bool
Dinh Nguyen677a16f2015-12-02 13:31:25 -0600[diff] [blame]9 select TARGET_SOCFPGA_GEN5
10
11config TARGET_SOCFPGA_GEN5
12 bool
Marek Vasut822e7952015-08-02 21:57:57 +0200[diff] [blame]13
Masahiro Yamada144a3e02015-04-21 20:38:20 +0900[diff] [blame]14choice
15 prompt "Altera SOCFPGA board select"
Joe Hershbergerf0699602015-05-12 14:46:23 -0500[diff] [blame]16 optional
Masahiro Yamada144a3e02015-04-21 20:38:20 +0900[diff] [blame]17
Marek Vasut822e7952015-08-02 21:57:57 +0200[diff] [blame]18config TARGET_SOCFPGA_ARRIA5_SOCDK
19 bool "Altera SOCFPGA SoCDK (Arria V)"
20 select TARGET_SOCFPGA_ARRIA5
Masahiro Yamada144a3e02015-04-21 20:38:20 +0900[diff] [blame]21
Marek Vasut822e7952015-08-02 21:57:57 +0200[diff] [blame]22config TARGET_SOCFPGA_CYCLONE5_SOCDK
23 bool "Altera SOCFPGA SoCDK (Cyclone V)"
24 select TARGET_SOCFPGA_CYCLONE5
Masahiro Yamada144a3e02015-04-21 20:38:20 +0900[diff] [blame]25
Marek Vasut8e8b62a2015-08-03 01:37:28 +0200[diff] [blame]26config TARGET_SOCFPGA_DENX_MCVEVK
27 bool "DENX MCVEVK (Cyclone V)"
28 select TARGET_SOCFPGA_CYCLONE5
29
Marek Vasut567356a2015-11-23 17:06:27 +0100[diff] [blame]30config TARGET_SOCFPGA_EBV_SOCRATES
31 bool "EBV SoCrates (Cyclone V)"
32 select TARGET_SOCFPGA_CYCLONE5
33
Pavel Machek9802e872016-06-07 12:37:23 +0200[diff] [blame]34config TARGET_SOCFPGA_IS1
35 bool "IS1 (Cyclone V)"
36 select TARGET_SOCFPGA_CYCLONE5
37
Marek Vasutba2ade92015-12-01 18:09:52 +0100[diff] [blame]38config TARGET_SOCFPGA_SAMTEC_VINING_FPGA
39 bool "samtec VIN|ING FPGA (Cyclone V)"
40 select TARGET_SOCFPGA_CYCLONE5
41
Marek Vasut2e717ec2016-06-08 02:57:05 +0200[diff] [blame]42config TARGET_SOCFPGA_SR1500
43 bool "SR1500 (Cyclone V)"
44 select TARGET_SOCFPGA_CYCLONE5
45
Dinh Nguyenc3364da2015-09-01 17:41:52 -0500[diff] [blame]46config TARGET_SOCFPGA_TERASIC_DE0_NANO
47 bool "Terasic DE0-Nano-Atlas (Cyclone V)"
48 select TARGET_SOCFPGA_CYCLONE5
49
Marek Vasutb415bad2015-06-21 17:28:53 +0200[diff] [blame]50config TARGET_SOCFPGA_TERASIC_SOCKIT
51 bool "Terasic SoCkit (Cyclone V)"
52 select TARGET_SOCFPGA_CYCLONE5
53
Masahiro Yamada144a3e02015-04-21 20:38:20 +0900[diff] [blame]54endchoice
55
56config SYS_BOARD
Marek Vasut3f4c5612015-08-10 21:24:53 +0200[diff] [blame]57 default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
58 default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
Dinh Nguyenc3364da2015-09-01 17:41:52 -0500[diff] [blame]59 default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
Pavel Machek9802e872016-06-07 12:37:23 +0200[diff] [blame]60 default "is1" if TARGET_SOCFPGA_IS1
Marek Vasut8e8b62a2015-08-03 01:37:28 +0200[diff] [blame]61 default "mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
Marek Vasutb415bad2015-06-21 17:28:53 +0200[diff] [blame]62 default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
Marek Vasut567356a2015-11-23 17:06:27 +0100[diff] [blame]63 default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
Stefan Roesebf5ed2e2015-11-18 11:06:09 +0100[diff] [blame]64 default "sr1500" if TARGET_SOCFPGA_SR1500
Marek Vasutba2ade92015-12-01 18:09:52 +0100[diff] [blame]65 default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
Masahiro Yamada144a3e02015-04-21 20:38:20 +0900[diff] [blame]66
67config SYS_VENDOR
Marek Vasut822e7952015-08-02 21:57:57 +0200[diff] [blame]68 default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
69 default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
Marek Vasut8e8b62a2015-08-03 01:37:28 +0200[diff] [blame]70 default "denx" if TARGET_SOCFPGA_DENX_MCVEVK
Marek Vasut567356a2015-11-23 17:06:27 +0100[diff] [blame]71 default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
Marek Vasutba2ade92015-12-01 18:09:52 +0100[diff] [blame]72 default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
Dinh Nguyenc3364da2015-09-01 17:41:52 -0500[diff] [blame]73 default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
Marek Vasutb415bad2015-06-21 17:28:53 +0200[diff] [blame]74 default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
Masahiro Yamada144a3e02015-04-21 20:38:20 +0900[diff] [blame]75
76config SYS_SOC
77 default "socfpga"
78
79config SYS_CONFIG_NAME
Dinh Nguyen16f6ffd2015-09-22 17:01:32 -0500[diff] [blame]80 default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
81 default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
Dinh Nguyenc3364da2015-09-01 17:41:52 -0500[diff] [blame]82 default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
Pavel Machek9802e872016-06-07 12:37:23 +0200[diff] [blame]83 default "socfpga_is1" if TARGET_SOCFPGA_IS1
Marek Vasut8e8b62a2015-08-03 01:37:28 +0200[diff] [blame]84 default "socfpga_mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
Marek Vasutb415bad2015-06-21 17:28:53 +0200[diff] [blame]85 default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
Marek Vasut567356a2015-11-23 17:06:27 +0100[diff] [blame]86 default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
Stefan Roesebf5ed2e2015-11-18 11:06:09 +0100[diff] [blame]87 default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
Marek Vasutba2ade92015-12-01 18:09:52 +0100[diff] [blame]88 default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
Masahiro Yamada144a3e02015-04-21 20:38:20 +0900[diff] [blame]89
90endif