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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0
Vladimir Barinov2f8c00e2015-02-14 01:06:13 +03002/*
3 * board/renesas/porter/porter.c
4 *
5 * Copyright (C) 2015 Renesas Electronics Corporation
6 * Copyright (C) 2015 Cogent Embedded, Inc.
Vladimir Barinov2f8c00e2015-02-14 01:06:13 +03007 */
8
9#include <common.h>
Simon Glass0af6e2d2019-08-01 09:46:52 -060010#include <env.h>
Vladimir Barinov2f8c00e2015-02-14 01:06:13 +030011#include <malloc.h>
12#include <dm.h>
13#include <dm/platform_data/serial_sh.h>
Simon Glass9d1f6192019-08-02 09:44:25 -060014#include <env_internal.h>
Vladimir Barinov2f8c00e2015-02-14 01:06:13 +030015#include <asm/processor.h>
16#include <asm/mach-types.h>
17#include <asm/io.h>
Masahiro Yamada56a931c2016-09-21 11:28:55 +090018#include <linux/errno.h>
Vladimir Barinov2f8c00e2015-02-14 01:06:13 +030019#include <asm/arch/sys_proto.h>
20#include <asm/gpio.h>
21#include <asm/arch/rmobile.h>
22#include <asm/arch/rcar-mstp.h>
23#include <asm/arch/sh_sdhi.h>
24#include <netdev.h>
25#include <miiphy.h>
26#include <i2c.h>
27#include <div64.h>
28#include "qos.h"
29
30DECLARE_GLOBAL_DATA_PTR;
31
32#define CLK2MHZ(clk) (clk / 1000 / 1000)
33void s_init(void)
34{
35 struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
36 struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
37 u32 stc;
38
39 /* Watchdog init */
40 writel(0xA5A5A500, &rwdt->rwtcsra);
41 writel(0xA5A5A500, &swdt->swtcsra);
42
43 /* CPU frequency setting. Set to 1.5GHz */
44 stc = ((1500 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_BIT;
45 clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
46
47 /* QoS */
48 qos_init();
49}
50
Marek Vasuta5bbe262018-01-07 19:32:56 +010051#define TMU0_MSTP125 BIT(25)
Vladimir Barinov2f8c00e2015-02-14 01:06:13 +030052
53#define SD2CKCR 0xE615026C
54#define SD_97500KHZ 0x7
55
56int board_early_init_f(void)
57{
58 mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
59
Vladimir Barinov2f8c00e2015-02-14 01:06:13 +030060 /*
61 * SD0 clock is set to 97.5MHz by default.
62 * Set SD2 to the 97.5MHz as well.
63 */
64 writel(SD_97500KHZ, SD2CKCR);
65
66 return 0;
67}
68
Marek Vasutb97daa62018-02-17 00:35:23 +010069#define ETHERNET_PHY_RESET 176 /* GPIO 5 22 */
70
Vladimir Barinov2f8c00e2015-02-14 01:06:13 +030071int board_init(void)
72{
73 /* adress of boot parameters */
74 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
75
Marek Vasutb97daa62018-02-17 00:35:23 +010076 /* Force ethernet PHY out of reset */
77 gpio_request(ETHERNET_PHY_RESET, "phy_reset");
78 gpio_direction_output(ETHERNET_PHY_RESET, 0);
79 mdelay(10);
80 gpio_direction_output(ETHERNET_PHY_RESET, 1);
81
Vladimir Barinov2f8c00e2015-02-14 01:06:13 +030082 return 0;
83}
84
Marek Vasuta5bbe262018-01-07 19:32:56 +010085int dram_init(void)
Vladimir Barinov2f8c00e2015-02-14 01:06:13 +030086{
Siva Durga Prasad Paladugub3d55ea2018-07-16 15:56:11 +053087 if (fdtdec_setup_mem_size_base() != 0)
Marek Vasuta5bbe262018-01-07 19:32:56 +010088 return -EINVAL;
Vladimir Barinov2f8c00e2015-02-14 01:06:13 +030089
Vladimir Barinov2f8c00e2015-02-14 01:06:13 +030090 return 0;
Vladimir Barinov2f8c00e2015-02-14 01:06:13 +030091}
92
Marek Vasuta5bbe262018-01-07 19:32:56 +010093int dram_init_banksize(void)
Vladimir Barinov2f8c00e2015-02-14 01:06:13 +030094{
Marek Vasuta5bbe262018-01-07 19:32:56 +010095 fdtdec_setup_memory_banksize();
Vladimir Barinov2f8c00e2015-02-14 01:06:13 +030096
97 return 0;
98}
99
100/* porter has KSZ8041RNLI */
101#define PHY_CONTROL1 0x1E
Marek Vasut9580a452019-03-30 07:05:09 +0100102#define PHY_LED_MODE 0xC000
Vladimir Barinov2f8c00e2015-02-14 01:06:13 +0300103#define PHY_LED_MODE_ACK 0x4000
104int board_phy_config(struct phy_device *phydev)
105{
106 int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1);
107 ret &= ~PHY_LED_MODE;
108 ret |= PHY_LED_MODE_ACK;
109 ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret);
110
111 return 0;
112}
113
Vladimir Barinov2f8c00e2015-02-14 01:06:13 +0300114void reset_cpu(ulong addr)
115{
Marek Vasut5e61b942018-02-17 02:16:48 +0100116 struct udevice *dev;
117 const u8 pmic_bus = 6;
118 const u8 pmic_addr = 0x5a;
119 u8 data;
120 int ret;
121
122 ret = i2c_get_chip_for_busnum(pmic_bus, pmic_addr, 1, &dev);
123 if (ret)
124 hang();
125
126 ret = dm_i2c_read(dev, 0x13, &data, 1);
127 if (ret)
128 hang();
129
130 data |= BIT(1);
Vladimir Barinov2f8c00e2015-02-14 01:06:13 +0300131
Marek Vasut5e61b942018-02-17 02:16:48 +0100132 ret = dm_i2c_write(dev, 0x13, &data, 1);
133 if (ret)
134 hang();
Vladimir Barinov2f8c00e2015-02-14 01:06:13 +0300135}
Marek Vasutebcf2812018-04-17 02:49:48 +0200136
137enum env_location env_get_location(enum env_operation op, int prio)
138{
139 const u32 load_magic = 0xb33fc0de;
140
141 /* Block environment access if loaded using JTAG */
142 if ((readl(CONFIG_SPL_TEXT_BASE + 0x24) == load_magic) &&
143 (op != ENVOP_INIT))
144 return ENVL_UNKNOWN;
145
146 if (prio)
147 return ENVL_UNKNOWN;
148
149 return ENVL_SPI_FLASH;
150}