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git01.mediatek.com / filogic / uboot / 9d1f6196dda01b9cc76d3a3ff3beb26f62e0a5d7 / . / arch / arm / dts / stm32mp157-u-boot.dtsi
blob: 8102ce20d0d7c0f92c8b4b0b46a916eaa95208cc [file] [log] [blame]
Tom Rini8b0c8a12018-05-06 18:27:01 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
Patrick Delaunay06020d82018-03-12 10:46:17 +0100[diff] [blame]2/*
3 * Copyright : STMicroelectronics 2018
Patrick Delaunay06020d82018-03-12 10:46:17 +0100[diff] [blame]4 */
5
6/ {
7 aliases {
8 gpio0 = &gpioa;
9 gpio1 = &gpiob;
10 gpio2 = &gpioc;
11 gpio3 = &gpiod;
12 gpio4 = &gpioe;
13 gpio5 = &gpiof;
14 gpio6 = &gpiog;
15 gpio7 = &gpioh;
16 gpio8 = &gpioi;
17 gpio9 = &gpioj;
18 gpio10 = &gpiok;
19 gpio25 = &gpioz;
Patrick Delaunay1b58b552019-04-12 14:38:28 +0200[diff] [blame]20 pinctrl0 = &pinctrl;
21 pinctrl1 = &pinctrl_z;
Patrick Delaunay06020d82018-03-12 10:46:17 +0100[diff] [blame]22 };
23
Patrick Delaunaya3705302019-07-11 11:15:28 +0200[diff] [blame]24 clocks {
Patrick Delaunay06020d82018-03-12 10:46:17 +0100[diff] [blame]25 u-boot,dm-pre-reloc;
26 };
27
Patrick Delaunaya3705302019-07-11 11:15:28 +0200[diff] [blame]28 reboot {
Patrick Delaunay06020d82018-03-12 10:46:17 +0100[diff] [blame]29 u-boot,dm-pre-reloc;
30 };
31
32 soc {
33 u-boot,dm-pre-reloc;
Patrick Delaunay089d4352018-03-20 11:45:14 +0100[diff] [blame]34 };
Patrick Delaunay06020d82018-03-12 10:46:17 +0100[diff] [blame]35};
36
Patrick Delaunaybdd71362019-02-27 17:01:27 +0100[diff] [blame]37&bsec {
Patrick Delaunaya3705302019-07-11 11:15:28 +0200[diff] [blame]38 u-boot,dm-pre-proper;
Patrick Delaunay06020d82018-03-12 10:46:17 +0100[diff] [blame]39};
40
Patrick Delaunay06020d82018-03-12 10:46:17 +0100[diff] [blame]41&clk_csi {
42 u-boot,dm-pre-reloc;
43};
44
Patrick Delaunaya3705302019-07-11 11:15:28 +0200[diff] [blame]45&clk_hsi {
Patrick Delaunay06020d82018-03-12 10:46:17 +0100[diff] [blame]46 u-boot,dm-pre-reloc;
47};
48
Patrick Delaunaya3705302019-07-11 11:15:28 +0200[diff] [blame]49&clk_hse {
Patrick Delaunay32ddd262018-03-20 14:15:06 +0100[diff] [blame]50 u-boot,dm-pre-reloc;
51};
52
Patrick Delaunaya3705302019-07-11 11:15:28 +0200[diff] [blame]53&clk_lsi {
Patrick Delaunay06020d82018-03-12 10:46:17 +0100[diff] [blame]54 u-boot,dm-pre-reloc;
55};
56
Patrick Delaunaya3705302019-07-11 11:15:28 +0200[diff] [blame]57&clk_lse {
Patrick Delaunay06020d82018-03-12 10:46:17 +0100[diff] [blame]58 u-boot,dm-pre-reloc;
59};
60
61&gpioa {
Patrick Delaunay06020d82018-03-12 10:46:17 +0100[diff] [blame]62 u-boot,dm-pre-reloc;
63};
64
65&gpiob {
Patrick Delaunay06020d82018-03-12 10:46:17 +0100[diff] [blame]66 u-boot,dm-pre-reloc;
67};
68
69&gpioc {
Patrick Delaunay06020d82018-03-12 10:46:17 +0100[diff] [blame]70 u-boot,dm-pre-reloc;
71};
72
73&gpiod {
Patrick Delaunay06020d82018-03-12 10:46:17 +0100[diff] [blame]74 u-boot,dm-pre-reloc;
75};
76
77&gpioe {
Patrick Delaunay06020d82018-03-12 10:46:17 +0100[diff] [blame]78 u-boot,dm-pre-reloc;
79};
80
81&gpiof {
Patrick Delaunay06020d82018-03-12 10:46:17 +0100[diff] [blame]82 u-boot,dm-pre-reloc;
83};
84
85&gpiog {
Patrick Delaunay06020d82018-03-12 10:46:17 +0100[diff] [blame]86 u-boot,dm-pre-reloc;
87};
88
89&gpioh {
Patrick Delaunay06020d82018-03-12 10:46:17 +0100[diff] [blame]90 u-boot,dm-pre-reloc;
91};
92
93&gpioi {
Patrick Delaunay06020d82018-03-12 10:46:17 +0100[diff] [blame]94 u-boot,dm-pre-reloc;
95};
96
97&gpioj {
Patrick Delaunay06020d82018-03-12 10:46:17 +0100[diff] [blame]98 u-boot,dm-pre-reloc;
99};
100
101&gpiok {
Patrick Delaunay06020d82018-03-12 10:46:17 +0100[diff] [blame]102 u-boot,dm-pre-reloc;
103};
104
105&gpioz {
Patrick Delaunay06020d82018-03-12 10:46:17 +0100[diff] [blame]106 u-boot,dm-pre-reloc;
107};
Patrice Chotard26d11072019-04-30 17:26:21 +0200[diff] [blame]108
Patrick Delaunaya3705302019-07-11 11:15:28 +0200[diff] [blame]109&pinctrl {
110 u-boot,dm-pre-reloc;
111};
112
113&pinctrl_z {
114 u-boot,dm-pre-reloc;
115};
116
117&pwr {
Patrice Chotard26d11072019-04-30 17:26:21 +0200[diff] [blame]118 u-boot,dm-pre-reloc;
119};
Patrick Delaunaya3705302019-07-11 11:15:28 +0200[diff] [blame]120
121&rcc {
122 u-boot,dm-pre-reloc;
123};
124
125&sdmmc1 {
126 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
127};
128
129&sdmmc2 {
130 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
131};
132
133&sdmmc3 {
134 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
135};
136
137&usbotg_hs {
138 compatible = "st,stm32mp1-hsotg", "snps,dwc2";
139};