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git01.mediatek.com / filogic / uboot / 9d1f6196dda01b9cc76d3a3ff3beb26f62e0a5d7 / . / arch / arm / dts / k3-am65-main.dtsi
blob: 7d037060576960d622890cf7769be438f75b3391 [file] [log] [blame]
Lokesh Vutla8bfaf012018-08-27 15:59:08 +0530[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for AM6 SoC Family Main Domain peripherals
4 *
5 * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
6 */
7
8&cbass_main {
9 gic500: interrupt-controller@1800000 {
10 compatible = "arm,gic-v3";
Lokesh Vutla3d09ed32018-11-02 19:51:08 +0530[diff] [blame]11 #address-cells = <2>;
12 #size-cells = <2>;
Lokesh Vutla8bfaf012018-08-27 15:59:08 +0530[diff] [blame]13 ranges;
14 #interrupt-cells = <3>;
15 interrupt-controller;
Lokesh Vutla3d09ed32018-11-02 19:51:08 +0530[diff] [blame]16 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
17 <0x00 0x01880000 0x00 0x90000>; /* GICR */
Lokesh Vutla8bfaf012018-08-27 15:59:08 +0530[diff] [blame]18 /*
19 * vcpumntirq:
20 * virtual CPU interface maintenance interrupt
21 */
22 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
23
24 gic_its: gic-its@18200000 {
25 compatible = "arm,gic-v3-its";
Lokesh Vutla3d09ed32018-11-02 19:51:08 +0530[diff] [blame]26 reg = <0x00 0x01820000 0x00 0x10000>;
Lokesh Vutla8bfaf012018-08-27 15:59:08 +0530[diff] [blame]27 msi-controller;
28 #msi-cells = <1>;
29 };
30 };
Lokesh Vutla3d09ed32018-11-02 19:51:08 +0530[diff] [blame]31
32 secure_proxy_main: mailbox@32c00000 {
33 compatible = "ti,am654-secure-proxy";
34 #mbox-cells = <1>;
35 reg-names = "target_data", "rt", "scfg";
36 reg = <0x00 0x32c00000 0x00 0x100000>,
37 <0x00 0x32400000 0x00 0x100000>,
38 <0x00 0x32800000 0x00 0x100000>;
39 interrupt-names = "rx_011";
40 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
41 };
42
43 main_uart0: serial@2800000 {
44 compatible = "ti,am654-uart";
45 reg = <0x00 0x02800000 0x00 0x100>;
46 reg-shift = <2>;
47 reg-io-width = <4>;
48 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
49 clock-frequency = <48000000>;
50 current-speed = <115200>;
51 };
52
53 main_uart1: serial@2810000 {
54 compatible = "ti,am654-uart";
55 reg = <0x00 0x02810000 0x00 0x100>;
56 reg-shift = <2>;
57 reg-io-width = <4>;
58 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
59 clock-frequency = <48000000>;
60 current-speed = <115200>;
61 };
62
63 main_uart2: serial@2820000 {
64 compatible = "ti,am654-uart";
65 reg = <0x00 0x02820000 0x00 0x100>;
66 reg-shift = <2>;
67 reg-io-width = <4>;
68 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
69 clock-frequency = <48000000>;
70 current-speed = <115200>;
71 };
Faiz Abbasd8fb3092019-06-11 00:43:31 +0530[diff] [blame]72
73 main_pmx0: pinmux@11c000 {
74 compatible = "pinctrl-single";
75 reg = <0x0 0x11c000 0x0 0x2e4>;
76 #pinctrl-cells = <1>;
77 pinctrl-single,register-width = <32>;
78 pinctrl-single,function-mask = <0xffffffff>;
79 };
80
Andreas Dannenberg9976b862019-06-04 18:08:13 -0500[diff] [blame]81 main_pmx1: pinmux@11c2e8 {
82 compatible = "pinctrl-single";
83 reg = <0x0 0x11c2e8 0x0 0x24>;
84 #pinctrl-cells = <1>;
85 pinctrl-single,register-width = <32>;
86 pinctrl-single,function-mask = <0xffffffff>;
87 };
88
Faiz Abbasd8fb3092019-06-11 00:43:31 +0530[diff] [blame]89 sdhci0: sdhci@4f80000 {
90 compatible = "ti,am654-sdhci-5.1";
91 reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>;
Lokesh Vutla61ff6a32019-06-07 19:24:47 +0530[diff] [blame]92 power-domains = <&k3_pds 47 TI_SCI_PD_EXCLUSIVE>;
Faiz Abbasd8fb3092019-06-11 00:43:31 +0530[diff] [blame]93 clocks = <&k3_clks 47 0>, <&k3_clks 47 1>;
94 clock-names = "clk_ahb", "clk_xin";
95 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
96 mmc-ddr-1_8v;
97 mmc-hs200-1_8v;
98 ti,otap-del-sel = <0x2>;
99 ti,trm-icp = <0x8>;
100 dma-coherent;
101 };
Andreas Dannenberge3179be2019-06-04 18:08:14 -0500[diff] [blame]102
103 main_i2c0: i2c@2000000 {
104 compatible = "ti,am654-i2c", "ti,omap4-i2c";
105 reg = <0x0 0x2000000 0x0 0x100>;
106 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
107 #address-cells = <1>;
108 #size-cells = <0>;
109 clock-names = "fck";
110 clocks = <&k3_clks 110 1>;
Lokesh Vutla61ff6a32019-06-07 19:24:47 +0530[diff] [blame]111 power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
Andreas Dannenberge3179be2019-06-04 18:08:14 -0500[diff] [blame]112 };
113
114 main_i2c1: i2c@2010000 {
115 compatible = "ti,am654-i2c", "ti,omap4-i2c";
116 reg = <0x0 0x2010000 0x0 0x100>;
117 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
118 #address-cells = <1>;
119 #size-cells = <0>;
120 clock-names = "fck";
121 clocks = <&k3_clks 111 1>;
Lokesh Vutla61ff6a32019-06-07 19:24:47 +0530[diff] [blame]122 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
Andreas Dannenberge3179be2019-06-04 18:08:14 -0500[diff] [blame]123 };
124
125 main_i2c2: i2c@2020000 {
126 compatible = "ti,am654-i2c", "ti,omap4-i2c";
127 reg = <0x0 0x2020000 0x0 0x100>;
128 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
129 #address-cells = <1>;
130 #size-cells = <0>;
131 clock-names = "fck";
132 clocks = <&k3_clks 112 1>;
Lokesh Vutla61ff6a32019-06-07 19:24:47 +0530[diff] [blame]133 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
Andreas Dannenberge3179be2019-06-04 18:08:14 -0500[diff] [blame]134 };
135
136 main_i2c3: i2c@2030000 {
137 compatible = "ti,am654-i2c", "ti,omap4-i2c";
138 reg = <0x0 0x2030000 0x0 0x100>;
139 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
140 #address-cells = <1>;
141 #size-cells = <0>;
142 clock-names = "fck";
143 clocks = <&k3_clks 113 1>;
Lokesh Vutla61ff6a32019-06-07 19:24:47 +0530[diff] [blame]144 power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
Andreas Dannenberge3179be2019-06-04 18:08:14 -0500[diff] [blame]145 };
Lokesh Vutla8bfaf012018-08-27 15:59:08 +0530[diff] [blame]146};