blob: a556acd5cb5f6c30e0a9fcea1c6d9397562b4542 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Marek Vasut06485cf2018-04-08 15:22:58 +02002/*
3 * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
Marek Vasut06485cf2018-04-08 15:22:58 +02004 */
5
6#include <common.h>
7#include <clk.h>
8#include <fdtdec.h>
9#include <mmc.h>
10#include <dm.h>
11#include <linux/compat.h>
12#include <linux/dma-direction.h>
13#include <linux/io.h>
14#include <linux/sizes.h>
15#include <power/regulator.h>
16#include <asm/unaligned.h>
17
Marek Vasutfd83e762018-04-13 23:51:33 +020018#include "tmio-common.h"
Marek Vasut06485cf2018-04-08 15:22:58 +020019
Marek Vasut10d77ed2018-06-13 08:02:55 +020020#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
21 CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
22 CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
Marek Vasute0781e42018-04-08 19:09:17 +020023
24/* SCC registers */
25#define RENESAS_SDHI_SCC_DTCNTL 0x800
26#define RENESAS_SDHI_SCC_DTCNTL_TAPEN BIT(0)
27#define RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT 16
28#define RENESAS_SDHI_SCC_DTCNTL_TAPNUM_MASK 0xff
29#define RENESAS_SDHI_SCC_TAPSET 0x804
30#define RENESAS_SDHI_SCC_DT2FF 0x808
31#define RENESAS_SDHI_SCC_CKSEL 0x80c
32#define RENESAS_SDHI_SCC_CKSEL_DTSEL BIT(0)
33#define RENESAS_SDHI_SCC_RVSCNTL 0x810
34#define RENESAS_SDHI_SCC_RVSCNTL_RVSEN BIT(0)
35#define RENESAS_SDHI_SCC_RVSREQ 0x814
36#define RENESAS_SDHI_SCC_RVSREQ_RVSERR BIT(2)
37#define RENESAS_SDHI_SCC_SMPCMP 0x818
38#define RENESAS_SDHI_SCC_TMPPORT2 0x81c
Marek Vasutefea7a82018-06-13 08:02:55 +020039#define RENESAS_SDHI_SCC_TMPPORT2_HS400EN BIT(31)
40#define RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL BIT(4)
Marek Vasute0781e42018-04-08 19:09:17 +020041
42#define RENESAS_SDHI_MAX_TAP 3
43
Marek Vasutfd83e762018-04-13 23:51:33 +020044static unsigned int renesas_sdhi_init_tuning(struct tmio_sd_priv *priv)
Marek Vasute0781e42018-04-08 19:09:17 +020045{
46 u32 reg;
47
48 /* Initialize SCC */
Marek Vasutfd83e762018-04-13 23:51:33 +020049 tmio_sd_writel(priv, 0, TMIO_SD_INFO1);
Marek Vasute0781e42018-04-08 19:09:17 +020050
Marek Vasutfd83e762018-04-13 23:51:33 +020051 reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
52 reg &= ~TMIO_SD_CLKCTL_SCLKEN;
53 tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
Marek Vasute0781e42018-04-08 19:09:17 +020054
55 /* Set sampling clock selection range */
Marek Vasutda4873d2018-06-13 08:02:55 +020056 tmio_sd_writel(priv, (0x8 << RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) |
57 RENESAS_SDHI_SCC_DTCNTL_TAPEN,
58 RENESAS_SDHI_SCC_DTCNTL);
Marek Vasute0781e42018-04-08 19:09:17 +020059
Marek Vasutfd83e762018-04-13 23:51:33 +020060 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL);
Marek Vasute0781e42018-04-08 19:09:17 +020061 reg |= RENESAS_SDHI_SCC_CKSEL_DTSEL;
Marek Vasutfd83e762018-04-13 23:51:33 +020062 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL);
Marek Vasute0781e42018-04-08 19:09:17 +020063
Marek Vasutfd83e762018-04-13 23:51:33 +020064 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
Marek Vasute0781e42018-04-08 19:09:17 +020065 reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
Marek Vasutfd83e762018-04-13 23:51:33 +020066 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
Marek Vasute0781e42018-04-08 19:09:17 +020067
Marek Vasutfd83e762018-04-13 23:51:33 +020068 tmio_sd_writel(priv, 0x300 /* scc_tappos */,
Marek Vasute0781e42018-04-08 19:09:17 +020069 RENESAS_SDHI_SCC_DT2FF);
70
Marek Vasutfd83e762018-04-13 23:51:33 +020071 reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
72 reg |= TMIO_SD_CLKCTL_SCLKEN;
73 tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
Marek Vasute0781e42018-04-08 19:09:17 +020074
75 /* Read TAPNUM */
Marek Vasutfd83e762018-04-13 23:51:33 +020076 return (tmio_sd_readl(priv, RENESAS_SDHI_SCC_DTCNTL) >>
Marek Vasute0781e42018-04-08 19:09:17 +020077 RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) &
78 RENESAS_SDHI_SCC_DTCNTL_TAPNUM_MASK;
79}
80
Marek Vasutfd83e762018-04-13 23:51:33 +020081static void renesas_sdhi_reset_tuning(struct tmio_sd_priv *priv)
Marek Vasute0781e42018-04-08 19:09:17 +020082{
83 u32 reg;
84
85 /* Reset SCC */
Marek Vasutfd83e762018-04-13 23:51:33 +020086 reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
87 reg &= ~TMIO_SD_CLKCTL_SCLKEN;
88 tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
Marek Vasute0781e42018-04-08 19:09:17 +020089
Marek Vasutfd83e762018-04-13 23:51:33 +020090 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL);
Marek Vasute0781e42018-04-08 19:09:17 +020091 reg &= ~RENESAS_SDHI_SCC_CKSEL_DTSEL;
Marek Vasutfd83e762018-04-13 23:51:33 +020092 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL);
Marek Vasute0781e42018-04-08 19:09:17 +020093
Marek Vasutefea7a82018-06-13 08:02:55 +020094 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_TMPPORT2);
95 reg &= ~(RENESAS_SDHI_SCC_TMPPORT2_HS400EN |
96 RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL);
97 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_TMPPORT2);
98
Marek Vasutfd83e762018-04-13 23:51:33 +020099 reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
100 reg |= TMIO_SD_CLKCTL_SCLKEN;
101 tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
Marek Vasute0781e42018-04-08 19:09:17 +0200102
Marek Vasutfd83e762018-04-13 23:51:33 +0200103 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
Marek Vasute0781e42018-04-08 19:09:17 +0200104 reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
Marek Vasutfd83e762018-04-13 23:51:33 +0200105 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
Marek Vasute0781e42018-04-08 19:09:17 +0200106
Marek Vasutfd83e762018-04-13 23:51:33 +0200107 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
Marek Vasute0781e42018-04-08 19:09:17 +0200108 reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
Marek Vasutfd83e762018-04-13 23:51:33 +0200109 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
Marek Vasute0781e42018-04-08 19:09:17 +0200110}
111
Marek Vasut10d77ed2018-06-13 08:02:55 +0200112static int renesas_sdhi_hs400(struct udevice *dev)
113{
114 struct tmio_sd_priv *priv = dev_get_priv(dev);
115 struct mmc *mmc = mmc_get_mmc_dev(dev);
116 bool hs400 = (mmc->selected_mode == MMC_HS_400);
117 int ret, taps = hs400 ? priv->nrtaps : 8;
118 u32 reg;
119
120 if (taps == 4) /* HS400 on 4tap SoC needs different clock */
121 ret = clk_set_rate(&priv->clk, 400000000);
122 else
123 ret = clk_set_rate(&priv->clk, 200000000);
124 if (ret < 0)
125 return ret;
126
127 tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_RVSREQ);
128
129 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_TMPPORT2);
130 if (hs400) {
131 reg |= RENESAS_SDHI_SCC_TMPPORT2_HS400EN |
132 RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL;
133 } else {
134 reg &= ~(RENESAS_SDHI_SCC_TMPPORT2_HS400EN |
135 RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL);
136 }
137
138 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_TMPPORT2);
139
140 tmio_sd_writel(priv, (taps << RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) |
141 RENESAS_SDHI_SCC_DTCNTL_TAPEN,
142 RENESAS_SDHI_SCC_DTCNTL);
143
144 if (taps == 4) {
145 tmio_sd_writel(priv, priv->tap_set >> 1,
146 RENESAS_SDHI_SCC_TAPSET);
147 } else {
148 tmio_sd_writel(priv, priv->tap_set, RENESAS_SDHI_SCC_TAPSET);
149 }
150
151 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL);
152 reg |= RENESAS_SDHI_SCC_CKSEL_DTSEL;
153 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL);
154
155 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
156 reg |= RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
157 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
158
159 return 0;
160}
161
Marek Vasutfd83e762018-04-13 23:51:33 +0200162static void renesas_sdhi_prepare_tuning(struct tmio_sd_priv *priv,
Marek Vasute0781e42018-04-08 19:09:17 +0200163 unsigned long tap)
164{
165 /* Set sampling clock position */
Marek Vasutfd83e762018-04-13 23:51:33 +0200166 tmio_sd_writel(priv, tap, RENESAS_SDHI_SCC_TAPSET);
Marek Vasute0781e42018-04-08 19:09:17 +0200167}
168
Marek Vasutfd83e762018-04-13 23:51:33 +0200169static unsigned int renesas_sdhi_compare_scc_data(struct tmio_sd_priv *priv)
Marek Vasute0781e42018-04-08 19:09:17 +0200170{
171 /* Get comparison of sampling data */
Marek Vasutfd83e762018-04-13 23:51:33 +0200172 return tmio_sd_readl(priv, RENESAS_SDHI_SCC_SMPCMP);
Marek Vasute0781e42018-04-08 19:09:17 +0200173}
174
Marek Vasutfd83e762018-04-13 23:51:33 +0200175static int renesas_sdhi_select_tuning(struct tmio_sd_priv *priv,
Marek Vasute0781e42018-04-08 19:09:17 +0200176 unsigned int tap_num, unsigned int taps,
177 unsigned int smpcmp)
178{
179 unsigned long tap_cnt; /* counter of tuning success */
Marek Vasute0781e42018-04-08 19:09:17 +0200180 unsigned long tap_start;/* start position of tuning success */
181 unsigned long tap_end; /* end position of tuning success */
182 unsigned long ntap; /* temporary counter of tuning success */
183 unsigned long match_cnt;/* counter of matching data */
184 unsigned long i;
185 bool select = false;
186 u32 reg;
187
188 /* Clear SCC_RVSREQ */
Marek Vasutfd83e762018-04-13 23:51:33 +0200189 tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_RVSREQ);
Marek Vasute0781e42018-04-08 19:09:17 +0200190
191 /* Merge the results */
192 for (i = 0; i < tap_num * 2; i++) {
193 if (!(taps & BIT(i))) {
194 taps &= ~BIT(i % tap_num);
195 taps &= ~BIT((i % tap_num) + tap_num);
196 }
197 if (!(smpcmp & BIT(i))) {
198 smpcmp &= ~BIT(i % tap_num);
199 smpcmp &= ~BIT((i % tap_num) + tap_num);
200 }
201 }
202
203 /*
204 * Find the longest consecutive run of successful probes. If that
205 * is more than RENESAS_SDHI_MAX_TAP probes long then use the
206 * center index as the tap.
207 */
208 tap_cnt = 0;
209 ntap = 0;
210 tap_start = 0;
211 tap_end = 0;
212 for (i = 0; i < tap_num * 2; i++) {
213 if (taps & BIT(i))
214 ntap++;
215 else {
216 if (ntap > tap_cnt) {
217 tap_start = i - ntap;
218 tap_end = i - 1;
219 tap_cnt = ntap;
220 }
221 ntap = 0;
222 }
223 }
224
225 if (ntap > tap_cnt) {
226 tap_start = i - ntap;
227 tap_end = i - 1;
228 tap_cnt = ntap;
229 }
230
231 /*
232 * If all of the TAP is OK, the sampling clock position is selected by
233 * identifying the change point of data.
234 */
235 if (tap_cnt == tap_num * 2) {
236 match_cnt = 0;
237 ntap = 0;
238 tap_start = 0;
239 tap_end = 0;
240 for (i = 0; i < tap_num * 2; i++) {
241 if (smpcmp & BIT(i))
242 ntap++;
243 else {
244 if (ntap > match_cnt) {
245 tap_start = i - ntap;
246 tap_end = i - 1;
247 match_cnt = ntap;
248 }
249 ntap = 0;
250 }
251 }
252 if (ntap > match_cnt) {
253 tap_start = i - ntap;
254 tap_end = i - 1;
255 match_cnt = ntap;
256 }
257 if (match_cnt)
258 select = true;
259 } else if (tap_cnt >= RENESAS_SDHI_MAX_TAP)
260 select = true;
261
262 if (select)
Marek Vasut1ebb9d62018-06-13 08:02:55 +0200263 priv->tap_set = ((tap_start + tap_end) / 2) % tap_num;
Marek Vasute0781e42018-04-08 19:09:17 +0200264 else
265 return -EIO;
266
267 /* Set SCC */
Marek Vasut1ebb9d62018-06-13 08:02:55 +0200268 tmio_sd_writel(priv, priv->tap_set, RENESAS_SDHI_SCC_TAPSET);
Marek Vasute0781e42018-04-08 19:09:17 +0200269
270 /* Enable auto re-tuning */
Marek Vasutfd83e762018-04-13 23:51:33 +0200271 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
Marek Vasute0781e42018-04-08 19:09:17 +0200272 reg |= RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
Marek Vasutfd83e762018-04-13 23:51:33 +0200273 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
Marek Vasute0781e42018-04-08 19:09:17 +0200274
275 return 0;
276}
277
278int renesas_sdhi_execute_tuning(struct udevice *dev, uint opcode)
279{
Marek Vasutfd83e762018-04-13 23:51:33 +0200280 struct tmio_sd_priv *priv = dev_get_priv(dev);
Marek Vasute0781e42018-04-08 19:09:17 +0200281 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
282 struct mmc *mmc = upriv->mmc;
283 unsigned int tap_num;
284 unsigned int taps = 0, smpcmp = 0;
285 int i, ret = 0;
286 u32 caps;
287
288 /* Only supported on Renesas RCar */
Marek Vasutfd83e762018-04-13 23:51:33 +0200289 if (!(priv->caps & TMIO_SD_CAP_RCAR_UHS))
Marek Vasute0781e42018-04-08 19:09:17 +0200290 return -EINVAL;
291
292 /* clock tuning is not needed for upto 52MHz */
293 if (!((mmc->selected_mode == MMC_HS_200) ||
Marek Vasut10d77ed2018-06-13 08:02:55 +0200294 (mmc->selected_mode == MMC_HS_400) ||
Marek Vasute0781e42018-04-08 19:09:17 +0200295 (mmc->selected_mode == UHS_SDR104) ||
296 (mmc->selected_mode == UHS_SDR50)))
297 return 0;
298
299 tap_num = renesas_sdhi_init_tuning(priv);
300 if (!tap_num)
301 /* Tuning is not supported */
302 goto out;
303
304 if (tap_num * 2 >= sizeof(taps) * 8) {
305 dev_err(dev,
306 "Too many taps, skipping tuning. Please consider updating size of taps field of tmio_mmc_host\n");
307 goto out;
308 }
309
310 /* Issue CMD19 twice for each tap */
311 for (i = 0; i < 2 * tap_num; i++) {
312 renesas_sdhi_prepare_tuning(priv, i % tap_num);
313
314 /* Force PIO for the tuning */
315 caps = priv->caps;
Marek Vasutfd83e762018-04-13 23:51:33 +0200316 priv->caps &= ~TMIO_SD_CAP_DMA_INTERNAL;
Marek Vasute0781e42018-04-08 19:09:17 +0200317
318 ret = mmc_send_tuning(mmc, opcode, NULL);
319
320 priv->caps = caps;
321
322 if (ret == 0)
323 taps |= BIT(i);
324
325 ret = renesas_sdhi_compare_scc_data(priv);
326 if (ret == 0)
327 smpcmp |= BIT(i);
328
329 mdelay(1);
330 }
331
332 ret = renesas_sdhi_select_tuning(priv, tap_num, taps, smpcmp);
333
334out:
335 if (ret < 0) {
336 dev_warn(dev, "Tuning procedure failed\n");
337 renesas_sdhi_reset_tuning(priv);
338 }
339
340 return ret;
341}
Marek Vasut10d77ed2018-06-13 08:02:55 +0200342#else
343static int renesas_sdhi_hs400(struct udevice *dev)
344{
345 return 0;
346}
Marek Vasute0781e42018-04-08 19:09:17 +0200347#endif
348
349static int renesas_sdhi_set_ios(struct udevice *dev)
350{
Marek Vasut10d77ed2018-06-13 08:02:55 +0200351 struct tmio_sd_priv *priv = dev_get_priv(dev);
352 u32 tmp;
353 int ret;
Marek Vasut33d38182018-04-09 20:47:31 +0200354
Marek Vasut10d77ed2018-06-13 08:02:55 +0200355 /* Stop the clock before changing its rate to avoid a glitch signal */
356 tmp = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
357 tmp &= ~TMIO_SD_CLKCTL_SCLKEN;
358 tmio_sd_writel(priv, tmp, TMIO_SD_CLKCTL);
Marek Vasut33d38182018-04-09 20:47:31 +0200359
Marek Vasut10d77ed2018-06-13 08:02:55 +0200360 ret = renesas_sdhi_hs400(dev);
361 if (ret)
362 return ret;
Marek Vasute0781e42018-04-08 19:09:17 +0200363
Marek Vasut10d77ed2018-06-13 08:02:55 +0200364 ret = tmio_sd_set_ios(dev);
365
366 mdelay(10);
367
368#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
369 CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
370 CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
371 struct mmc *mmc = mmc_get_mmc_dev(dev);
372 if ((priv->caps & TMIO_SD_CAP_RCAR_UHS) &&
373 (mmc->selected_mode != UHS_SDR104) &&
374 (mmc->selected_mode != MMC_HS_200) &&
375 (mmc->selected_mode != MMC_HS_400)) {
Marek Vasut35773802018-10-28 15:30:06 +0100376 renesas_sdhi_reset_tuning(priv);
Marek Vasut10d77ed2018-06-13 08:02:55 +0200377 }
Marek Vasute0781e42018-04-08 19:09:17 +0200378#endif
379
380 return ret;
381}
382
Marek Vasut576a6d92018-10-28 19:28:56 +0100383#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
384static int renesas_sdhi_wait_dat0(struct udevice *dev, int state, int timeout)
385{
386 int ret = -ETIMEDOUT;
387 bool dat0_high;
388 bool target_dat0_high = !!state;
389 struct tmio_sd_priv *priv = dev_get_priv(dev);
390
391 timeout = DIV_ROUND_UP(timeout, 10); /* check every 10 us. */
392 while (timeout--) {
393 dat0_high = !!(tmio_sd_readl(priv, TMIO_SD_INFO2) & TMIO_SD_INFO2_DAT0);
394 if (dat0_high == target_dat0_high) {
395 ret = 0;
396 break;
397 }
398 udelay(10);
399 }
400
401 return ret;
402}
403#endif
404
Marek Vasut06485cf2018-04-08 15:22:58 +0200405static const struct dm_mmc_ops renesas_sdhi_ops = {
Marek Vasutfd83e762018-04-13 23:51:33 +0200406 .send_cmd = tmio_sd_send_cmd,
Marek Vasute0781e42018-04-08 19:09:17 +0200407 .set_ios = renesas_sdhi_set_ios,
Marek Vasutfd83e762018-04-13 23:51:33 +0200408 .get_cd = tmio_sd_get_cd,
Marek Vasut10d77ed2018-06-13 08:02:55 +0200409#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
410 CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
411 CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
Marek Vasute0781e42018-04-08 19:09:17 +0200412 .execute_tuning = renesas_sdhi_execute_tuning,
413#endif
Marek Vasut576a6d92018-10-28 19:28:56 +0100414#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
415 .wait_dat0 = renesas_sdhi_wait_dat0,
416#endif
Marek Vasut06485cf2018-04-08 15:22:58 +0200417};
418
Marek Vasutfd83e762018-04-13 23:51:33 +0200419#define RENESAS_GEN2_QUIRKS TMIO_SD_CAP_RCAR_GEN2
Marek Vasut9db9e6a2018-04-08 18:49:52 +0200420#define RENESAS_GEN3_QUIRKS \
Marek Vasutfd83e762018-04-13 23:51:33 +0200421 TMIO_SD_CAP_64BIT | TMIO_SD_CAP_RCAR_GEN3 | TMIO_SD_CAP_RCAR_UHS
Marek Vasut9db9e6a2018-04-08 18:49:52 +0200422
Marek Vasut06485cf2018-04-08 15:22:58 +0200423static const struct udevice_id renesas_sdhi_match[] = {
Marek Vasut9db9e6a2018-04-08 18:49:52 +0200424 { .compatible = "renesas,sdhi-r8a7790", .data = RENESAS_GEN2_QUIRKS },
425 { .compatible = "renesas,sdhi-r8a7791", .data = RENESAS_GEN2_QUIRKS },
426 { .compatible = "renesas,sdhi-r8a7792", .data = RENESAS_GEN2_QUIRKS },
427 { .compatible = "renesas,sdhi-r8a7793", .data = RENESAS_GEN2_QUIRKS },
428 { .compatible = "renesas,sdhi-r8a7794", .data = RENESAS_GEN2_QUIRKS },
429 { .compatible = "renesas,sdhi-r8a7795", .data = RENESAS_GEN3_QUIRKS },
430 { .compatible = "renesas,sdhi-r8a7796", .data = RENESAS_GEN3_QUIRKS },
431 { .compatible = "renesas,sdhi-r8a77965", .data = RENESAS_GEN3_QUIRKS },
432 { .compatible = "renesas,sdhi-r8a77970", .data = RENESAS_GEN3_QUIRKS },
Marek Vasut8b2ae7d2018-04-26 13:19:29 +0200433 { .compatible = "renesas,sdhi-r8a77990", .data = RENESAS_GEN3_QUIRKS },
Marek Vasut9db9e6a2018-04-08 18:49:52 +0200434 { .compatible = "renesas,sdhi-r8a77995", .data = RENESAS_GEN3_QUIRKS },
Marek Vasut06485cf2018-04-08 15:22:58 +0200435 { /* sentinel */ }
436};
437
Marek Vasutda90a1b2018-06-13 08:02:55 +0200438static ulong renesas_sdhi_clk_get_rate(struct tmio_sd_priv *priv)
439{
440 return clk_get_rate(&priv->clk);
441}
442
Marek Vasutb59180a2018-06-13 08:02:55 +0200443static void renesas_sdhi_filter_caps(struct udevice *dev)
444{
445 struct tmio_sd_plat *plat = dev_get_platdata(dev);
446 struct tmio_sd_priv *priv = dev_get_priv(dev);
447
448 if (!(priv->caps & TMIO_SD_CAP_RCAR_GEN3))
449 return;
450
451 /* HS400 is not supported on H3 ES1.x and M3W ES1.0,ES1.1 */
452 if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
453 (rmobile_get_cpu_rev_integer() <= 1)) ||
454 ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
455 (rmobile_get_cpu_rev_integer() == 1) &&
456 (rmobile_get_cpu_rev_fraction() <= 1)))
457 plat->cfg.host_caps &= ~MMC_MODE_HS400;
Marek Vasut10d77ed2018-06-13 08:02:55 +0200458
459 /* H3 ES2.0 uses 4 tuning taps */
460 if ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
461 (rmobile_get_cpu_rev_integer() == 2))
462 priv->nrtaps = 4;
463 else
464 priv->nrtaps = 8;
Marek Vasute9a28222019-01-11 23:45:54 +0100465
466 /* H3 ES1.x and M3W ES1.0 uses bit 17 for DTRAEND */
467 if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
468 (rmobile_get_cpu_rev_integer() <= 1)) ||
469 ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
470 (rmobile_get_cpu_rev_integer() == 1) &&
471 (rmobile_get_cpu_rev_fraction() == 0)))
472 priv->read_poll_flag = TMIO_SD_DMA_INFO1_END_RD;
473 else
474 priv->read_poll_flag = TMIO_SD_DMA_INFO1_END_RD2;
Marek Vasutb59180a2018-06-13 08:02:55 +0200475}
476
Marek Vasutabe3e952018-04-08 17:45:23 +0200477static int renesas_sdhi_probe(struct udevice *dev)
478{
Masahiro Yamada19989d832018-04-20 18:14:24 +0900479 struct tmio_sd_priv *priv = dev_get_priv(dev);
Marek Vasutabe3e952018-04-08 17:45:23 +0200480 u32 quirks = dev_get_driver_data(dev);
Marek Vasut1949d482018-04-08 18:14:22 +0200481 struct fdt_resource reg_res;
482 DECLARE_GLOBAL_DATA_PTR;
483 int ret;
484
Marek Vasutda90a1b2018-06-13 08:02:55 +0200485 priv->clk_get_rate = renesas_sdhi_clk_get_rate;
486
Marek Vasut9db9e6a2018-04-08 18:49:52 +0200487 if (quirks == RENESAS_GEN2_QUIRKS) {
488 ret = fdt_get_resource(gd->fdt_blob, dev_of_offset(dev),
489 "reg", 0, &reg_res);
490 if (ret < 0) {
491 dev_err(dev, "\"reg\" resource not found, ret=%i\n",
492 ret);
493 return ret;
494 }
Marek Vasut1949d482018-04-08 18:14:22 +0200495
Marek Vasut9db9e6a2018-04-08 18:49:52 +0200496 if (fdt_resource_size(&reg_res) == 0x100)
Marek Vasutfd83e762018-04-13 23:51:33 +0200497 quirks |= TMIO_SD_CAP_16BIT;
Marek Vasut9db9e6a2018-04-08 18:49:52 +0200498 }
Marek Vasutabe3e952018-04-08 17:45:23 +0200499
Marek Vasutda90a1b2018-06-13 08:02:55 +0200500 ret = clk_get_by_index(dev, 0, &priv->clk);
Masahiro Yamada19989d832018-04-20 18:14:24 +0900501 if (ret < 0) {
502 dev_err(dev, "failed to get host clock\n");
503 return ret;
504 }
505
506 /* set to max rate */
Marek Vasutda90a1b2018-06-13 08:02:55 +0200507 ret = clk_set_rate(&priv->clk, 200000000);
508 if (ret < 0) {
Masahiro Yamada19989d832018-04-20 18:14:24 +0900509 dev_err(dev, "failed to set rate for host clock\n");
Marek Vasutda90a1b2018-06-13 08:02:55 +0200510 clk_free(&priv->clk);
511 return ret;
Masahiro Yamada19989d832018-04-20 18:14:24 +0900512 }
513
Marek Vasutda90a1b2018-06-13 08:02:55 +0200514 ret = clk_enable(&priv->clk);
Masahiro Yamada19989d832018-04-20 18:14:24 +0900515 if (ret) {
516 dev_err(dev, "failed to enable host clock\n");
517 return ret;
518 }
519
Marek Vasutfd83e762018-04-13 23:51:33 +0200520 ret = tmio_sd_probe(dev, quirks);
Marek Vasutb59180a2018-06-13 08:02:55 +0200521
522 renesas_sdhi_filter_caps(dev);
523
Marek Vasut10d77ed2018-06-13 08:02:55 +0200524#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
525 CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
526 CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
Marek Vasut35773802018-10-28 15:30:06 +0100527 if (!ret && (priv->caps & TMIO_SD_CAP_RCAR_UHS))
Marek Vasutda70ebb2018-08-30 15:27:26 +0200528 renesas_sdhi_reset_tuning(priv);
Marek Vasute0781e42018-04-08 19:09:17 +0200529#endif
530 return ret;
Marek Vasutabe3e952018-04-08 17:45:23 +0200531}
532
Marek Vasut06485cf2018-04-08 15:22:58 +0200533U_BOOT_DRIVER(renesas_sdhi) = {
534 .name = "renesas-sdhi",
535 .id = UCLASS_MMC,
536 .of_match = renesas_sdhi_match,
Marek Vasutfd83e762018-04-13 23:51:33 +0200537 .bind = tmio_sd_bind,
Marek Vasutabe3e952018-04-08 17:45:23 +0200538 .probe = renesas_sdhi_probe,
Marek Vasutfd83e762018-04-13 23:51:33 +0200539 .priv_auto_alloc_size = sizeof(struct tmio_sd_priv),
540 .platdata_auto_alloc_size = sizeof(struct tmio_sd_plat),
Marek Vasut06485cf2018-04-08 15:22:58 +0200541 .ops = &renesas_sdhi_ops,
542};