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git01.mediatek.com / filogic / uboot / 9c8af15f86b602d32dc0a1e638467c05b8792439 / . / src / arm / nxp / imx / imx6qdl-wandboard.dtsi
blob: 7130b9c3b3aa052944b2e25ba15fdcb1add57901 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright 2013 Freescale Semiconductor, Inc.
4 *
5 * Author: Fabio Estevam <fabio.estevam@freescale.com>
6 */
7
8#include <dt-bindings/gpio/gpio.h>
9
10/ {
11 chosen {
12 stdout-path = &uart1;
13 };
14
15 sound {
16 compatible = "fsl,imx6-wandboard-sgtl5000",
17 "fsl,imx-audio-sgtl5000";
18 model = "imx6-wandboard-sgtl5000";
19 ssi-controller = <&ssi1>;
20 audio-codec = <&codec>;
21 audio-routing =
22 "MIC_IN", "Mic Jack",
23 "Mic Jack", "Mic Bias",
24 "Headphone Jack", "HP_OUT";
25 mux-int-port = <1>;
26 mux-ext-port = <3>;
27 };
28
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame^]29 spdif_out: spdif-out {
30 compatible = "linux,spdif-dit";
31 #sound-dai-cells = <0>;
32 };
33
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]34 sound-spdif {
35 compatible = "fsl,imx-audio-spdif";
36 model = "imx-spdif";
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame^]37 audio-cpu = <&spdif>;
38 audio-codec = <&spdif_out>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]39 };
40
41 reg_1p5v: regulator-1p5v {
42 compatible = "regulator-fixed";
43 regulator-name = "1P5V";
44 regulator-min-microvolt = <1500000>;
45 regulator-max-microvolt = <1500000>;
46 regulator-always-on;
47 };
48
49 reg_1p8v: regulator-1p8v {
50 compatible = "regulator-fixed";
51 regulator-name = "1P8V";
52 regulator-min-microvolt = <1800000>;
53 regulator-max-microvolt = <1800000>;
54 regulator-always-on;
55 };
56
57 reg_2p8v: regulator-2p8v {
58 compatible = "regulator-fixed";
59 regulator-name = "2P8V";
60 regulator-min-microvolt = <2800000>;
61 regulator-max-microvolt = <2800000>;
62 regulator-always-on;
63 };
64
65 reg_2p5v: regulator-2p5v {
66 compatible = "regulator-fixed";
67 regulator-name = "2P5V";
68 regulator-min-microvolt = <2500000>;
69 regulator-max-microvolt = <2500000>;
70 regulator-always-on;
71 };
72
73 reg_3p3v: regulator-3p3v {
74 compatible = "regulator-fixed";
75 regulator-name = "3P3V";
76 regulator-min-microvolt = <3300000>;
77 regulator-max-microvolt = <3300000>;
78 regulator-always-on;
79 };
80
81 reg_usb_otg_vbus: regulator-usbotgvbus {
82 compatible = "regulator-fixed";
83 regulator-name = "usb_otg_vbus";
84 regulator-min-microvolt = <5000000>;
85 regulator-max-microvolt = <5000000>;
86 pinctrl-names = "default";
87 pinctrl-0 = <&pinctrl_usbotgvbus>;
88 gpio = <&gpio3 22 GPIO_ACTIVE_LOW>;
89 };
90};
91
92&audmux {
93 pinctrl-names = "default";
94 pinctrl-0 = <&pinctrl_audmux>;
95 status = "okay";
96};
97
98&hdmi {
99 ddc-i2c-bus = <&i2c1>;
100 status = "okay";
101};
102
103&i2c1 {
104 clock-frequency = <100000>;
105 pinctrl-names = "default", "gpio";
106 pinctrl-0 = <&pinctrl_i2c1>;
107 pinctrl-1 = <&pinctrl_i2c1_gpio>;
108 scl-gpios = <&gpio3 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
109 sda-gpios = <&gpio3 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
110 status = "okay";
111};
112
113&i2c2 {
114 clock-frequency = <100000>;
115 pinctrl-names = "default", "gpio";
116 pinctrl-0 = <&pinctrl_i2c2>;
117 pinctrl-1 = <&pinctrl_i2c2_gpio>;
118 scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
119 sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
120 status = "okay";
121
122 codec: sgtl5000@a {
123 pinctrl-names = "default";
124 pinctrl-0 = <&pinctrl_mclk>;
125 compatible = "fsl,sgtl5000";
126 reg = <0x0a>;
127 #sound-dai-cells = <0>;
128 clocks = <&clks IMX6QDL_CLK_CKO>;
129 VDDA-supply = <&reg_2p5v>;
130 VDDIO-supply = <&reg_3p3v>;
131 lrclk-strength = <3>;
132 };
133
134 camera@3c {
135 compatible = "ovti,ov5645";
136 pinctrl-names = "default";
137 pinctrl-0 = <&pinctrl_ov5645>;
138 reg = <0x3c>;
139 clocks = <&clks IMX6QDL_CLK_CKO2>;
140 clock-frequency = <24000000>;
141 vdddo-supply = <&reg_1p8v>;
142 vdda-supply = <&reg_2p8v>;
143 vddd-supply = <&reg_1p5v>;
144 enable-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
145 reset-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>;
146
147 port {
148 ov5645_to_mipi_csi2: endpoint {
149 remote-endpoint = <&mipi_csi2_in>;
150 clock-lanes = <0>;
151 data-lanes = <1 2>;
152 };
153 };
154 };
155};
156
157&iomuxc {
158 pinctrl-names = "default";
159
160 imx6qdl-wandboard {
161
162 pinctrl_audmux: audmuxgrp {
163 fsl,pins = <
164 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
165 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
166 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
167 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
168 >;
169 };
170
171 pinctrl_enet: enetgrp {
172 fsl,pins = <
173 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
174 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
175 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
176 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
177 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
178 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
179 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
180 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
181 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
182 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
183 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
184 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
185 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
186 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
187 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
188 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
189 >;
190 };
191
192 pinctrl_i2c1: i2c1grp {
193 fsl,pins = <
194 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
195 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
196 >;
197 };
198
199 pinctrl_i2c1_gpio: i2c1gpiogrp {
200 fsl,pins = <
201 MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b0
202 MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b0
203 >;
204 };
205
206 pinctrl_i2c2: i2c2grp {
207 fsl,pins = <
208 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
209 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
210 >;
211 };
212
213 pinctrl_i2c2_gpio: i2c2gpiogrp {
214 fsl,pins = <
215 MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b0
216 MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b0
217 >;
218 };
219
220 pinctrl_mclk: mclkgrp {
221 fsl,pins = <
222 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
223 >;
224 };
225
226 pinctrl_ov5645: ov5645grp {
227 fsl,pins = <
228 MX6QDL_PAD_GPIO_3__CCM_CLKO2 0x000b0
229 MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0
230 MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0
231 >;
232 };
233
234 pinctrl_spdif: spdifgrp {
235 fsl,pins = <
236 MX6QDL_PAD_ENET_RXD0__SPDIF_OUT 0x1b0b0
237 >;
238 };
239
240 pinctrl_uart1: uart1grp {
241 fsl,pins = <
242 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
243 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
244 >;
245 };
246
247 pinctrl_uart3: uart3grp {
248 fsl,pins = <
249 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
250 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
251 MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1
252 MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1
253 >;
254 };
255
256 pinctrl_usbotg: usbotggrp {
257 fsl,pins = <
258 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
259 >;
260 };
261
262 pinctrl_usbotgvbus: usbotgvbusgrp {
263 fsl,pins = <
264 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x130b0
265 >;
266 };
267
268 pinctrl_usdhc1: usdhc1grp {
269 fsl,pins = <
270 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
271 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
272 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
273 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
274 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
275 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
276 >;
277 };
278
279 pinctrl_usdhc2: usdhc2grp {
280 fsl,pins = <
281 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
282 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
283 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
284 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
285 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
286 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
287 >;
288 };
289
290 pinctrl_usdhc3: usdhc3grp {
291 fsl,pins = <
292 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
293 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
294 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
295 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
296 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
297 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
298 >;
299 };
300 };
301};
302
303&fec {
304 pinctrl-names = "default";
305 pinctrl-0 = <&pinctrl_enet>;
306 phy-mode = "rgmii-id";
307 phy-handle = <&ethphy>;
308 phy-reset-gpios = <&gpio3 29 GPIO_ACTIVE_LOW>;
309 status = "okay";
310
311 mdio {
312 #address-cells = <1>;
313 #size-cells = <0>;
314
315 ethphy: ethernet-phy@1 {
316 reg = <1>;
317 qca,clk-out-frequency = <125000000>;
318 };
319 };
320};
321
322&mipi_csi {
323 status = "okay";
324
325 port@0 {
326 reg = <0>;
327
328 mipi_csi2_in: endpoint {
329 remote-endpoint = <&ov5645_to_mipi_csi2>;
330 clock-lanes = <0>;
331 data-lanes = <1 2>;
332 };
333 };
334};
335
336&spdif {
337 pinctrl-names = "default";
338 pinctrl-0 = <&pinctrl_spdif>;
339 status = "okay";
340};
341
342&ssi1 {
343 status = "okay";
344};
345
346&uart1 {
347 pinctrl-names = "default";
348 pinctrl-0 = <&pinctrl_uart1>;
349 status = "okay";
350};
351
352&uart3 {
353 pinctrl-names = "default";
354 pinctrl-0 = <&pinctrl_uart3>;
355 uart-has-rtscts;
356 status = "okay";
357};
358
359&usbh1 {
360 status = "okay";
361};
362
363&usbotg {
364 vbus-supply = <&reg_usb_otg_vbus>;
365 pinctrl-names = "default";
366 pinctrl-0 = <&pinctrl_usbotg>;
367 disable-over-current;
368 dr_mode = "otg";
369 status = "okay";
370};
371
372&usdhc1 {
373 pinctrl-names = "default";
374 pinctrl-0 = <&pinctrl_usdhc1>;
375 cd-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
376 status = "okay";
377};
378
379&usdhc3 {
380 pinctrl-names = "default";
381 pinctrl-0 = <&pinctrl_usdhc3>;
382 cd-gpios = <&gpio3 9 GPIO_ACTIVE_LOW>;
383 status = "okay";
384};