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git01.mediatek.com / filogic / uboot / 53633a893a06bd5a0c807287d9cc29337806eaf7 / . / src / arm / nxp / imx / imx6qdl-wandboard.dtsi
blob: 38abb6b50f6cbc9ed76ccddfeeb682c22a2e3b55 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame^]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright 2013 Freescale Semiconductor, Inc.
4 *
5 * Author: Fabio Estevam <fabio.estevam@freescale.com>
6 */
7
8#include <dt-bindings/gpio/gpio.h>
9
10/ {
11 chosen {
12 stdout-path = &uart1;
13 };
14
15 sound {
16 compatible = "fsl,imx6-wandboard-sgtl5000",
17 "fsl,imx-audio-sgtl5000";
18 model = "imx6-wandboard-sgtl5000";
19 ssi-controller = <&ssi1>;
20 audio-codec = <&codec>;
21 audio-routing =
22 "MIC_IN", "Mic Jack",
23 "Mic Jack", "Mic Bias",
24 "Headphone Jack", "HP_OUT";
25 mux-int-port = <1>;
26 mux-ext-port = <3>;
27 };
28
29 sound-spdif {
30 compatible = "fsl,imx-audio-spdif";
31 model = "imx-spdif";
32 spdif-controller = <&spdif>;
33 spdif-out;
34 };
35
36 reg_1p5v: regulator-1p5v {
37 compatible = "regulator-fixed";
38 regulator-name = "1P5V";
39 regulator-min-microvolt = <1500000>;
40 regulator-max-microvolt = <1500000>;
41 regulator-always-on;
42 };
43
44 reg_1p8v: regulator-1p8v {
45 compatible = "regulator-fixed";
46 regulator-name = "1P8V";
47 regulator-min-microvolt = <1800000>;
48 regulator-max-microvolt = <1800000>;
49 regulator-always-on;
50 };
51
52 reg_2p8v: regulator-2p8v {
53 compatible = "regulator-fixed";
54 regulator-name = "2P8V";
55 regulator-min-microvolt = <2800000>;
56 regulator-max-microvolt = <2800000>;
57 regulator-always-on;
58 };
59
60 reg_2p5v: regulator-2p5v {
61 compatible = "regulator-fixed";
62 regulator-name = "2P5V";
63 regulator-min-microvolt = <2500000>;
64 regulator-max-microvolt = <2500000>;
65 regulator-always-on;
66 };
67
68 reg_3p3v: regulator-3p3v {
69 compatible = "regulator-fixed";
70 regulator-name = "3P3V";
71 regulator-min-microvolt = <3300000>;
72 regulator-max-microvolt = <3300000>;
73 regulator-always-on;
74 };
75
76 reg_usb_otg_vbus: regulator-usbotgvbus {
77 compatible = "regulator-fixed";
78 regulator-name = "usb_otg_vbus";
79 regulator-min-microvolt = <5000000>;
80 regulator-max-microvolt = <5000000>;
81 pinctrl-names = "default";
82 pinctrl-0 = <&pinctrl_usbotgvbus>;
83 gpio = <&gpio3 22 GPIO_ACTIVE_LOW>;
84 };
85};
86
87&audmux {
88 pinctrl-names = "default";
89 pinctrl-0 = <&pinctrl_audmux>;
90 status = "okay";
91};
92
93&hdmi {
94 ddc-i2c-bus = <&i2c1>;
95 status = "okay";
96};
97
98&i2c1 {
99 clock-frequency = <100000>;
100 pinctrl-names = "default", "gpio";
101 pinctrl-0 = <&pinctrl_i2c1>;
102 pinctrl-1 = <&pinctrl_i2c1_gpio>;
103 scl-gpios = <&gpio3 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
104 sda-gpios = <&gpio3 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
105 status = "okay";
106};
107
108&i2c2 {
109 clock-frequency = <100000>;
110 pinctrl-names = "default", "gpio";
111 pinctrl-0 = <&pinctrl_i2c2>;
112 pinctrl-1 = <&pinctrl_i2c2_gpio>;
113 scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
114 sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
115 status = "okay";
116
117 codec: sgtl5000@a {
118 pinctrl-names = "default";
119 pinctrl-0 = <&pinctrl_mclk>;
120 compatible = "fsl,sgtl5000";
121 reg = <0x0a>;
122 #sound-dai-cells = <0>;
123 clocks = <&clks IMX6QDL_CLK_CKO>;
124 VDDA-supply = <&reg_2p5v>;
125 VDDIO-supply = <&reg_3p3v>;
126 lrclk-strength = <3>;
127 };
128
129 camera@3c {
130 compatible = "ovti,ov5645";
131 pinctrl-names = "default";
132 pinctrl-0 = <&pinctrl_ov5645>;
133 reg = <0x3c>;
134 clocks = <&clks IMX6QDL_CLK_CKO2>;
135 clock-frequency = <24000000>;
136 vdddo-supply = <&reg_1p8v>;
137 vdda-supply = <&reg_2p8v>;
138 vddd-supply = <&reg_1p5v>;
139 enable-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
140 reset-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>;
141
142 port {
143 ov5645_to_mipi_csi2: endpoint {
144 remote-endpoint = <&mipi_csi2_in>;
145 clock-lanes = <0>;
146 data-lanes = <1 2>;
147 };
148 };
149 };
150};
151
152&iomuxc {
153 pinctrl-names = "default";
154
155 imx6qdl-wandboard {
156
157 pinctrl_audmux: audmuxgrp {
158 fsl,pins = <
159 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
160 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
161 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
162 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
163 >;
164 };
165
166 pinctrl_enet: enetgrp {
167 fsl,pins = <
168 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
169 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
170 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
171 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
172 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
173 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
174 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
175 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
176 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
177 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
178 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
179 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
180 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
181 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
182 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
183 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
184 >;
185 };
186
187 pinctrl_i2c1: i2c1grp {
188 fsl,pins = <
189 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
190 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
191 >;
192 };
193
194 pinctrl_i2c1_gpio: i2c1gpiogrp {
195 fsl,pins = <
196 MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b0
197 MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b0
198 >;
199 };
200
201 pinctrl_i2c2: i2c2grp {
202 fsl,pins = <
203 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
204 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
205 >;
206 };
207
208 pinctrl_i2c2_gpio: i2c2gpiogrp {
209 fsl,pins = <
210 MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b0
211 MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b0
212 >;
213 };
214
215 pinctrl_mclk: mclkgrp {
216 fsl,pins = <
217 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
218 >;
219 };
220
221 pinctrl_ov5645: ov5645grp {
222 fsl,pins = <
223 MX6QDL_PAD_GPIO_3__CCM_CLKO2 0x000b0
224 MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0
225 MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0
226 >;
227 };
228
229 pinctrl_spdif: spdifgrp {
230 fsl,pins = <
231 MX6QDL_PAD_ENET_RXD0__SPDIF_OUT 0x1b0b0
232 >;
233 };
234
235 pinctrl_uart1: uart1grp {
236 fsl,pins = <
237 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
238 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
239 >;
240 };
241
242 pinctrl_uart3: uart3grp {
243 fsl,pins = <
244 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
245 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
246 MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1
247 MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1
248 >;
249 };
250
251 pinctrl_usbotg: usbotggrp {
252 fsl,pins = <
253 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
254 >;
255 };
256
257 pinctrl_usbotgvbus: usbotgvbusgrp {
258 fsl,pins = <
259 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x130b0
260 >;
261 };
262
263 pinctrl_usdhc1: usdhc1grp {
264 fsl,pins = <
265 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
266 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
267 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
268 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
269 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
270 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
271 >;
272 };
273
274 pinctrl_usdhc2: usdhc2grp {
275 fsl,pins = <
276 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
277 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
278 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
279 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
280 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
281 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
282 >;
283 };
284
285 pinctrl_usdhc3: usdhc3grp {
286 fsl,pins = <
287 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
288 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
289 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
290 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
291 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
292 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
293 >;
294 };
295 };
296};
297
298&fec {
299 pinctrl-names = "default";
300 pinctrl-0 = <&pinctrl_enet>;
301 phy-mode = "rgmii-id";
302 phy-handle = <&ethphy>;
303 phy-reset-gpios = <&gpio3 29 GPIO_ACTIVE_LOW>;
304 status = "okay";
305
306 mdio {
307 #address-cells = <1>;
308 #size-cells = <0>;
309
310 ethphy: ethernet-phy@1 {
311 reg = <1>;
312 qca,clk-out-frequency = <125000000>;
313 };
314 };
315};
316
317&mipi_csi {
318 status = "okay";
319
320 port@0 {
321 reg = <0>;
322
323 mipi_csi2_in: endpoint {
324 remote-endpoint = <&ov5645_to_mipi_csi2>;
325 clock-lanes = <0>;
326 data-lanes = <1 2>;
327 };
328 };
329};
330
331&spdif {
332 pinctrl-names = "default";
333 pinctrl-0 = <&pinctrl_spdif>;
334 status = "okay";
335};
336
337&ssi1 {
338 status = "okay";
339};
340
341&uart1 {
342 pinctrl-names = "default";
343 pinctrl-0 = <&pinctrl_uart1>;
344 status = "okay";
345};
346
347&uart3 {
348 pinctrl-names = "default";
349 pinctrl-0 = <&pinctrl_uart3>;
350 uart-has-rtscts;
351 status = "okay";
352};
353
354&usbh1 {
355 status = "okay";
356};
357
358&usbotg {
359 vbus-supply = <&reg_usb_otg_vbus>;
360 pinctrl-names = "default";
361 pinctrl-0 = <&pinctrl_usbotg>;
362 disable-over-current;
363 dr_mode = "otg";
364 status = "okay";
365};
366
367&usdhc1 {
368 pinctrl-names = "default";
369 pinctrl-0 = <&pinctrl_usdhc1>;
370 cd-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
371 status = "okay";
372};
373
374&usdhc3 {
375 pinctrl-names = "default";
376 pinctrl-0 = <&pinctrl_usdhc3>;
377 cd-gpios = <&gpio3 9 GPIO_ACTIVE_LOW>;
378 status = "okay";
379};