Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Albert Aribaud | acc41ff | 2010-06-17 19:38:21 +0530 | [diff] [blame] | 2 | /* |
Albert ARIBAUD | 340983d | 2011-04-22 19:41:02 +0200 | [diff] [blame] | 3 | * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net> |
Albert Aribaud | acc41ff | 2010-06-17 19:38:21 +0530 | [diff] [blame] | 4 | * |
| 5 | * Based on original Kirkwood support which is |
| 6 | * (C) Copyright 2009 |
| 7 | * Marvell Semiconductor <www.marvell.com> |
| 8 | * Written-by: Prafulla Wadaskar <prafulla@marvell.com> |
Albert Aribaud | acc41ff | 2010-06-17 19:38:21 +0530 | [diff] [blame] | 9 | */ |
| 10 | |
| 11 | #ifndef _CONFIG_EDMINIV2_H |
| 12 | #define _CONFIG_EDMINIV2_H |
| 13 | |
| 14 | /* |
Albert ARIBAUD | 2ac3792 | 2015-01-31 22:55:38 +0100 | [diff] [blame] | 15 | * SPL |
| 16 | */ |
| 17 | |
Albert ARIBAUD | 2ac3792 | 2015-01-31 22:55:38 +0100 | [diff] [blame] | 18 | #define CONFIG_SPL_MAX_SIZE 0x0000fff0 |
| 19 | #define CONFIG_SPL_STACK 0x00020000 |
| 20 | #define CONFIG_SPL_BSS_START_ADDR 0x00020000 |
| 21 | #define CONFIG_SPL_BSS_MAX_SIZE 0x0001ffff |
| 22 | #define CONFIG_SYS_SPL_MALLOC_START 0x00040000 |
| 23 | #define CONFIG_SYS_SPL_MALLOC_SIZE 0x0001ffff |
Albert ARIBAUD | 2ac3792 | 2015-01-31 22:55:38 +0100 | [diff] [blame] | 24 | #define CONFIG_SYS_UBOOT_BASE 0xfff90000 |
| 25 | #define CONFIG_SYS_UBOOT_START 0x00800000 |
Albert ARIBAUD | 2ac3792 | 2015-01-31 22:55:38 +0100 | [diff] [blame] | 26 | |
| 27 | /* |
Albert Aribaud | acc41ff | 2010-06-17 19:38:21 +0530 | [diff] [blame] | 28 | * High Level Configuration Options (easy to change) |
| 29 | */ |
| 30 | |
Albert Aribaud | acc41ff | 2010-06-17 19:38:21 +0530 | [diff] [blame] | 31 | #define CONFIG_FEROCEON 1 /* CPU Core subversion */ |
Albert Aribaud | acc41ff | 2010-06-17 19:38:21 +0530 | [diff] [blame] | 32 | #define CONFIG_88F5182 1 /* SOC Name */ |
Albert Aribaud | acc41ff | 2010-06-17 19:38:21 +0530 | [diff] [blame] | 33 | |
Lei Wen | 749941a | 2011-10-24 16:27:32 +0000 | [diff] [blame] | 34 | #include <asm/arch/orion5x.h> |
Albert Aribaud | acc41ff | 2010-06-17 19:38:21 +0530 | [diff] [blame] | 35 | /* |
| 36 | * CLKs configurations |
| 37 | */ |
| 38 | |
Albert Aribaud | acc41ff | 2010-06-17 19:38:21 +0530 | [diff] [blame] | 39 | /* |
| 40 | * Board-specific values for Orion5x MPP low level init: |
| 41 | * - MPPs 12 to 15 are SATA LEDs (mode 5) |
| 42 | * - Others are GPIO/unused (mode 3 for MPP0, mode 5 for |
| 43 | * MPP16 to MPP19, mode 0 for others |
| 44 | */ |
| 45 | |
| 46 | #define ORION5X_MPP0_7 0x00000003 |
| 47 | #define ORION5X_MPP8_15 0x55550000 |
Albert Aribaud | 26137d0 | 2010-08-08 05:17:06 +0530 | [diff] [blame] | 48 | #define ORION5X_MPP16_23 0x00005555 |
Albert Aribaud | acc41ff | 2010-06-17 19:38:21 +0530 | [diff] [blame] | 49 | |
| 50 | /* |
| 51 | * Board-specific values for Orion5x GPIO low level init: |
| 52 | * - GPIO3 is input (RTC interrupt) |
| 53 | * - GPIO16 is Power LED control (0 = on, 1 = off) |
| 54 | * - GPIO17 is Power LED source select (0 = CPLD, 1 = GPIO16) |
| 55 | * - GPIO18 is Power Button status (0 = Released, 1 = Pressed) |
Albert ARIBAUD | dea1cfb | 2012-08-16 06:35:21 +0000 | [diff] [blame] | 56 | * - GPIO19 is SATA disk power toggle (toggles on 0-to-1) |
| 57 | * - GPIO22 is SATA disk power status () |
| 58 | * - GPIO23 is supply status for SATA disk () |
| 59 | * - GPIO24 is supply control for board (write 1 to power off) |
| 60 | * Last GPIO is 25, further bits are supposed to be 0. |
Albert Aribaud | acc41ff | 2010-06-17 19:38:21 +0530 | [diff] [blame] | 61 | * Enable mask has ones for INPUT, 0 for OUTPUT. |
Albert ARIBAUD | dea1cfb | 2012-08-16 06:35:21 +0000 | [diff] [blame] | 62 | * Default is LED ON, board ON :) |
Albert Aribaud | acc41ff | 2010-06-17 19:38:21 +0530 | [diff] [blame] | 63 | */ |
| 64 | |
Albert ARIBAUD | dea1cfb | 2012-08-16 06:35:21 +0000 | [diff] [blame] | 65 | #define ORION5X_GPIO_OUT_ENABLE 0xfef4f0ca |
| 66 | #define ORION5X_GPIO_OUT_VALUE 0x00000000 |
| 67 | #define ORION5X_GPIO_IN_POLARITY 0x000000d0 |
Albert Aribaud | acc41ff | 2010-06-17 19:38:21 +0530 | [diff] [blame] | 68 | |
| 69 | /* |
| 70 | * NS16550 Configuration |
| 71 | */ |
| 72 | |
Albert Aribaud | acc41ff | 2010-06-17 19:38:21 +0530 | [diff] [blame] | 73 | #define CONFIG_SYS_NS16550_SERIAL |
| 74 | #define CONFIG_SYS_NS16550_REG_SIZE (-4) |
| 75 | #define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK |
| 76 | #define CONFIG_SYS_NS16550_COM1 ORION5X_UART0_BASE |
| 77 | |
| 78 | /* |
| 79 | * Serial Port configuration |
| 80 | * The following definitions let you select what serial you want to use |
| 81 | * for your console driver. |
| 82 | */ |
| 83 | |
Albert Aribaud | acc41ff | 2010-06-17 19:38:21 +0530 | [diff] [blame] | 84 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
| 85 | { 9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600 } |
| 86 | |
| 87 | /* |
| 88 | * FLASH configuration |
| 89 | */ |
| 90 | |
Albert Aribaud | acc41ff | 2010-06-17 19:38:21 +0530 | [diff] [blame] | 91 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ |
| 92 | #define CONFIG_SYS_MAX_FLASH_SECT 11 /* max num of sects on one chip */ |
| 93 | #define CONFIG_SYS_FLASH_BASE 0xfff80000 |
Albert Aribaud | acc41ff | 2010-06-17 19:38:21 +0530 | [diff] [blame] | 94 | |
| 95 | /* auto boot */ |
Albert Aribaud | acc41ff | 2010-06-17 19:38:21 +0530 | [diff] [blame] | 96 | |
| 97 | /* |
| 98 | * For booting Linux, the board info and command line data |
| 99 | * have to be in the first 8 MB of memory, since this is |
| 100 | * the maximum mapped by the Linux kernel during initialization. |
| 101 | */ |
| 102 | #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ |
| 103 | #define CONFIG_INITRD_TAG 1 /* enable INITRD tag */ |
| 104 | #define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */ |
| 105 | |
Albert Aribaud | acc41ff | 2010-06-17 19:38:21 +0530 | [diff] [blame] | 106 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */ |
Albert Aribaud | c5b205b | 2010-07-12 22:24:30 +0200 | [diff] [blame] | 107 | |
Albert Aribaud | acc41ff | 2010-06-17 19:38:21 +0530 | [diff] [blame] | 108 | /* |
Albert Aribaud | c5b205b | 2010-07-12 22:24:30 +0200 | [diff] [blame] | 109 | * Network |
Albert Aribaud | acc41ff | 2010-06-17 19:38:21 +0530 | [diff] [blame] | 110 | */ |
Albert Aribaud | c5b205b | 2010-07-12 22:24:30 +0200 | [diff] [blame] | 111 | |
| 112 | #ifdef CONFIG_CMD_NET |
Albert Aribaud | c5b205b | 2010-07-12 22:24:30 +0200 | [diff] [blame] | 113 | #define CONFIG_MVGBE_PORTS {1} /* enable port 0 only */ |
| 114 | #define CONFIG_SKIP_LOCAL_MAC_RANDOMIZATION /* don't randomize MAC */ |
| 115 | #define CONFIG_PHY_BASE_ADR 0x8 |
| 116 | #define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */ |
Albert Aribaud | c5b205b | 2010-07-12 22:24:30 +0200 | [diff] [blame] | 117 | #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */ |
Albert Aribaud | c5b205b | 2010-07-12 22:24:30 +0200 | [diff] [blame] | 118 | #endif |
Albert Aribaud | acc41ff | 2010-06-17 19:38:21 +0530 | [diff] [blame] | 119 | |
| 120 | /* |
Albert Aribaud | 26137d0 | 2010-08-08 05:17:06 +0530 | [diff] [blame] | 121 | * IDE |
| 122 | */ |
Simon Glass | b569a01 | 2017-05-17 03:25:30 -0600 | [diff] [blame] | 123 | #ifdef CONFIG_IDE |
Albert Aribaud | 26137d0 | 2010-08-08 05:17:06 +0530 | [diff] [blame] | 124 | #define __io |
| 125 | #define CONFIG_IDE_PREINIT |
Albert Aribaud | 26137d0 | 2010-08-08 05:17:06 +0530 | [diff] [blame] | 126 | /* ED Mini V has an IDE-compatible SATA connector for port 1 */ |
Albert Aribaud | 26137d0 | 2010-08-08 05:17:06 +0530 | [diff] [blame] | 127 | #define CONFIG_MVSATA_IDE_USE_PORT1 |
| 128 | /* Needs byte-swapping for ATA data register */ |
| 129 | #define CONFIG_IDE_SWAP_IO |
| 130 | /* Data, registers and alternate blocks are at the same offset */ |
| 131 | #define CONFIG_SYS_ATA_DATA_OFFSET (0x0100) |
| 132 | #define CONFIG_SYS_ATA_REG_OFFSET (0x0100) |
| 133 | #define CONFIG_SYS_ATA_ALT_OFFSET (0x0100) |
| 134 | /* Each 8-bit ATA register is aligned to a 4-bytes address */ |
| 135 | #define CONFIG_SYS_ATA_STRIDE 4 |
| 136 | /* Controller supports 48-bits LBA addressing */ |
| 137 | #define CONFIG_LBA48 |
| 138 | /* A single bus, a single device */ |
| 139 | #define CONFIG_SYS_IDE_MAXBUS 1 |
| 140 | #define CONFIG_SYS_IDE_MAXDEVICE 1 |
| 141 | /* ATA registers base is at SATA controller base */ |
| 142 | #define CONFIG_SYS_ATA_BASE_ADDR ORION5X_SATA_BASE |
| 143 | /* ATA bus 0 is orion5x port 1 on ED Mini V2 */ |
| 144 | #define CONFIG_SYS_ATA_IDE0_OFFSET ORION5X_SATA_PORT1_OFFSET |
| 145 | /* end of IDE defines */ |
| 146 | #endif /* CMD_IDE */ |
| 147 | |
| 148 | /* |
Albert ARIBAUD | 90bdece | 2012-01-15 22:08:41 +0000 | [diff] [blame] | 149 | * Common USB/EHCI configuration |
| 150 | */ |
| 151 | #ifdef CONFIG_CMD_USB |
Albert ARIBAUD | 90bdece | 2012-01-15 22:08:41 +0000 | [diff] [blame] | 152 | #define ORION5X_USB20_HOST_PORT_BASE ORION5X_USB20_PORT0_BASE |
Albert ARIBAUD | 90bdece | 2012-01-15 22:08:41 +0000 | [diff] [blame] | 153 | #endif /* CONFIG_CMD_USB */ |
| 154 | |
| 155 | /* |
Albert Aribaud | 81c9981 | 2010-08-27 18:26:06 +0200 | [diff] [blame] | 156 | * I2C related stuff |
| 157 | */ |
| 158 | #ifdef CONFIG_CMD_I2C |
Hans de Goede | 9830f1c | 2014-06-13 22:55:48 +0200 | [diff] [blame] | 159 | #define CONFIG_SYS_I2C |
| 160 | #define CONFIG_SYS_I2C_MVTWSI |
Paul Kocialkowski | 2fae3e7 | 2015-04-10 23:09:51 +0200 | [diff] [blame] | 161 | #define CONFIG_I2C_MVTWSI_BASE0 ORION5X_TWSI_BASE |
Albert Aribaud | 81c9981 | 2010-08-27 18:26:06 +0200 | [diff] [blame] | 162 | #define CONFIG_SYS_I2C_SLAVE 0x0 |
| 163 | #define CONFIG_SYS_I2C_SPEED 100000 |
| 164 | #endif |
| 165 | |
| 166 | /* |
Albert Aribaud | acc41ff | 2010-06-17 19:38:21 +0530 | [diff] [blame] | 167 | * Environment variables configurations |
| 168 | */ |
Albert Aribaud | acc41ff | 2010-06-17 19:38:21 +0530 | [diff] [blame] | 169 | |
| 170 | /* |
| 171 | * Size of malloc() pool |
| 172 | */ |
Albert ARIBAUD | a1ec610 | 2012-09-21 14:57:12 +0000 | [diff] [blame] | 173 | #define CONFIG_SYS_MALLOC_LEN (1024 * 256) /* 256kB for malloc() */ |
Albert Aribaud | acc41ff | 2010-06-17 19:38:21 +0530 | [diff] [blame] | 174 | |
| 175 | /* |
| 176 | * Other required minimal configurations |
| 177 | */ |
Albert Aribaud | acc41ff | 2010-06-17 19:38:21 +0530 | [diff] [blame] | 178 | |
Albert Aribaud | acc41ff | 2010-06-17 19:38:21 +0530 | [diff] [blame] | 179 | #define CONFIG_SYS_LOAD_ADDR 0x00800000 |
Albert Aribaud | acc41ff | 2010-06-17 19:38:21 +0530 | [diff] [blame] | 180 | #define CONFIG_SYS_RESET_ADDRESS 0xffff0000 |
Albert Aribaud | acc41ff | 2010-06-17 19:38:21 +0530 | [diff] [blame] | 181 | |
Albert ARIBAUD | c4d48a6 | 2012-02-06 20:32:19 +0530 | [diff] [blame] | 182 | /* Enable command line editing */ |
Albert ARIBAUD | c4d48a6 | 2012-02-06 20:32:19 +0530 | [diff] [blame] | 183 | |
| 184 | /* provide extensive help */ |
Albert ARIBAUD | c4d48a6 | 2012-02-06 20:32:19 +0530 | [diff] [blame] | 185 | |
Albert Aribaud | a2ddee4 | 2010-10-11 13:13:29 +0200 | [diff] [blame] | 186 | /* additions for new relocation code, must be added to all boards */ |
| 187 | #define CONFIG_SYS_SDRAM_BASE 0 |
| 188 | #define CONFIG_SYS_INIT_SP_ADDR \ |
Wolfgang Denk | 0191e47 | 2010-10-26 14:34:52 +0200 | [diff] [blame] | 189 | (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) |
Albert Aribaud | a2ddee4 | 2010-10-11 13:13:29 +0200 | [diff] [blame] | 190 | |
Albert Aribaud | acc41ff | 2010-06-17 19:38:21 +0530 | [diff] [blame] | 191 | #endif /* _CONFIG_EDMINIV2_H */ |