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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Albert Aribaudacc41ff2010-06-17 19:38:21 +05302/*
Albert ARIBAUD340983d2011-04-22 19:41:02 +02003 * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
Albert Aribaudacc41ff2010-06-17 19:38:21 +05304 *
5 * Based on original Kirkwood support which is
6 * (C) Copyright 2009
7 * Marvell Semiconductor <www.marvell.com>
8 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
Albert Aribaudacc41ff2010-06-17 19:38:21 +05309 */
10
11#ifndef _CONFIG_EDMINIV2_H
12#define _CONFIG_EDMINIV2_H
13
14/*
Albert ARIBAUD2ac37922015-01-31 22:55:38 +010015 * SPL
16 */
17
Albert ARIBAUD2ac37922015-01-31 22:55:38 +010018#define CONFIG_SPL_MAX_SIZE 0x0000fff0
19#define CONFIG_SPL_STACK 0x00020000
20#define CONFIG_SPL_BSS_START_ADDR 0x00020000
21#define CONFIG_SPL_BSS_MAX_SIZE 0x0001ffff
22#define CONFIG_SYS_SPL_MALLOC_START 0x00040000
23#define CONFIG_SYS_SPL_MALLOC_SIZE 0x0001ffff
Albert ARIBAUD2ac37922015-01-31 22:55:38 +010024#define CONFIG_SYS_UBOOT_BASE 0xfff90000
25#define CONFIG_SYS_UBOOT_START 0x00800000
Albert ARIBAUD2ac37922015-01-31 22:55:38 +010026
27/*
Albert Aribaudacc41ff2010-06-17 19:38:21 +053028 * High Level Configuration Options (easy to change)
29 */
30
Albert Aribaudacc41ff2010-06-17 19:38:21 +053031#define CONFIG_FEROCEON 1 /* CPU Core subversion */
Albert Aribaudacc41ff2010-06-17 19:38:21 +053032#define CONFIG_88F5182 1 /* SOC Name */
Albert Aribaudacc41ff2010-06-17 19:38:21 +053033
Lei Wen749941a2011-10-24 16:27:32 +000034#include <asm/arch/orion5x.h>
Albert Aribaudacc41ff2010-06-17 19:38:21 +053035/*
36 * CLKs configurations
37 */
38
Albert Aribaudacc41ff2010-06-17 19:38:21 +053039/*
40 * Board-specific values for Orion5x MPP low level init:
41 * - MPPs 12 to 15 are SATA LEDs (mode 5)
42 * - Others are GPIO/unused (mode 3 for MPP0, mode 5 for
43 * MPP16 to MPP19, mode 0 for others
44 */
45
46#define ORION5X_MPP0_7 0x00000003
47#define ORION5X_MPP8_15 0x55550000
Albert Aribaud26137d02010-08-08 05:17:06 +053048#define ORION5X_MPP16_23 0x00005555
Albert Aribaudacc41ff2010-06-17 19:38:21 +053049
50/*
51 * Board-specific values for Orion5x GPIO low level init:
52 * - GPIO3 is input (RTC interrupt)
53 * - GPIO16 is Power LED control (0 = on, 1 = off)
54 * - GPIO17 is Power LED source select (0 = CPLD, 1 = GPIO16)
55 * - GPIO18 is Power Button status (0 = Released, 1 = Pressed)
Albert ARIBAUDdea1cfb2012-08-16 06:35:21 +000056 * - GPIO19 is SATA disk power toggle (toggles on 0-to-1)
57 * - GPIO22 is SATA disk power status ()
58 * - GPIO23 is supply status for SATA disk ()
59 * - GPIO24 is supply control for board (write 1 to power off)
60 * Last GPIO is 25, further bits are supposed to be 0.
Albert Aribaudacc41ff2010-06-17 19:38:21 +053061 * Enable mask has ones for INPUT, 0 for OUTPUT.
Albert ARIBAUDdea1cfb2012-08-16 06:35:21 +000062 * Default is LED ON, board ON :)
Albert Aribaudacc41ff2010-06-17 19:38:21 +053063 */
64
Albert ARIBAUDdea1cfb2012-08-16 06:35:21 +000065#define ORION5X_GPIO_OUT_ENABLE 0xfef4f0ca
66#define ORION5X_GPIO_OUT_VALUE 0x00000000
67#define ORION5X_GPIO_IN_POLARITY 0x000000d0
Albert Aribaudacc41ff2010-06-17 19:38:21 +053068
69/*
70 * NS16550 Configuration
71 */
72
Albert Aribaudacc41ff2010-06-17 19:38:21 +053073#define CONFIG_SYS_NS16550_SERIAL
74#define CONFIG_SYS_NS16550_REG_SIZE (-4)
75#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK
76#define CONFIG_SYS_NS16550_COM1 ORION5X_UART0_BASE
77
78/*
79 * Serial Port configuration
80 * The following definitions let you select what serial you want to use
81 * for your console driver.
82 */
83
Albert Aribaudacc41ff2010-06-17 19:38:21 +053084#define CONFIG_SYS_BAUDRATE_TABLE \
85 { 9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600 }
86
87/*
88 * FLASH configuration
89 */
90
Albert Aribaudacc41ff2010-06-17 19:38:21 +053091#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
92#define CONFIG_SYS_MAX_FLASH_SECT 11 /* max num of sects on one chip */
93#define CONFIG_SYS_FLASH_BASE 0xfff80000
Albert Aribaudacc41ff2010-06-17 19:38:21 +053094
95/* auto boot */
Albert Aribaudacc41ff2010-06-17 19:38:21 +053096
97/*
98 * For booting Linux, the board info and command line data
99 * have to be in the first 8 MB of memory, since this is
100 * the maximum mapped by the Linux kernel during initialization.
101 */
102#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
103#define CONFIG_INITRD_TAG 1 /* enable INITRD tag */
104#define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */
105
Albert Aribaudacc41ff2010-06-17 19:38:21 +0530106#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */
Albert Aribaudc5b205b2010-07-12 22:24:30 +0200107
Albert Aribaudacc41ff2010-06-17 19:38:21 +0530108/*
Albert Aribaudc5b205b2010-07-12 22:24:30 +0200109 * Network
Albert Aribaudacc41ff2010-06-17 19:38:21 +0530110 */
Albert Aribaudc5b205b2010-07-12 22:24:30 +0200111
112#ifdef CONFIG_CMD_NET
Albert Aribaudc5b205b2010-07-12 22:24:30 +0200113#define CONFIG_MVGBE_PORTS {1} /* enable port 0 only */
114#define CONFIG_SKIP_LOCAL_MAC_RANDOMIZATION /* don't randomize MAC */
115#define CONFIG_PHY_BASE_ADR 0x8
116#define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */
Albert Aribaudc5b205b2010-07-12 22:24:30 +0200117#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */
Albert Aribaudc5b205b2010-07-12 22:24:30 +0200118#endif
Albert Aribaudacc41ff2010-06-17 19:38:21 +0530119
120/*
Albert Aribaud26137d02010-08-08 05:17:06 +0530121 * IDE
122 */
Simon Glassb569a012017-05-17 03:25:30 -0600123#ifdef CONFIG_IDE
Albert Aribaud26137d02010-08-08 05:17:06 +0530124#define __io
125#define CONFIG_IDE_PREINIT
Albert Aribaud26137d02010-08-08 05:17:06 +0530126/* ED Mini V has an IDE-compatible SATA connector for port 1 */
Albert Aribaud26137d02010-08-08 05:17:06 +0530127#define CONFIG_MVSATA_IDE_USE_PORT1
128/* Needs byte-swapping for ATA data register */
129#define CONFIG_IDE_SWAP_IO
130/* Data, registers and alternate blocks are at the same offset */
131#define CONFIG_SYS_ATA_DATA_OFFSET (0x0100)
132#define CONFIG_SYS_ATA_REG_OFFSET (0x0100)
133#define CONFIG_SYS_ATA_ALT_OFFSET (0x0100)
134/* Each 8-bit ATA register is aligned to a 4-bytes address */
135#define CONFIG_SYS_ATA_STRIDE 4
136/* Controller supports 48-bits LBA addressing */
137#define CONFIG_LBA48
138/* A single bus, a single device */
139#define CONFIG_SYS_IDE_MAXBUS 1
140#define CONFIG_SYS_IDE_MAXDEVICE 1
141/* ATA registers base is at SATA controller base */
142#define CONFIG_SYS_ATA_BASE_ADDR ORION5X_SATA_BASE
143/* ATA bus 0 is orion5x port 1 on ED Mini V2 */
144#define CONFIG_SYS_ATA_IDE0_OFFSET ORION5X_SATA_PORT1_OFFSET
145/* end of IDE defines */
146#endif /* CMD_IDE */
147
148/*
Albert ARIBAUD90bdece2012-01-15 22:08:41 +0000149 * Common USB/EHCI configuration
150 */
151#ifdef CONFIG_CMD_USB
Albert ARIBAUD90bdece2012-01-15 22:08:41 +0000152#define ORION5X_USB20_HOST_PORT_BASE ORION5X_USB20_PORT0_BASE
Albert ARIBAUD90bdece2012-01-15 22:08:41 +0000153#endif /* CONFIG_CMD_USB */
154
155/*
Albert Aribaud81c99812010-08-27 18:26:06 +0200156 * I2C related stuff
157 */
158#ifdef CONFIG_CMD_I2C
Hans de Goede9830f1c2014-06-13 22:55:48 +0200159#define CONFIG_SYS_I2C
160#define CONFIG_SYS_I2C_MVTWSI
Paul Kocialkowski2fae3e72015-04-10 23:09:51 +0200161#define CONFIG_I2C_MVTWSI_BASE0 ORION5X_TWSI_BASE
Albert Aribaud81c99812010-08-27 18:26:06 +0200162#define CONFIG_SYS_I2C_SLAVE 0x0
163#define CONFIG_SYS_I2C_SPEED 100000
164#endif
165
166/*
Albert Aribaudacc41ff2010-06-17 19:38:21 +0530167 * Environment variables configurations
168 */
Albert Aribaudacc41ff2010-06-17 19:38:21 +0530169
170/*
171 * Size of malloc() pool
172 */
Albert ARIBAUDa1ec6102012-09-21 14:57:12 +0000173#define CONFIG_SYS_MALLOC_LEN (1024 * 256) /* 256kB for malloc() */
Albert Aribaudacc41ff2010-06-17 19:38:21 +0530174
175/*
176 * Other required minimal configurations
177 */
Albert Aribaudacc41ff2010-06-17 19:38:21 +0530178
Albert Aribaudacc41ff2010-06-17 19:38:21 +0530179#define CONFIG_SYS_LOAD_ADDR 0x00800000
Albert Aribaudacc41ff2010-06-17 19:38:21 +0530180#define CONFIG_SYS_RESET_ADDRESS 0xffff0000
Albert Aribaudacc41ff2010-06-17 19:38:21 +0530181
Albert ARIBAUDc4d48a62012-02-06 20:32:19 +0530182/* Enable command line editing */
Albert ARIBAUDc4d48a62012-02-06 20:32:19 +0530183
184/* provide extensive help */
Albert ARIBAUDc4d48a62012-02-06 20:32:19 +0530185
Albert Aribauda2ddee42010-10-11 13:13:29 +0200186/* additions for new relocation code, must be added to all boards */
187#define CONFIG_SYS_SDRAM_BASE 0
188#define CONFIG_SYS_INIT_SP_ADDR \
Wolfgang Denk0191e472010-10-26 14:34:52 +0200189 (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
Albert Aribauda2ddee42010-10-11 13:13:29 +0200190
Albert Aribaudacc41ff2010-06-17 19:38:21 +0530191#endif /* _CONFIG_EDMINIV2_H */