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git01.mediatek.com / filogic / uboot / 9b8fc6cfc877ab811b65c7545b79beff967dc8a1 / . / arch / arm / dts / imx8mn-evk.dtsi
blob: fd253f0042e52ff558a74462f48ebff6d7278839 [file] [log] [blame]
Peng Fancdc90f32020-12-27 09:37:06 +0800[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2019 NXP
4 */
5
6#include <dt-bindings/usb/pd.h>
7#include "imx8mn.dtsi"
8
9/ {
10 chosen {
11 stdout-path = &uart2;
12 };
13
14 gpio-leds {
15 compatible = "gpio-leds";
16 pinctrl-names = "default";
17 pinctrl-0 = <&pinctrl_gpio_led>;
18
19 status {
20 label = "yellow:status";
21 gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
22 default-state = "on";
23 };
24 };
25
26 memory@40000000 {
27 device_type = "memory";
28 reg = <0x0 0x40000000 0 0x80000000>;
29 };
30
31 reg_usdhc2_vmmc: regulator-usdhc2 {
32 compatible = "regulator-fixed";
33 pinctrl-names = "default";
34 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
35 regulator-name = "VSD_3V3";
36 regulator-min-microvolt = <3300000>;
37 regulator-max-microvolt = <3300000>;
38 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
39 enable-active-high;
40 };
41
42 ir-receiver {
43 compatible = "gpio-ir-receiver";
44 gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
45 pinctrl-names = "default";
46 pinctrl-0 = <&pinctrl_ir>;
47 linux,autosuspend-period = <125>;
48 };
49};
50
51&fec1 {
52 pinctrl-names = "default";
53 pinctrl-0 = <&pinctrl_fec1>;
54 phy-mode = "rgmii-id";
55 phy-handle = <&ethphy0>;
Peng Fancdc90f32020-12-27 09:37:06 +0800[diff] [blame]56 fsl,magic-packet;
57 status = "okay";
58
59 mdio {
60 #address-cells = <1>;
61 #size-cells = <0>;
62
63 ethphy0: ethernet-phy@0 {
64 compatible = "ethernet-phy-ieee802.3-c22";
65 reg = <0>;
Heiko Thieryab74a3e2022-02-23 10:48:26 +0100[diff] [blame]66 reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
67 reset-assert-us = <10000>;
Heiko Thiery3659be02022-02-23 10:48:28 +0100[diff] [blame]68 qca,disable-smarteee;
Heiko Thiery26eaca62022-02-23 09:10:29 +0100[diff] [blame]69 vddio-supply = <&vddio>;
70
71 vddio: vddio-regulator {
72 regulator-min-microvolt = <1800000>;
73 regulator-max-microvolt = <1800000>;
74 };
Peng Fancdc90f32020-12-27 09:37:06 +0800[diff] [blame]75 };
76 };
77};
78
79&i2c1 {
80 clock-frequency = <400000>;
81 pinctrl-names = "default";
82 pinctrl-0 = <&pinctrl_i2c1>;
83 status = "okay";
84};
85
86&i2c2 {
87 clock-frequency = <400000>;
88 pinctrl-names = "default";
89 pinctrl-0 = <&pinctrl_i2c2>;
90 status = "okay";
91
92 ptn5110: tcpc@50 {
93 compatible = "nxp,ptn5110";
94 pinctrl-names = "default";
95 pinctrl-0 = <&pinctrl_typec1>;
96 reg = <0x50>;
97 interrupt-parent = <&gpio2>;
98 interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
99 status = "okay";
100
101 port {
102 typec1_dr_sw: endpoint {
103 remote-endpoint = <&usb1_drd_sw>;
104 };
105 };
106
107 typec1_con: connector {
108 compatible = "usb-c-connector";
109 label = "USB-C";
110 power-role = "dual";
111 data-role = "dual";
112 try-power-role = "sink";
113 source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
114 sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
115 PDO_VAR(5000, 20000, 3000)>;
116 op-sink-microwatt = <15000000>;
117 self-powered;
118 };
119 };
120};
121
122&i2c3 {
123 clock-frequency = <400000>;
124 pinctrl-names = "default";
125 pinctrl-0 = <&pinctrl_i2c3>;
126 status = "okay";
127
128 pca6416: gpio@20 {
129 compatible = "ti,tca6416";
130 reg = <0x20>;
131 gpio-controller;
132 #gpio-cells = <2>;
133 };
134};
135
136&snvs_pwrkey {
137 status = "okay";
138};
139
140&uart2 { /* console */
141 pinctrl-names = "default";
142 pinctrl-0 = <&pinctrl_uart2>;
143 status = "okay";
144};
145
146&usbotg1 {
147 dr_mode = "otg";
148 hnp-disable;
149 srp-disable;
150 adp-disable;
151 usb-role-switch;
152 samsung,picophy-pre-emp-curr-control = <3>;
153 samsung,picophy-dc-vol-level-adjust = <7>;
154 status = "okay";
155
156 port {
157 usb1_drd_sw: endpoint {
158 remote-endpoint = <&typec1_dr_sw>;
159 };
160 };
161};
162
163&usdhc2 {
164 assigned-clocks = <&clk IMX8MN_CLK_USDHC2>;
165 assigned-clock-rates = <200000000>;
166 pinctrl-names = "default", "state_100mhz", "state_200mhz";
167 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
168 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
169 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
170 cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
171 bus-width = <4>;
172 vmmc-supply = <&reg_usdhc2_vmmc>;
173 status = "okay";
174};
175
176&usdhc3 {
177 assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>;
178 assigned-clock-rates = <400000000>;
179 pinctrl-names = "default", "state_100mhz", "state_200mhz";
180 pinctrl-0 = <&pinctrl_usdhc3>;
181 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
182 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
183 bus-width = <8>;
184 non-removable;
185 status = "okay";
186};
187
188&wdog1 {
189 pinctrl-names = "default";
190 pinctrl-0 = <&pinctrl_wdog>;
191 fsl,ext-reset-output;
192 status = "okay";
193};
194
195&iomuxc {
196 pinctrl_fec1: fec1grp {
197 fsl,pins = <
198 MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3
199 MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
200 MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
201 MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
202 MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
203 MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
204 MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
205 MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
206 MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
207 MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
208 MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
209 MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
210 MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
211 MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
212 MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19
213 >;
214 };
215
216 pinctrl_gpio_led: gpioledgrp {
217 fsl,pins = <
218 MX8MN_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19
219 >;
220 };
221
222 pinctrl_ir: irgrp {
223 fsl,pins = <
224 MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x4f
225 >;
226 };
227
228 pinctrl_i2c1: i2c1grp {
229 fsl,pins = <
230 MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
231 MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
232 >;
233 };
234
235 pinctrl_i2c2: i2c2grp {
236 fsl,pins = <
237 MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
238 MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
239 >;
240 };
241
242 pinctrl_i2c3: i2c3grp {
243 fsl,pins = <
244 MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
245 MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
246 >;
247 };
248
249 pinctrl_pmic: pmicirqgrp {
250 fsl,pins = <
251 MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141
252 >;
253 };
254
255 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
256 fsl,pins = <
257 MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
258 >;
259 };
260
261 pinctrl_typec1: typec1grp {
262 fsl,pins = <
263 MX8MN_IOMUXC_SD1_STROBE_GPIO2_IO11 0x159
264 >;
265 };
266
267 pinctrl_uart2: uart2grp {
268 fsl,pins = <
269 MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
270 MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
271 >;
272 };
273
274 pinctrl_usdhc2_gpio: usdhc2gpiogrp {
275 fsl,pins = <
276 MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4
277 >;
278 };
279
280 pinctrl_usdhc2: usdhc2grp {
281 fsl,pins = <
282 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
283 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
284 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
285 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
286 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
287 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
288 MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
289 >;
290 };
291
292 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
293 fsl,pins = <
294 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
295 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
296 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
297 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
298 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
299 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
300 MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
301 >;
302 };
303
304 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
305 fsl,pins = <
306 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
307 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
308 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
309 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
310 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
311 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
312 MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
313 >;
314 };
315
316 pinctrl_usdhc3: usdhc3grp {
317 fsl,pins = <
318 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000190
319 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
320 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
321 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
322 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
323 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
324 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
325 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
326 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
327 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
328 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
329 >;
330 };
331
332 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
333 fsl,pins = <
334 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000194
335 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
336 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
337 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
338 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
339 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
340 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
341 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
342 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
343 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
344 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
345 >;
346 };
347
348 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
349 fsl,pins = <
350 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000196
351 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
352 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
353 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
354 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
355 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
356 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
357 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
358 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
359 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
360 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
361 >;
362 };
363
364 pinctrl_wdog: wdoggrp {
365 fsl,pins = <
366 MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166
367 >;
368 };
369};