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git01.mediatek.com / filogic / uboot / 26eaca69c949c853a24824d2296da470bde6cf18 / . / arch / arm / dts / imx8mn-evk.dtsi
blob: fc2c7f1d440d59511e6be940faa05a46935cd9d4 [file] [log] [blame]
Peng Fancdc90f32020-12-27 09:37:06 +0800[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2019 NXP
4 */
5
6#include <dt-bindings/usb/pd.h>
7#include "imx8mn.dtsi"
8
9/ {
10 chosen {
11 stdout-path = &uart2;
12 };
13
14 gpio-leds {
15 compatible = "gpio-leds";
16 pinctrl-names = "default";
17 pinctrl-0 = <&pinctrl_gpio_led>;
18
19 status {
20 label = "yellow:status";
21 gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
22 default-state = "on";
23 };
24 };
25
26 memory@40000000 {
27 device_type = "memory";
28 reg = <0x0 0x40000000 0 0x80000000>;
29 };
30
31 reg_usdhc2_vmmc: regulator-usdhc2 {
32 compatible = "regulator-fixed";
33 pinctrl-names = "default";
34 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
35 regulator-name = "VSD_3V3";
36 regulator-min-microvolt = <3300000>;
37 regulator-max-microvolt = <3300000>;
38 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
39 enable-active-high;
40 };
41
42 ir-receiver {
43 compatible = "gpio-ir-receiver";
44 gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
45 pinctrl-names = "default";
46 pinctrl-0 = <&pinctrl_ir>;
47 linux,autosuspend-period = <125>;
48 };
49};
50
51&fec1 {
52 pinctrl-names = "default";
53 pinctrl-0 = <&pinctrl_fec1>;
54 phy-mode = "rgmii-id";
55 phy-handle = <&ethphy0>;
Marek Vasutf87338f2022-02-19 17:13:54 +0100[diff] [blame]56 phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
Peng Fancdc90f32020-12-27 09:37:06 +0800[diff] [blame]57 fsl,magic-packet;
58 status = "okay";
59
60 mdio {
61 #address-cells = <1>;
62 #size-cells = <0>;
63
64 ethphy0: ethernet-phy@0 {
65 compatible = "ethernet-phy-ieee802.3-c22";
66 reg = <0>;
Heiko Thiery26eaca62022-02-23 09:10:29 +0100[diff] [blame^]67 vddio-supply = <&vddio>;
68
69 vddio: vddio-regulator {
70 regulator-min-microvolt = <1800000>;
71 regulator-max-microvolt = <1800000>;
72 };
Peng Fancdc90f32020-12-27 09:37:06 +0800[diff] [blame]73 };
74 };
75};
76
77&i2c1 {
78 clock-frequency = <400000>;
79 pinctrl-names = "default";
80 pinctrl-0 = <&pinctrl_i2c1>;
81 status = "okay";
82};
83
84&i2c2 {
85 clock-frequency = <400000>;
86 pinctrl-names = "default";
87 pinctrl-0 = <&pinctrl_i2c2>;
88 status = "okay";
89
90 ptn5110: tcpc@50 {
91 compatible = "nxp,ptn5110";
92 pinctrl-names = "default";
93 pinctrl-0 = <&pinctrl_typec1>;
94 reg = <0x50>;
95 interrupt-parent = <&gpio2>;
96 interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
97 status = "okay";
98
99 port {
100 typec1_dr_sw: endpoint {
101 remote-endpoint = <&usb1_drd_sw>;
102 };
103 };
104
105 typec1_con: connector {
106 compatible = "usb-c-connector";
107 label = "USB-C";
108 power-role = "dual";
109 data-role = "dual";
110 try-power-role = "sink";
111 source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
112 sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
113 PDO_VAR(5000, 20000, 3000)>;
114 op-sink-microwatt = <15000000>;
115 self-powered;
116 };
117 };
118};
119
120&i2c3 {
121 clock-frequency = <400000>;
122 pinctrl-names = "default";
123 pinctrl-0 = <&pinctrl_i2c3>;
124 status = "okay";
125
126 pca6416: gpio@20 {
127 compatible = "ti,tca6416";
128 reg = <0x20>;
129 gpio-controller;
130 #gpio-cells = <2>;
131 };
132};
133
134&snvs_pwrkey {
135 status = "okay";
136};
137
138&uart2 { /* console */
139 pinctrl-names = "default";
140 pinctrl-0 = <&pinctrl_uart2>;
141 status = "okay";
142};
143
144&usbotg1 {
145 dr_mode = "otg";
146 hnp-disable;
147 srp-disable;
148 adp-disable;
149 usb-role-switch;
150 samsung,picophy-pre-emp-curr-control = <3>;
151 samsung,picophy-dc-vol-level-adjust = <7>;
152 status = "okay";
153
154 port {
155 usb1_drd_sw: endpoint {
156 remote-endpoint = <&typec1_dr_sw>;
157 };
158 };
159};
160
161&usdhc2 {
162 assigned-clocks = <&clk IMX8MN_CLK_USDHC2>;
163 assigned-clock-rates = <200000000>;
164 pinctrl-names = "default", "state_100mhz", "state_200mhz";
165 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
166 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
167 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
168 cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
169 bus-width = <4>;
170 vmmc-supply = <&reg_usdhc2_vmmc>;
171 status = "okay";
172};
173
174&usdhc3 {
175 assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>;
176 assigned-clock-rates = <400000000>;
177 pinctrl-names = "default", "state_100mhz", "state_200mhz";
178 pinctrl-0 = <&pinctrl_usdhc3>;
179 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
180 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
181 bus-width = <8>;
182 non-removable;
183 status = "okay";
184};
185
186&wdog1 {
187 pinctrl-names = "default";
188 pinctrl-0 = <&pinctrl_wdog>;
189 fsl,ext-reset-output;
190 status = "okay";
191};
192
193&iomuxc {
194 pinctrl_fec1: fec1grp {
195 fsl,pins = <
196 MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3
197 MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
198 MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
199 MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
200 MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
201 MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
202 MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
203 MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
204 MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
205 MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
206 MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
207 MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
208 MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
209 MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
210 MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19
211 >;
212 };
213
214 pinctrl_gpio_led: gpioledgrp {
215 fsl,pins = <
216 MX8MN_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19
217 >;
218 };
219
220 pinctrl_ir: irgrp {
221 fsl,pins = <
222 MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x4f
223 >;
224 };
225
226 pinctrl_i2c1: i2c1grp {
227 fsl,pins = <
228 MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
229 MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
230 >;
231 };
232
233 pinctrl_i2c2: i2c2grp {
234 fsl,pins = <
235 MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
236 MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
237 >;
238 };
239
240 pinctrl_i2c3: i2c3grp {
241 fsl,pins = <
242 MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
243 MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
244 >;
245 };
246
247 pinctrl_pmic: pmicirqgrp {
248 fsl,pins = <
249 MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141
250 >;
251 };
252
253 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
254 fsl,pins = <
255 MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
256 >;
257 };
258
259 pinctrl_typec1: typec1grp {
260 fsl,pins = <
261 MX8MN_IOMUXC_SD1_STROBE_GPIO2_IO11 0x159
262 >;
263 };
264
265 pinctrl_uart2: uart2grp {
266 fsl,pins = <
267 MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
268 MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
269 >;
270 };
271
272 pinctrl_usdhc2_gpio: usdhc2gpiogrp {
273 fsl,pins = <
274 MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4
275 >;
276 };
277
278 pinctrl_usdhc2: usdhc2grp {
279 fsl,pins = <
280 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
281 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
282 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
283 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
284 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
285 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
286 MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
287 >;
288 };
289
290 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
291 fsl,pins = <
292 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
293 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
294 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
295 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
296 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
297 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
298 MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
299 >;
300 };
301
302 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
303 fsl,pins = <
304 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
305 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
306 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
307 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
308 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
309 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
310 MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
311 >;
312 };
313
314 pinctrl_usdhc3: usdhc3grp {
315 fsl,pins = <
316 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000190
317 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
318 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
319 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
320 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
321 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
322 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
323 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
324 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
325 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
326 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
327 >;
328 };
329
330 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
331 fsl,pins = <
332 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000194
333 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
334 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
335 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
336 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
337 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
338 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
339 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
340 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
341 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
342 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
343 >;
344 };
345
346 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
347 fsl,pins = <
348 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000196
349 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
350 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
351 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
352 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
353 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
354 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
355 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
356 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
357 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
358 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
359 >;
360 };
361
362 pinctrl_wdog: wdoggrp {
363 fsl,pins = <
364 MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166
365 >;
366 };
367};