blob: 43cb2d820e89e1a7c2f0e55525ed4a152e39f2d2 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Simon Glass11d7a5b2013-04-17 16:13:36 +00002/*
3 * Copyright (c) 2012 The Chromium OS Authors.
4 *
Bin Meng49f70992014-11-09 22:19:13 +08005 * TSC calibration codes are adapted from Linux kernel
6 * arch/x86/kernel/tsc_msr.c and arch/x86/kernel/tsc.c
Simon Glass11d7a5b2013-04-17 16:13:36 +00007 */
8
9#include <common.h>
Bin Meng976c2e82015-11-13 00:11:21 -080010#include <dm.h>
Simon Glass11d7a5b2013-04-17 16:13:36 +000011#include <malloc.h>
Simon Glass495a5dc2019-11-14 12:57:30 -070012#include <time.h>
Bin Meng976c2e82015-11-13 00:11:21 -080013#include <timer.h>
Bin Mengd159ffb2017-07-25 20:12:01 -070014#include <asm/cpu.h>
Simon Glass11d7a5b2013-04-17 16:13:36 +000015#include <asm/io.h>
16#include <asm/i8254.h>
17#include <asm/ibmpc.h>
18#include <asm/msr.h>
19#include <asm/u-boot-x86.h>
20
Bin Meng7943dc22017-08-15 22:41:50 -070021#define MAX_NUM_FREQS 9
Bin Meng49f70992014-11-09 22:19:13 +080022
Bernhard Messerklinger0576f552019-01-07 12:14:40 +010023#define INTEL_FAM6_SKYLAKE_MOBILE 0x4E
24#define INTEL_FAM6_ATOM_GOLDMONT 0x5C /* Apollo Lake */
25#define INTEL_FAM6_SKYLAKE_DESKTOP 0x5E
26#define INTEL_FAM6_ATOM_GOLDMONT_X 0x5F /* Denverton */
27#define INTEL_FAM6_KABYLAKE_MOBILE 0x8E
28#define INTEL_FAM6_KABYLAKE_DESKTOP 0x9E
29
Simon Glass11d7a5b2013-04-17 16:13:36 +000030DECLARE_GLOBAL_DATA_PTR;
31
Bernhard Messerklinger0576f552019-01-07 12:14:40 +010032/*
33 * native_calibrate_tsc
34 * Determine TSC frequency via CPUID, else return 0.
35 */
36static unsigned long native_calibrate_tsc(void)
37{
38 struct cpuid_result tsc_info;
39 unsigned int crystal_freq;
40
41 if (gd->arch.x86_vendor != X86_VENDOR_INTEL)
42 return 0;
43
44 if (cpuid_eax(0) < 0x15)
45 return 0;
46
47 tsc_info = cpuid(0x15);
48
49 if (tsc_info.ebx == 0 || tsc_info.eax == 0)
50 return 0;
51
52 crystal_freq = tsc_info.ecx / 1000;
Simon Glassbba203e2019-12-06 21:41:50 -070053 if (!CONFIG_IS_ENABLED(X86_TSC_TIMER_NATIVE) && !crystal_freq) {
Bernhard Messerklinger0576f552019-01-07 12:14:40 +010054 switch (gd->arch.x86_model) {
55 case INTEL_FAM6_SKYLAKE_MOBILE:
56 case INTEL_FAM6_SKYLAKE_DESKTOP:
57 case INTEL_FAM6_KABYLAKE_MOBILE:
58 case INTEL_FAM6_KABYLAKE_DESKTOP:
59 crystal_freq = 24000; /* 24.0 MHz */
60 break;
61 case INTEL_FAM6_ATOM_GOLDMONT_X:
62 crystal_freq = 25000; /* 25.0 MHz */
63 break;
64 case INTEL_FAM6_ATOM_GOLDMONT:
65 crystal_freq = 19200; /* 19.2 MHz */
66 break;
67 default:
68 return 0;
69 }
70 }
71
72 return (crystal_freq * tsc_info.ebx / tsc_info.eax) / 1000;
73}
74
Christian Gmeiner1b1472a2018-05-14 11:32:17 +020075static unsigned long cpu_mhz_from_cpuid(void)
76{
77 if (gd->arch.x86_vendor != X86_VENDOR_INTEL)
78 return 0;
79
80 if (cpuid_eax(0) < 0x16)
81 return 0;
82
83 return cpuid_eax(0x16);
84}
85
Bin Meng49f70992014-11-09 22:19:13 +080086/*
87 * According to Intel 64 and IA-32 System Programming Guide,
88 * if MSR_PERF_STAT[31] is set, the maximum resolved bus ratio can be
89 * read in MSR_PLATFORM_ID[12:8], otherwise in MSR_PERF_STAT[44:40].
90 * Unfortunately some Intel Atom SoCs aren't quite compliant to this,
91 * so we need manually differentiate SoC families. This is what the
92 * field msr_plat does.
93 */
94struct freq_desc {
95 u8 x86_family; /* CPU family */
96 u8 x86_model; /* model */
Simon Glass40a8c352014-11-12 22:42:04 -070097 /* 2: use 100MHz, 1: use MSR_PLATFORM_INFO, 0: MSR_IA32_PERF_STATUS */
98 u8 msr_plat;
Bin Meng49f70992014-11-09 22:19:13 +080099 u32 freqs[MAX_NUM_FREQS];
100};
101
102static struct freq_desc freq_desc_tables[] = {
103 /* PNW */
Bin Meng7943dc22017-08-15 22:41:50 -0700104 { 6, 0x27, 0, { 0, 0, 0, 0, 0, 99840, 0, 83200, 0 } },
Bin Meng49f70992014-11-09 22:19:13 +0800105 /* CLV+ */
Bin Meng7943dc22017-08-15 22:41:50 -0700106 { 6, 0x35, 0, { 0, 133200, 0, 0, 0, 99840, 0, 83200, 0 } },
Bin Mengaeb581a2017-07-25 20:12:03 -0700107 /* TNG - Intel Atom processor Z3400 series */
Bin Meng7943dc22017-08-15 22:41:50 -0700108 { 6, 0x4a, 1, { 0, 100000, 133300, 0, 0, 0, 0, 0, 0 } },
Bin Mengaeb581a2017-07-25 20:12:03 -0700109 /* VLV2 - Intel Atom processor E3000, Z3600, Z3700 series */
Bin Meng7943dc22017-08-15 22:41:50 -0700110 { 6, 0x37, 1, { 83300, 100000, 133300, 116700, 80000, 0, 0, 0, 0 } },
Bin Mengaeb581a2017-07-25 20:12:03 -0700111 /* ANN - Intel Atom processor Z3500 series */
Bin Meng7943dc22017-08-15 22:41:50 -0700112 { 6, 0x5a, 1, { 83300, 100000, 133300, 100000, 0, 0, 0, 0, 0 } },
113 /* AMT - Intel Atom processor X7-Z8000 and X5-Z8000 series */
114 { 6, 0x4c, 1, { 83300, 100000, 133300, 116700,
115 80000, 93300, 90000, 88900, 87500 } },
Simon Glass40a8c352014-11-12 22:42:04 -0700116 /* Ivybridge */
Bin Meng7943dc22017-08-15 22:41:50 -0700117 { 6, 0x3a, 2, { 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
Bin Meng49f70992014-11-09 22:19:13 +0800118};
119
120static int match_cpu(u8 family, u8 model)
121{
122 int i;
123
124 for (i = 0; i < ARRAY_SIZE(freq_desc_tables); i++) {
125 if ((family == freq_desc_tables[i].x86_family) &&
126 (model == freq_desc_tables[i].x86_model))
127 return i;
128 }
129
130 return -1;
131}
132
133/* Map CPU reference clock freq ID(0-7) to CPU reference clock freq(KHz) */
134#define id_to_freq(cpu_index, freq_id) \
135 (freq_desc_tables[cpu_index].freqs[freq_id])
136
137/*
Bin Meng6ffad642017-07-25 20:12:05 -0700138 * TSC on Intel Atom SoCs capable of determining TSC frequency by MSR is
139 * reliable and the frequency is known (provided by HW).
Bin Meng49f70992014-11-09 22:19:13 +0800140 *
Bin Meng6ffad642017-07-25 20:12:05 -0700141 * On these platforms PIT/HPET is generally not available so calibration won't
142 * work at all and there is no other clocksource to act as a watchdog for the
143 * TSC, so we have no other choice than to trust it.
144 *
145 * Returns the TSC frequency in MHz or 0 if HW does not provide it.
Bin Meng49f70992014-11-09 22:19:13 +0800146 */
Bin Meng6ffad642017-07-25 20:12:05 -0700147static unsigned long __maybe_unused cpu_mhz_from_msr(void)
Bin Meng49f70992014-11-09 22:19:13 +0800148{
149 u32 lo, hi, ratio, freq_id, freq;
150 unsigned long res;
151 int cpu_index;
152
Bin Mengd159ffb2017-07-25 20:12:01 -0700153 if (gd->arch.x86_vendor != X86_VENDOR_INTEL)
154 return 0;
155
Bin Meng49f70992014-11-09 22:19:13 +0800156 cpu_index = match_cpu(gd->arch.x86, gd->arch.x86_model);
157 if (cpu_index < 0)
158 return 0;
159
160 if (freq_desc_tables[cpu_index].msr_plat) {
161 rdmsr(MSR_PLATFORM_INFO, lo, hi);
Bin Mengf4ed4d72017-07-25 20:12:00 -0700162 ratio = (lo >> 8) & 0xff;
Bin Meng49f70992014-11-09 22:19:13 +0800163 } else {
164 rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
165 ratio = (hi >> 8) & 0x1f;
166 }
167 debug("Maximum core-clock to bus-clock ratio: 0x%x\n", ratio);
168
Simon Glass40a8c352014-11-12 22:42:04 -0700169 if (freq_desc_tables[cpu_index].msr_plat == 2) {
170 /* TODO: Figure out how best to deal with this */
Bin Meng23ee9ab2017-07-25 20:12:04 -0700171 freq = 100000;
Simon Glass40a8c352014-11-12 22:42:04 -0700172 debug("Using frequency: %u KHz\n", freq);
173 } else {
174 /* Get FSB FREQ ID */
175 rdmsr(MSR_FSB_FREQ, lo, hi);
176 freq_id = lo & 0x7;
177 freq = id_to_freq(cpu_index, freq_id);
178 debug("Resolved frequency ID: %u, frequency: %u KHz\n",
179 freq_id, freq);
180 }
Bin Meng49f70992014-11-09 22:19:13 +0800181
182 /* TSC frequency = maximum resolved freq * maximum resolved bus ratio */
183 res = freq * ratio / 1000;
184 debug("TSC runs at %lu MHz\n", res);
185
186 return res;
Bin Meng49f70992014-11-09 22:19:13 +0800187}
188
Bin Mengbba97052014-11-09 22:19:25 +0800189/*
190 * This reads the current MSB of the PIT counter, and
191 * checks if we are running on sufficiently fast and
192 * non-virtualized hardware.
193 *
194 * Our expectations are:
195 *
196 * - the PIT is running at roughly 1.19MHz
197 *
198 * - each IO is going to take about 1us on real hardware,
199 * but we allow it to be much faster (by a factor of 10) or
200 * _slightly_ slower (ie we allow up to a 2us read+counter
201 * update - anything else implies a unacceptably slow CPU
202 * or PIT for the fast calibration to work.
203 *
204 * - with 256 PIT ticks to read the value, we have 214us to
205 * see the same MSB (and overhead like doing a single TSC
206 * read per MSB value etc).
207 *
208 * - We're doing 2 reads per loop (LSB, MSB), and we expect
209 * them each to take about a microsecond on real hardware.
210 * So we expect a count value of around 100. But we'll be
211 * generous, and accept anything over 50.
212 *
213 * - if the PIT is stuck, and we see *many* more reads, we
214 * return early (and the next caller of pit_expect_msb()
215 * then consider it a failure when they don't see the
216 * next expected value).
217 *
218 * These expectations mean that we know that we have seen the
219 * transition from one expected value to another with a fairly
220 * high accuracy, and we didn't miss any events. We can thus
221 * use the TSC value at the transitions to calculate a pretty
222 * good value for the TSC frequencty.
223 */
224static inline int pit_verify_msb(unsigned char val)
225{
226 /* Ignore LSB */
227 inb(0x42);
228 return inb(0x42) == val;
229}
230
231static inline int pit_expect_msb(unsigned char val, u64 *tscp,
232 unsigned long *deltap)
233{
234 int count;
235 u64 tsc = 0, prev_tsc = 0;
236
237 for (count = 0; count < 50000; count++) {
238 if (!pit_verify_msb(val))
239 break;
240 prev_tsc = tsc;
241 tsc = rdtsc();
242 }
243 *deltap = rdtsc() - prev_tsc;
244 *tscp = tsc;
245
246 /*
247 * We require _some_ success, but the quality control
248 * will be based on the error terms on the TSC values.
249 */
250 return count > 5;
251}
252
253/*
254 * How many MSB values do we want to see? We aim for
255 * a maximum error rate of 500ppm (in practice the
256 * real error is much smaller), but refuse to spend
257 * more than 50ms on it.
258 */
259#define MAX_QUICK_PIT_MS 50
260#define MAX_QUICK_PIT_ITERATIONS (MAX_QUICK_PIT_MS * PIT_TICK_RATE / 1000 / 256)
261
Bin Mengb2eb48b2015-01-06 22:14:14 +0800262static unsigned long __maybe_unused quick_pit_calibrate(void)
Bin Mengbba97052014-11-09 22:19:25 +0800263{
264 int i;
265 u64 tsc, delta;
266 unsigned long d1, d2;
267
268 /* Set the Gate high, disable speaker */
269 outb((inb(0x61) & ~0x02) | 0x01, 0x61);
270
271 /*
272 * Counter 2, mode 0 (one-shot), binary count
273 *
274 * NOTE! Mode 2 decrements by two (and then the
275 * output is flipped each time, giving the same
276 * final output frequency as a decrement-by-one),
277 * so mode 0 is much better when looking at the
278 * individual counts.
279 */
280 outb(0xb0, 0x43);
281
282 /* Start at 0xffff */
283 outb(0xff, 0x42);
284 outb(0xff, 0x42);
285
286 /*
287 * The PIT starts counting at the next edge, so we
288 * need to delay for a microsecond. The easiest way
289 * to do that is to just read back the 16-bit counter
290 * once from the PIT.
291 */
292 pit_verify_msb(0);
293
294 if (pit_expect_msb(0xff, &tsc, &d1)) {
295 for (i = 1; i <= MAX_QUICK_PIT_ITERATIONS; i++) {
296 if (!pit_expect_msb(0xff-i, &delta, &d2))
297 break;
298
299 /*
300 * Iterate until the error is less than 500 ppm
301 */
302 delta -= tsc;
303 if (d1+d2 >= delta >> 11)
304 continue;
305
306 /*
307 * Check the PIT one more time to verify that
308 * all TSC reads were stable wrt the PIT.
309 *
310 * This also guarantees serialization of the
311 * last cycle read ('d2') in pit_expect_msb.
312 */
313 if (!pit_verify_msb(0xfe - i))
314 break;
315 goto success;
316 }
317 }
318 debug("Fast TSC calibration failed\n");
319 return 0;
320
321success:
322 /*
323 * Ok, if we get here, then we've seen the
324 * MSB of the PIT decrement 'i' times, and the
325 * error has shrunk to less than 500 ppm.
326 *
327 * As a result, we can depend on there not being
328 * any odd delays anywhere, and the TSC reads are
329 * reliable (within the error).
330 *
331 * kHz = ticks / time-in-seconds / 1000;
332 * kHz = (t2 - t1) / (I * 256 / PIT_TICK_RATE) / 1000
333 * kHz = ((t2 - t1) * PIT_TICK_RATE) / (I * 256 * 1000)
334 */
335 delta *= PIT_TICK_RATE;
336 delta /= (i*256*1000);
337 debug("Fast TSC calibration using PIT\n");
338 return delta / 1000;
339}
340
Simon Glass11d7a5b2013-04-17 16:13:36 +0000341/* Get the speed of the TSC timer in MHz */
Bin Meng500361e2015-11-13 00:11:20 -0800342unsigned notrace long get_tbclk_mhz(void)
Simon Glass11d7a5b2013-04-17 16:13:36 +0000343{
Bin Meng976c2e82015-11-13 00:11:21 -0800344 return get_tbclk() / 1000000;
Simon Glass11d7a5b2013-04-17 16:13:36 +0000345}
346
Simon Glass11d7a5b2013-04-17 16:13:36 +0000347static ulong get_ms_timer(void)
348{
349 return (get_ticks() * 1000) / get_tbclk();
350}
351
352ulong get_timer(ulong base)
353{
354 return get_ms_timer() - base;
355}
356
Bin Meng500361e2015-11-13 00:11:20 -0800357ulong notrace timer_get_us(void)
Simon Glass11d7a5b2013-04-17 16:13:36 +0000358{
359 return get_ticks() / get_tbclk_mhz();
360}
361
362ulong timer_get_boot_us(void)
363{
364 return timer_get_us();
365}
366
367void __udelay(unsigned long usec)
368{
369 u64 now = get_ticks();
370 u64 stop;
371
372 stop = now + usec * get_tbclk_mhz();
373
374 while ((int64_t)(stop - get_ticks()) > 0)
Miao Yanb9f32772015-07-27 19:16:07 +0800375#if defined(CONFIG_QEMU) && defined(CONFIG_SMP)
376 /*
377 * Add a 'pause' instruction on qemu target,
378 * to give other VCPUs a chance to run.
379 */
380 asm volatile("pause");
381#else
Simon Glass11d7a5b2013-04-17 16:13:36 +0000382 ;
Miao Yanb9f32772015-07-27 19:16:07 +0800383#endif
Simon Glass11d7a5b2013-04-17 16:13:36 +0000384}
385
Bin Meng976c2e82015-11-13 00:11:21 -0800386static int tsc_timer_get_count(struct udevice *dev, u64 *count)
387{
388 u64 now_tick = rdtsc();
389
390 *count = now_tick - gd->arch.tsc_base;
391
392 return 0;
393}
394
Bin Meng855e6572018-10-13 20:52:10 -0700395static void tsc_timer_ensure_setup(bool early)
Bin Meng976c2e82015-11-13 00:11:21 -0800396{
Simon Glassed10a4f2019-10-20 21:37:47 -0600397 if (gd->arch.tsc_inited)
Simon Glass471919d2017-09-05 19:49:46 -0600398 return;
Simon Glassd3edd422019-12-06 21:41:49 -0700399 if (IS_ENABLED(CONFIG_X86_TSC_READ_BASE))
400 gd->arch.tsc_base = rdtsc();
Bin Meng976c2e82015-11-13 00:11:21 -0800401
Simon Glass471919d2017-09-05 19:49:46 -0600402 if (!gd->arch.clock_rate) {
Bin Meng976c2e82015-11-13 00:11:21 -0800403 unsigned long fast_calibrate;
404
Bernhard Messerklinger0576f552019-01-07 12:14:40 +0100405 fast_calibrate = native_calibrate_tsc();
406 if (fast_calibrate)
407 goto done;
408
Simon Glassbba203e2019-12-06 21:41:50 -0700409 /* Reduce code size by dropping other methods */
410 if (CONFIG_IS_ENABLED(X86_TSC_TIMER_NATIVE))
411 panic("no timer");
412
Christian Gmeiner1b1472a2018-05-14 11:32:17 +0200413 fast_calibrate = cpu_mhz_from_cpuid();
414 if (fast_calibrate)
415 goto done;
416
Bin Meng6ffad642017-07-25 20:12:05 -0700417 fast_calibrate = cpu_mhz_from_msr();
Christian Gmeiner1b1472a2018-05-14 11:32:17 +0200418 if (fast_calibrate)
419 goto done;
420
421 fast_calibrate = quick_pit_calibrate();
422 if (fast_calibrate)
423 goto done;
424
Bin Meng855e6572018-10-13 20:52:10 -0700425 if (early)
426 fast_calibrate = CONFIG_X86_TSC_TIMER_EARLY_FREQ;
Bin Meng20ffaae2018-08-10 02:39:36 -0700427 else
428 return;
Bin Meng976c2e82015-11-13 00:11:21 -0800429
Christian Gmeiner1b1472a2018-05-14 11:32:17 +0200430done:
Simon Glass471919d2017-09-05 19:49:46 -0600431 gd->arch.clock_rate = fast_calibrate * 1000000;
Bin Meng976c2e82015-11-13 00:11:21 -0800432 }
Simon Glassed10a4f2019-10-20 21:37:47 -0600433 gd->arch.tsc_inited = true;
Simon Glass471919d2017-09-05 19:49:46 -0600434}
435
436static int tsc_timer_probe(struct udevice *dev)
437{
438 struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
439
Bin Meng20ffaae2018-08-10 02:39:36 -0700440 /* Try hardware calibration first */
441 tsc_timer_ensure_setup(false);
442 if (!gd->arch.clock_rate) {
443 /*
444 * Use the clock frequency specified in the
445 * device tree as last resort
446 */
447 if (!uc_priv->clock_rate)
448 panic("TSC frequency is ZERO");
Bin Meng1394fbb2018-06-23 03:03:47 -0700449 } else {
Bin Meng20ffaae2018-08-10 02:39:36 -0700450 uc_priv->clock_rate = gd->arch.clock_rate;
Bin Meng1394fbb2018-06-23 03:03:47 -0700451 }
Bin Meng976c2e82015-11-13 00:11:21 -0800452
453 return 0;
454}
455
Simon Glass471919d2017-09-05 19:49:46 -0600456unsigned long notrace timer_early_get_rate(void)
457{
Bin Meng1394fbb2018-06-23 03:03:47 -0700458 /*
459 * When TSC timer is used as the early timer, be warned that the timer
460 * clock rate can only be calibrated via some hardware ways. Specifying
461 * it in the device tree won't work for the early timer.
462 */
Bin Meng20ffaae2018-08-10 02:39:36 -0700463 tsc_timer_ensure_setup(true);
Simon Glass471919d2017-09-05 19:49:46 -0600464
465 return gd->arch.clock_rate;
466}
467
468u64 notrace timer_early_get_count(void)
469{
Simon Glass4a1050e2019-10-20 21:31:54 -0600470 tsc_timer_ensure_setup(true);
471
Simon Glass471919d2017-09-05 19:49:46 -0600472 return rdtsc() - gd->arch.tsc_base;
473}
474
Bin Meng976c2e82015-11-13 00:11:21 -0800475static const struct timer_ops tsc_timer_ops = {
476 .get_count = tsc_timer_get_count,
477};
478
479static const struct udevice_id tsc_timer_ids[] = {
480 { .compatible = "x86,tsc-timer", },
481 { }
482};
483
484U_BOOT_DRIVER(tsc_timer) = {
485 .name = "tsc_timer",
486 .id = UCLASS_TIMER,
487 .of_match = tsc_timer_ids,
488 .probe = tsc_timer_probe,
489 .ops = &tsc_timer_ops,
Bin Meng976c2e82015-11-13 00:11:21 -0800490};