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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Alexey Brodkin511ab042014-02-04 12:56:19 +04002/*
3 * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
Alexey Brodkin511ab042014-02-04 12:56:19 +04004 */
5
6#include <common.h>
Simon Glass370382c2019-11-14 12:57:35 -07007#include <cpu_func.h>
Alexey Brodkin511ab042014-02-04 12:56:19 +04008#include <dwmmc.h>
Simon Glass97589732020-05-10 11:40:02 -06009#include <init.h>
Alexey Brodkin511ab042014-02-04 12:56:19 +040010#include <malloc.h>
Alexey Brodkin323dad42017-03-31 11:14:35 +030011#include <asm/arcregs.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060012#include <asm/global_data.h>
Alexey Brodkinf8f13b12015-04-09 19:50:58 +030013#include "axs10x.h"
Simon Glass274e0b02020-05-10 11:39:56 -060014#include <asm/cache.h>
Alexey Brodkin511ab042014-02-04 12:56:19 +040015
16DECLARE_GLOBAL_DATA_PTR;
17
Alexey Brodkinf8f13b12015-04-09 19:50:58 +030018#define AXS_MB_CREG 0xE0011000
19
20int board_early_init_f(void)
21{
22 if (readl((void __iomem *)AXS_MB_CREG + 0x234) & (1 << 28))
23 gd->board_type = AXS_MB_V3;
24 else
25 gd->board_type = AXS_MB_V2;
26
27 return 0;
28}
Alexey Brodkincf9cafd2015-04-13 13:37:05 +030029
30#ifdef CONFIG_ISA_ARCV2
Eugeniy Paltsev01f45cc2018-03-23 15:35:03 +030031
32void board_jump_and_run(ulong entry, int zero, int arch, uint params)
33{
34 void (*kernel_entry)(int zero, int arch, uint params);
35
36 kernel_entry = (void (*)(int, int, uint))entry;
37
38 smp_set_core_boot_addr(entry, -1);
39 smp_kick_all_cpus();
40 kernel_entry(zero, arch, params);
41}
42
Alexey Brodkincf9cafd2015-04-13 13:37:05 +030043#define RESET_VECTOR_ADDR 0x0
44
45void smp_set_core_boot_addr(unsigned long addr, int corenr)
46{
47 /* All cores have reset vector pointing to 0 */
48 writel(addr, (void __iomem *)RESET_VECTOR_ADDR);
49
50 /* Make sure other cores see written value in memory */
Alexey Brodkin0fda9642016-06-08 08:19:33 +030051 flush_dcache_all();
Alexey Brodkincf9cafd2015-04-13 13:37:05 +030052}
53
54void smp_kick_all_cpus(void)
55{
56/* CPU start CREG */
57#define AXC003_CREG_CPU_START 0xF0001400
Alexey Brodkincf9cafd2015-04-13 13:37:05 +030058/* Bits positions in CPU start CREG */
59#define BITS_START 0
Alexey Brodkinef5b5172017-03-30 19:18:30 +030060#define BITS_START_MODE 4
Alexey Brodkincf9cafd2015-04-13 13:37:05 +030061#define BITS_CORE_SEL 9
Alexey Brodkincf9cafd2015-04-13 13:37:05 +030062
Alexey Brodkin323dad42017-03-31 11:14:35 +030063/*
64 * In axs103 v1.1 START bits semantics has changed quite a bit.
65 * We used to have a generic START bit for all cores selected by CORE_SEL mask.
66 * But now we don't touch CORE_SEL at all because we have a dedicated START bit
67 * for each core:
68 * bit 0: Core 0 (master)
69 * bit 1: Core 1 (slave)
70 */
71#define BITS_START_CORE1 1
72
73#define ARCVER_HS38_3_0 0x53
74
75 int core_family = read_aux_reg(ARC_AUX_IDENTITY) & 0xff;
Alexey Brodkinef5b5172017-03-30 19:18:30 +030076 int cmd = readl((void __iomem *)AXC003_CREG_CPU_START);
Alexey Brodkin323dad42017-03-31 11:14:35 +030077
78 if (core_family < ARCVER_HS38_3_0) {
79 cmd |= (1 << BITS_CORE_SEL) | (1 << BITS_START);
80 cmd &= ~(1 << BITS_START_MODE);
81 } else {
82 cmd |= (1 << BITS_START_CORE1);
83 }
Alexey Brodkinef5b5172017-03-30 19:18:30 +030084 writel(cmd, (void __iomem *)AXC003_CREG_CPU_START);
Alexey Brodkincf9cafd2015-04-13 13:37:05 +030085}
86#endif
Alexey Brodkindbf9fa22018-11-27 09:47:01 +030087
88int checkboard(void)
89{
90 printf("Board: ARC Software Development Platform AXS%s\n",
91 is_isa_arcv2() ? "103" : "101");
92
93 return 0;
94};