Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Vitaly Andrianov | 7bcf4d6 | 2014-04-04 13:16:53 -0400 | [diff] [blame] | 2 | /* |
| 3 | * Keystone2: DDR3 initialization |
| 4 | * |
| 5 | * (C) Copyright 2012-2014 |
| 6 | * Texas Instruments Incorporated, <www.ti.com> |
Vitaly Andrianov | 7bcf4d6 | 2014-04-04 13:16:53 -0400 | [diff] [blame] | 7 | */ |
| 8 | |
Simon Glass | afb0215 | 2019-12-28 10:45:01 -0700 | [diff] [blame] | 9 | #include <cpu_func.h> |
Simon Glass | ed38aef | 2020-05-10 11:40:03 -0600 | [diff] [blame] | 10 | #include <env.h> |
Vitaly Andrianov | 7bcf4d6 | 2014-04-04 13:16:53 -0400 | [diff] [blame] | 11 | #include <asm/io.h> |
Hao Zhang | d6c508c | 2014-07-09 19:48:41 +0300 | [diff] [blame] | 12 | #include <common.h> |
Vitaly Andrianov | 1917301 | 2014-10-22 17:47:58 +0300 | [diff] [blame] | 13 | #include <asm/arch/msmc.h> |
Khoronzhuk, Ivan | 50df5cc | 2014-07-09 19:48:40 +0300 | [diff] [blame] | 14 | #include <asm/arch/ddr3.h> |
Murali Karicheri | 39f4520 | 2014-09-10 15:54:59 +0300 | [diff] [blame] | 15 | #include <asm/arch/psc_defs.h> |
Simon Glass | dbd7954 | 2020-05-10 11:40:11 -0600 | [diff] [blame] | 16 | #include <linux/delay.h> |
Vitaly Andrianov | 7bcf4d6 | 2014-04-04 13:16:53 -0400 | [diff] [blame] | 17 | |
Vitaly Andrianov | 1917301 | 2014-10-22 17:47:58 +0300 | [diff] [blame] | 18 | #include <asm/ti-common/ti-edma3.h> |
| 19 | |
| 20 | #define DDR3_EDMA_BLK_SIZE_SHIFT 10 |
| 21 | #define DDR3_EDMA_BLK_SIZE (1 << DDR3_EDMA_BLK_SIZE_SHIFT) |
| 22 | #define DDR3_EDMA_BCNT 0x8000 |
| 23 | #define DDR3_EDMA_CCNT 1 |
| 24 | #define DDR3_EDMA_XF_SIZE (DDR3_EDMA_BLK_SIZE * DDR3_EDMA_BCNT) |
| 25 | #define DDR3_EDMA_SLOT_NUM 1 |
| 26 | |
Khoronzhuk, Ivan | 50df5cc | 2014-07-09 19:48:40 +0300 | [diff] [blame] | 27 | void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg) |
Vitaly Andrianov | 7bcf4d6 | 2014-04-04 13:16:53 -0400 | [diff] [blame] | 28 | { |
| 29 | unsigned int tmp; |
| 30 | |
| 31 | while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) |
| 32 | & 0x00000001) != 0x00000001) |
| 33 | ; |
| 34 | |
| 35 | __raw_writel(phy_cfg->pllcr, base + KS2_DDRPHY_PLLCR_OFFSET); |
| 36 | |
| 37 | tmp = __raw_readl(base + KS2_DDRPHY_PGCR1_OFFSET); |
| 38 | tmp &= ~(phy_cfg->pgcr1_mask); |
| 39 | tmp |= phy_cfg->pgcr1_val; |
| 40 | __raw_writel(tmp, base + KS2_DDRPHY_PGCR1_OFFSET); |
| 41 | |
| 42 | __raw_writel(phy_cfg->ptr0, base + KS2_DDRPHY_PTR0_OFFSET); |
| 43 | __raw_writel(phy_cfg->ptr1, base + KS2_DDRPHY_PTR1_OFFSET); |
| 44 | __raw_writel(phy_cfg->ptr3, base + KS2_DDRPHY_PTR3_OFFSET); |
| 45 | __raw_writel(phy_cfg->ptr4, base + KS2_DDRPHY_PTR4_OFFSET); |
| 46 | |
| 47 | tmp = __raw_readl(base + KS2_DDRPHY_DCR_OFFSET); |
| 48 | tmp &= ~(phy_cfg->dcr_mask); |
| 49 | tmp |= phy_cfg->dcr_val; |
| 50 | __raw_writel(tmp, base + KS2_DDRPHY_DCR_OFFSET); |
| 51 | |
| 52 | __raw_writel(phy_cfg->dtpr0, base + KS2_DDRPHY_DTPR0_OFFSET); |
| 53 | __raw_writel(phy_cfg->dtpr1, base + KS2_DDRPHY_DTPR1_OFFSET); |
| 54 | __raw_writel(phy_cfg->dtpr2, base + KS2_DDRPHY_DTPR2_OFFSET); |
| 55 | __raw_writel(phy_cfg->mr0, base + KS2_DDRPHY_MR0_OFFSET); |
| 56 | __raw_writel(phy_cfg->mr1, base + KS2_DDRPHY_MR1_OFFSET); |
Cooper Jr., Franklin | 2247db6 | 2017-06-16 17:25:20 -0500 | [diff] [blame] | 57 | __raw_writel(phy_cfg->mr2, base + KS2_DDRPHY_MR2_OFFSET); |
Vitaly Andrianov | 7bcf4d6 | 2014-04-04 13:16:53 -0400 | [diff] [blame] | 58 | __raw_writel(phy_cfg->dtcr, base + KS2_DDRPHY_DTCR_OFFSET); |
| 59 | __raw_writel(phy_cfg->pgcr2, base + KS2_DDRPHY_PGCR2_OFFSET); |
| 60 | |
| 61 | __raw_writel(phy_cfg->zq0cr1, base + KS2_DDRPHY_ZQ0CR1_OFFSET); |
| 62 | __raw_writel(phy_cfg->zq1cr1, base + KS2_DDRPHY_ZQ1CR1_OFFSET); |
| 63 | __raw_writel(phy_cfg->zq2cr1, base + KS2_DDRPHY_ZQ2CR1_OFFSET); |
| 64 | |
| 65 | __raw_writel(phy_cfg->pir_v1, base + KS2_DDRPHY_PIR_OFFSET); |
| 66 | while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) & 0x1) != 0x1) |
| 67 | ; |
| 68 | |
Vitaly Andrianov | bbf8ac2 | 2015-09-19 16:26:43 +0530 | [diff] [blame] | 69 | if (cpu_is_k2g()) { |
Cooper Jr., Franklin | 87b4b20 | 2017-06-16 17:25:21 -0500 | [diff] [blame] | 70 | clrsetbits_le32(base + KS2_DDRPHY_DATX8_2_OFFSET, |
| 71 | phy_cfg->datx8_2_mask, |
| 72 | phy_cfg->datx8_2_val); |
| 73 | |
| 74 | clrsetbits_le32(base + KS2_DDRPHY_DATX8_3_OFFSET, |
| 75 | phy_cfg->datx8_3_mask, |
| 76 | phy_cfg->datx8_3_val); |
| 77 | |
| 78 | clrsetbits_le32(base + KS2_DDRPHY_DATX8_4_OFFSET, |
| 79 | phy_cfg->datx8_4_mask, |
| 80 | phy_cfg->datx8_4_val); |
| 81 | |
| 82 | clrsetbits_le32(base + KS2_DDRPHY_DATX8_5_OFFSET, |
| 83 | phy_cfg->datx8_5_mask, |
| 84 | phy_cfg->datx8_5_val); |
| 85 | |
| 86 | clrsetbits_le32(base + KS2_DDRPHY_DATX8_6_OFFSET, |
| 87 | phy_cfg->datx8_6_mask, |
| 88 | phy_cfg->datx8_6_val); |
| 89 | |
| 90 | clrsetbits_le32(base + KS2_DDRPHY_DATX8_7_OFFSET, |
| 91 | phy_cfg->datx8_7_mask, |
| 92 | phy_cfg->datx8_7_val); |
| 93 | |
| 94 | clrsetbits_le32(base + KS2_DDRPHY_DATX8_8_OFFSET, |
| 95 | phy_cfg->datx8_8_mask, |
| 96 | phy_cfg->datx8_8_val); |
Vitaly Andrianov | bbf8ac2 | 2015-09-19 16:26:43 +0530 | [diff] [blame] | 97 | } |
| 98 | |
Vitaly Andrianov | 7bcf4d6 | 2014-04-04 13:16:53 -0400 | [diff] [blame] | 99 | __raw_writel(phy_cfg->pir_v2, base + KS2_DDRPHY_PIR_OFFSET); |
| 100 | while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) & 0x1) != 0x1) |
| 101 | ; |
| 102 | } |
| 103 | |
Khoronzhuk, Ivan | 50df5cc | 2014-07-09 19:48:40 +0300 | [diff] [blame] | 104 | void ddr3_init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg) |
Vitaly Andrianov | 7bcf4d6 | 2014-04-04 13:16:53 -0400 | [diff] [blame] | 105 | { |
| 106 | __raw_writel(emif_cfg->sdcfg, base + KS2_DDR3_SDCFG_OFFSET); |
| 107 | __raw_writel(emif_cfg->sdtim1, base + KS2_DDR3_SDTIM1_OFFSET); |
| 108 | __raw_writel(emif_cfg->sdtim2, base + KS2_DDR3_SDTIM2_OFFSET); |
| 109 | __raw_writel(emif_cfg->sdtim3, base + KS2_DDR3_SDTIM3_OFFSET); |
| 110 | __raw_writel(emif_cfg->sdtim4, base + KS2_DDR3_SDTIM4_OFFSET); |
| 111 | __raw_writel(emif_cfg->zqcfg, base + KS2_DDR3_ZQCFG_OFFSET); |
| 112 | __raw_writel(emif_cfg->sdrfc, base + KS2_DDR3_SDRFC_OFFSET); |
| 113 | } |
Hao Zhang | d6c508c | 2014-07-09 19:48:41 +0300 | [diff] [blame] | 114 | |
Vitaly Andrianov | 1917301 | 2014-10-22 17:47:58 +0300 | [diff] [blame] | 115 | int ddr3_ecc_support_rmw(u32 base) |
| 116 | { |
| 117 | u32 value = __raw_readl(base + KS2_DDR3_MIDR_OFFSET); |
| 118 | |
| 119 | /* Check the DDR3 controller ID reg if the controllers |
| 120 | supports ECC RMW or not */ |
| 121 | if (value == 0x40461C02) |
| 122 | return 1; |
| 123 | |
| 124 | return 0; |
| 125 | } |
| 126 | |
| 127 | static void ddr3_ecc_config(u32 base, u32 value) |
| 128 | { |
| 129 | u32 data; |
| 130 | |
| 131 | __raw_writel(value, base + KS2_DDR3_ECC_CTRL_OFFSET); |
| 132 | udelay(100000); /* delay required to synchronize across clock domains */ |
| 133 | |
| 134 | if (value & KS2_DDR3_ECC_EN) { |
| 135 | /* Clear the 1-bit error count */ |
| 136 | data = __raw_readl(base + KS2_DDR3_ONE_BIT_ECC_ERR_CNT_OFFSET); |
| 137 | __raw_writel(data, base + KS2_DDR3_ONE_BIT_ECC_ERR_CNT_OFFSET); |
| 138 | |
| 139 | /* enable the ECC interrupt */ |
| 140 | __raw_writel(KS2_DDR3_1B_ECC_ERR_SYS | KS2_DDR3_2B_ECC_ERR_SYS | |
| 141 | KS2_DDR3_WR_ECC_ERR_SYS, |
| 142 | base + KS2_DDR3_ECC_INT_ENABLE_SET_SYS_OFFSET); |
| 143 | |
| 144 | /* Clear the ECC error interrupt status */ |
| 145 | __raw_writel(KS2_DDR3_1B_ECC_ERR_SYS | KS2_DDR3_2B_ECC_ERR_SYS | |
| 146 | KS2_DDR3_WR_ECC_ERR_SYS, |
| 147 | base + KS2_DDR3_ECC_INT_STATUS_OFFSET); |
| 148 | } |
| 149 | } |
| 150 | |
| 151 | static void ddr3_reset_data(u32 base, u32 ddr3_size) |
| 152 | { |
| 153 | u32 mpax[2]; |
| 154 | u32 seg_num; |
| 155 | u32 seg, blks, dst, edma_blks; |
| 156 | struct edma3_slot_config slot; |
| 157 | struct edma3_channel_config edma_channel; |
| 158 | u32 edma_src[DDR3_EDMA_BLK_SIZE/4] __aligned(16) = {0, }; |
| 159 | |
| 160 | /* Setup an edma to copy the 1k block to the entire DDR */ |
| 161 | puts("\nClear entire DDR3 memory to enable ECC\n"); |
| 162 | |
| 163 | /* save the SES MPAX regs */ |
Nishanth Menon | 854b682 | 2016-11-29 12:07:50 +0530 | [diff] [blame] | 164 | if (cpu_is_k2g()) |
| 165 | msmc_get_ses_mpax(K2G_MSMC_SEGMENT_ARM, 0, mpax); |
| 166 | else |
| 167 | msmc_get_ses_mpax(K2HKLE_MSMC_SEGMENT_ARM, 0, mpax); |
Vitaly Andrianov | 1917301 | 2014-10-22 17:47:58 +0300 | [diff] [blame] | 168 | |
| 169 | /* setup edma slot 1 configuration */ |
| 170 | slot.opt = EDMA3_SLOPT_TRANS_COMP_INT_ENB | |
| 171 | EDMA3_SLOPT_COMP_CODE(0) | |
| 172 | EDMA3_SLOPT_STATIC | EDMA3_SLOPT_AB_SYNC; |
| 173 | slot.bcnt = DDR3_EDMA_BCNT; |
| 174 | slot.acnt = DDR3_EDMA_BLK_SIZE; |
| 175 | slot.ccnt = DDR3_EDMA_CCNT; |
| 176 | slot.src_bidx = 0; |
| 177 | slot.dst_bidx = DDR3_EDMA_BLK_SIZE; |
| 178 | slot.src_cidx = 0; |
| 179 | slot.dst_cidx = 0; |
| 180 | slot.link = EDMA3_PARSET_NULL_LINK; |
| 181 | slot.bcntrld = 0; |
| 182 | edma3_slot_configure(KS2_EDMA0_BASE, DDR3_EDMA_SLOT_NUM, &slot); |
| 183 | |
| 184 | /* configure quik edma channel */ |
| 185 | edma_channel.slot = DDR3_EDMA_SLOT_NUM; |
| 186 | edma_channel.chnum = 0; |
| 187 | edma_channel.complete_code = 0; |
| 188 | /* event trigger after dst update */ |
| 189 | edma_channel.trigger_slot_word = EDMA3_TWORD(dst); |
| 190 | qedma3_start(KS2_EDMA0_BASE, &edma_channel); |
| 191 | |
| 192 | /* DDR3 size in segments (4KB seg size) */ |
| 193 | seg_num = ddr3_size << (30 - KS2_MSMC_SEG_SIZE_SHIFT); |
| 194 | |
| 195 | for (seg = 0; seg < seg_num; seg += KS2_MSMC_MAP_SEG_NUM) { |
| 196 | /* map 2GB 36-bit DDR address to 32-bit DDR address in EMIF |
| 197 | access slave interface so that edma driver can access */ |
Nishanth Menon | 854b682 | 2016-11-29 12:07:50 +0530 | [diff] [blame] | 198 | if (cpu_is_k2g()) { |
| 199 | msmc_map_ses_segment(K2G_MSMC_SEGMENT_ARM, 0, |
| 200 | base >> KS2_MSMC_SEG_SIZE_SHIFT, |
| 201 | KS2_MSMC_DST_SEG_BASE + seg, |
| 202 | MPAX_SEG_2G); |
| 203 | } else { |
| 204 | msmc_map_ses_segment(K2HKLE_MSMC_SEGMENT_ARM, 0, |
| 205 | base >> KS2_MSMC_SEG_SIZE_SHIFT, |
| 206 | KS2_MSMC_DST_SEG_BASE + seg, |
| 207 | MPAX_SEG_2G); |
| 208 | } |
Vitaly Andrianov | 1917301 | 2014-10-22 17:47:58 +0300 | [diff] [blame] | 209 | |
| 210 | if ((seg_num - seg) > KS2_MSMC_MAP_SEG_NUM) |
| 211 | edma_blks = KS2_MSMC_MAP_SEG_NUM << |
| 212 | (KS2_MSMC_SEG_SIZE_SHIFT |
| 213 | - DDR3_EDMA_BLK_SIZE_SHIFT); |
| 214 | else |
| 215 | edma_blks = (seg_num - seg) << (KS2_MSMC_SEG_SIZE_SHIFT |
| 216 | - DDR3_EDMA_BLK_SIZE_SHIFT); |
| 217 | |
| 218 | /* Use edma driver to scrub 2GB DDR memory */ |
| 219 | for (dst = base, blks = 0; blks < edma_blks; |
| 220 | blks += DDR3_EDMA_BCNT, dst += DDR3_EDMA_XF_SIZE) { |
| 221 | edma3_set_src_addr(KS2_EDMA0_BASE, |
| 222 | edma_channel.slot, (u32)edma_src); |
| 223 | edma3_set_dest_addr(KS2_EDMA0_BASE, |
| 224 | edma_channel.slot, (u32)dst); |
| 225 | |
| 226 | while (edma3_check_for_transfer(KS2_EDMA0_BASE, |
| 227 | &edma_channel)) |
| 228 | udelay(10); |
| 229 | } |
| 230 | } |
| 231 | |
| 232 | qedma3_stop(KS2_EDMA0_BASE, &edma_channel); |
| 233 | |
| 234 | /* restore the SES MPAX regs */ |
Nishanth Menon | 854b682 | 2016-11-29 12:07:50 +0530 | [diff] [blame] | 235 | if (cpu_is_k2g()) |
| 236 | msmc_set_ses_mpax(K2G_MSMC_SEGMENT_ARM, 0, mpax); |
| 237 | else |
| 238 | msmc_set_ses_mpax(K2HKLE_MSMC_SEGMENT_ARM, 0, mpax); |
Vitaly Andrianov | 1917301 | 2014-10-22 17:47:58 +0300 | [diff] [blame] | 239 | } |
| 240 | |
| 241 | static void ddr3_ecc_init_range(u32 base) |
| 242 | { |
| 243 | u32 ecc_val = KS2_DDR3_ECC_EN; |
| 244 | u32 rmw = ddr3_ecc_support_rmw(base); |
| 245 | |
| 246 | if (rmw) |
| 247 | ecc_val |= KS2_DDR3_ECC_RMW_EN; |
| 248 | |
| 249 | __raw_writel(0, base + KS2_DDR3_ECC_ADDR_RANGE1_OFFSET); |
| 250 | |
| 251 | ddr3_ecc_config(base, ecc_val); |
| 252 | } |
| 253 | |
| 254 | void ddr3_enable_ecc(u32 base, int test) |
| 255 | { |
| 256 | u32 ecc_val = KS2_DDR3_ECC_ENABLE; |
| 257 | u32 rmw = ddr3_ecc_support_rmw(base); |
| 258 | |
| 259 | if (test) |
| 260 | ecc_val |= KS2_DDR3_ECC_ADDR_RNG_1_EN; |
| 261 | |
| 262 | if (!rmw) { |
| 263 | if (!test) |
| 264 | /* by default, disable ecc when rmw = 0 and no |
| 265 | ecc test */ |
| 266 | ecc_val = 0; |
| 267 | } else { |
| 268 | ecc_val |= KS2_DDR3_ECC_RMW_EN; |
| 269 | } |
| 270 | |
| 271 | ddr3_ecc_config(base, ecc_val); |
| 272 | } |
| 273 | |
| 274 | void ddr3_disable_ecc(u32 base) |
| 275 | { |
| 276 | ddr3_ecc_config(base, 0); |
| 277 | } |
| 278 | |
| 279 | #if defined(CONFIG_SOC_K2HK) || defined(CONFIG_SOC_K2L) |
| 280 | static void cic_init(u32 base) |
| 281 | { |
| 282 | /* Disable CIC global interrupts */ |
| 283 | __raw_writel(0, base + KS2_CIC_GLOBAL_ENABLE); |
| 284 | |
| 285 | /* Set to normal mode, no nesting, no priority hold */ |
| 286 | __raw_writel(0, base + KS2_CIC_CTRL); |
| 287 | __raw_writel(0, base + KS2_CIC_HOST_CTRL); |
| 288 | |
| 289 | /* Enable CIC global interrupts */ |
| 290 | __raw_writel(1, base + KS2_CIC_GLOBAL_ENABLE); |
| 291 | } |
| 292 | |
| 293 | static void cic_map_cic_to_gic(u32 base, u32 chan_num, u32 irq_num) |
| 294 | { |
| 295 | /* Map the system interrupt to a CIC channel */ |
| 296 | __raw_writeb(chan_num, base + KS2_CIC_CHAN_MAP(0) + irq_num); |
| 297 | |
| 298 | /* Enable CIC system interrupt */ |
| 299 | __raw_writel(irq_num, base + KS2_CIC_SYS_ENABLE_IDX_SET); |
| 300 | |
| 301 | /* Enable CIC Host interrupt */ |
| 302 | __raw_writel(chan_num, base + KS2_CIC_HOST_ENABLE_IDX_SET); |
| 303 | } |
| 304 | |
| 305 | static void ddr3_map_ecc_cic2_irq(u32 base) |
| 306 | { |
| 307 | cic_init(base); |
| 308 | cic_map_cic_to_gic(base, KS2_CIC2_DDR3_ECC_CHAN_NUM, |
| 309 | KS2_CIC2_DDR3_ECC_IRQ_NUM); |
| 310 | } |
| 311 | #endif |
| 312 | |
Vitaly Andrianov | a9554d6 | 2015-02-11 14:07:58 -0500 | [diff] [blame] | 313 | void ddr3_init_ecc(u32 base, u32 ddr3_size) |
Vitaly Andrianov | 1917301 | 2014-10-22 17:47:58 +0300 | [diff] [blame] | 314 | { |
Vitaly Andrianov | 1917301 | 2014-10-22 17:47:58 +0300 | [diff] [blame] | 315 | if (!ddr3_ecc_support_rmw(base)) { |
| 316 | ddr3_disable_ecc(base); |
| 317 | return; |
| 318 | } |
| 319 | |
| 320 | ddr3_ecc_init_range(base); |
Vitaly Andrianov | 1917301 | 2014-10-22 17:47:58 +0300 | [diff] [blame] | 321 | ddr3_reset_data(CONFIG_SYS_SDRAM_BASE, ddr3_size); |
| 322 | |
| 323 | /* mapping DDR3 ECC system interrupt from CIC2 to GIC */ |
| 324 | #if defined(CONFIG_SOC_K2HK) || defined(CONFIG_SOC_K2L) |
| 325 | ddr3_map_ecc_cic2_irq(KS2_CIC2_BASE); |
| 326 | #endif |
| 327 | ddr3_enable_ecc(base, 0); |
| 328 | } |
| 329 | |
| 330 | void ddr3_check_ecc_int(u32 base) |
| 331 | { |
| 332 | char *env; |
| 333 | int ecc_test = 0; |
| 334 | u32 value = __raw_readl(base + KS2_DDR3_ECC_INT_STATUS_OFFSET); |
| 335 | |
Simon Glass | 64b723f | 2017-08-03 12:22:12 -0600 | [diff] [blame] | 336 | env = env_get("ecc_test"); |
Vitaly Andrianov | 1917301 | 2014-10-22 17:47:58 +0300 | [diff] [blame] | 337 | if (env) |
| 338 | ecc_test = simple_strtol(env, NULL, 0); |
| 339 | |
| 340 | if (value & KS2_DDR3_WR_ECC_ERR_SYS) |
| 341 | puts("DDR3 ECC write error interrupted\n"); |
| 342 | |
| 343 | if (value & KS2_DDR3_2B_ECC_ERR_SYS) { |
| 344 | puts("DDR3 ECC 2-bit error interrupted\n"); |
| 345 | |
| 346 | if (!ecc_test) { |
| 347 | puts("Reseting the device ...\n"); |
| 348 | reset_cpu(0); |
| 349 | } |
| 350 | } |
| 351 | |
| 352 | value = __raw_readl(base + KS2_DDR3_ONE_BIT_ECC_ERR_CNT_OFFSET); |
| 353 | if (value) { |
| 354 | printf("1-bit ECC err count: 0x%x\n", value); |
| 355 | value = __raw_readl(base + |
| 356 | KS2_DDR3_ONE_BIT_ECC_ERR_ADDR_LOG_OFFSET); |
| 357 | printf("1-bit ECC err address log: 0x%x\n", value); |
| 358 | } |
| 359 | } |
| 360 | |
Hao Zhang | d6c508c | 2014-07-09 19:48:41 +0300 | [diff] [blame] | 361 | void ddr3_reset_ddrphy(void) |
| 362 | { |
| 363 | u32 tmp; |
| 364 | |
| 365 | /* Assert DDR3A PHY reset */ |
Khoronzhuk, Ivan | d5cb1bb | 2014-07-09 23:44:44 +0300 | [diff] [blame] | 366 | tmp = readl(KS2_DDR3APLLCTL1); |
Hao Zhang | d6c508c | 2014-07-09 19:48:41 +0300 | [diff] [blame] | 367 | tmp |= KS2_DDR3_PLLCTRL_PHY_RESET; |
Khoronzhuk, Ivan | d5cb1bb | 2014-07-09 23:44:44 +0300 | [diff] [blame] | 368 | writel(tmp, KS2_DDR3APLLCTL1); |
Hao Zhang | d6c508c | 2014-07-09 19:48:41 +0300 | [diff] [blame] | 369 | |
| 370 | /* wait 10us to catch the reset */ |
| 371 | udelay(10); |
| 372 | |
| 373 | /* Release DDR3A PHY reset */ |
Khoronzhuk, Ivan | d5cb1bb | 2014-07-09 23:44:44 +0300 | [diff] [blame] | 374 | tmp = readl(KS2_DDR3APLLCTL1); |
Hao Zhang | d6c508c | 2014-07-09 19:48:41 +0300 | [diff] [blame] | 375 | tmp &= ~KS2_DDR3_PLLCTRL_PHY_RESET; |
Khoronzhuk, Ivan | d5cb1bb | 2014-07-09 23:44:44 +0300 | [diff] [blame] | 376 | __raw_writel(tmp, KS2_DDR3APLLCTL1); |
Hao Zhang | d6c508c | 2014-07-09 19:48:41 +0300 | [diff] [blame] | 377 | } |
Murali Karicheri | 39f4520 | 2014-09-10 15:54:59 +0300 | [diff] [blame] | 378 | |
| 379 | #ifdef CONFIG_SOC_K2HK |
| 380 | /** |
| 381 | * ddr3_reset_workaround - reset workaround in case if leveling error |
| 382 | * detected for PG 1.0 and 1.1 k2hk SoCs |
| 383 | */ |
| 384 | void ddr3_err_reset_workaround(void) |
| 385 | { |
| 386 | unsigned int tmp; |
| 387 | unsigned int tmp_a; |
| 388 | unsigned int tmp_b; |
| 389 | |
| 390 | /* |
| 391 | * Check for PGSR0 error bits of DDR3 PHY. |
| 392 | * Check for WLERR, QSGERR, WLAERR, |
| 393 | * RDERR, WDERR, REERR, WEERR error to see if they are set or not |
| 394 | */ |
| 395 | tmp_a = __raw_readl(KS2_DDR3A_DDRPHYC + KS2_DDRPHY_PGSR0_OFFSET); |
| 396 | tmp_b = __raw_readl(KS2_DDR3B_DDRPHYC + KS2_DDRPHY_PGSR0_OFFSET); |
| 397 | |
| 398 | if (((tmp_a & 0x0FE00000) != 0) || ((tmp_b & 0x0FE00000) != 0)) { |
| 399 | printf("DDR Leveling Error Detected!\n"); |
| 400 | printf("DDR3A PGSR0 = 0x%x\n", tmp_a); |
| 401 | printf("DDR3B PGSR0 = 0x%x\n", tmp_b); |
| 402 | |
| 403 | /* |
| 404 | * Write Keys to KICK registers to enable writes to registers |
| 405 | * in boot config space |
| 406 | */ |
| 407 | __raw_writel(KS2_KICK0_MAGIC, KS2_KICK0); |
| 408 | __raw_writel(KS2_KICK1_MAGIC, KS2_KICK1); |
| 409 | |
| 410 | /* |
| 411 | * Move DDR3A Module out of reset isolation by setting |
| 412 | * MDCTL23[12] = 0 |
| 413 | */ |
| 414 | tmp_a = __raw_readl(KS2_PSC_BASE + |
| 415 | PSC_REG_MDCTL(KS2_LPSC_EMIF4F_DDR3A)); |
| 416 | |
| 417 | tmp_a = PSC_REG_MDCTL_SET_RESET_ISO(tmp_a, 0); |
| 418 | __raw_writel(tmp_a, KS2_PSC_BASE + |
| 419 | PSC_REG_MDCTL(KS2_LPSC_EMIF4F_DDR3A)); |
| 420 | |
| 421 | /* |
| 422 | * Move DDR3B Module out of reset isolation by setting |
| 423 | * MDCTL24[12] = 0 |
| 424 | */ |
| 425 | tmp_b = __raw_readl(KS2_PSC_BASE + |
| 426 | PSC_REG_MDCTL(KS2_LPSC_EMIF4F_DDR3B)); |
| 427 | tmp_b = PSC_REG_MDCTL_SET_RESET_ISO(tmp_b, 0); |
| 428 | __raw_writel(tmp_b, KS2_PSC_BASE + |
| 429 | PSC_REG_MDCTL(KS2_LPSC_EMIF4F_DDR3B)); |
| 430 | |
| 431 | /* |
| 432 | * Write 0x5A69 Key to RSTCTRL[15:0] to unlock writes |
| 433 | * to RSTCTRL and RSTCFG |
| 434 | */ |
| 435 | tmp = __raw_readl(KS2_RSTCTRL); |
| 436 | tmp &= KS2_RSTCTRL_MASK; |
| 437 | tmp |= KS2_RSTCTRL_KEY; |
| 438 | __raw_writel(tmp, KS2_RSTCTRL); |
| 439 | |
| 440 | /* |
| 441 | * Set PLL Controller to drive hard reset on SW trigger by |
| 442 | * setting RSTCFG[13] = 0 |
| 443 | */ |
| 444 | tmp = __raw_readl(KS2_RSTCTRL_RSCFG); |
| 445 | tmp &= ~KS2_RSTYPE_PLL_SOFT; |
| 446 | __raw_writel(tmp, KS2_RSTCTRL_RSCFG); |
| 447 | |
| 448 | reset_cpu(0); |
| 449 | } |
| 450 | } |
| 451 | #endif |