| commit | d6c508ca7d3fb45d518466cf8d412d826b384c85 | [log] [tgz] |
|---|---|---|
| author | Hao Zhang <hzhang@ti.com> | Wed Jul 09 19:48:41 2014 +0300 |
| committer | Tom Rini <trini@ti.com> | Fri Jul 25 16:26:09 2014 -0400 |
| tree | 3ce38417d6fa5b3131307167e075c18b8f47aa41 | |
| parent | 50df5cc265de601a8b6a5b26cb2e7b1904a160ff [diff] |
keystone2: ddr: add DDR3 PHY configs updated for PG 2.0 Add DDR3 PHY configs updated for PG 2.0 Also add DDR3A PHY reset before init for PG2.0 SoCs. Acked-by: Murali Karicheri <m-maricheri2@ti.com> Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>