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git01.mediatek.com / filogic / uboot / 9a6efd5c8ddfaba0c73958ee8a42ef2e3c2a1ad4 / . / configs / stm32f769-disco_spl_defconfig
blob: 6e03c451c70236195cd2b945c43f73cabfe82cfe [file] [log] [blame]
Yannick Fertréb495e132019-10-07 15:29:10 +0200[diff] [blame]1CONFIG_ARM=y
Trevor Woerner2bcc1ed2020-05-06 08:02:42 -0400[diff] [blame]2CONFIG_ARCH_STM32=y
Simon Glass72cc5382022-10-20 18:22:39 -0600[diff] [blame]3CONFIG_TEXT_BASE=0x08009000
Tom Rinie25a03a2021-11-01 12:19:22 +0000[diff] [blame]4CONFIG_SYS_MALLOC_LEN=0x100000
Patrice Chotardd3e0deb2022-04-27 13:53:55 +0200[diff] [blame]5CONFIG_SPL_GPIO=y
6CONFIG_SPL_LIBCOMMON_SUPPORT=y
7CONFIG_SPL_LIBGENERIC_SUPPORT=y
Tom Rini2e262c42020-08-10 15:31:07 -0400[diff] [blame]8CONFIG_NR_DRAM_BANKS=1
Tom Rini9924ca12023-02-17 09:58:06 -0500[diff] [blame]9CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
10CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20050000
Tom Rini5cd7ece2019-11-18 20:02:10 -0500[diff] [blame]11CONFIG_ENV_SIZE=0x2000
Tom Rinia20e51f2021-06-28 10:17:29 -0400[diff] [blame]12CONFIG_DEFAULT_DEVICE_TREE="stm32f769-disco"
Tom Rini0332a1a2020-07-06 13:54:25 -0400[diff] [blame]13CONFIG_SPL_TEXT_BASE=0x8000000
Tom Rinice53ec82022-08-23 15:24:14 -0400[diff] [blame]14CONFIG_SYS_PROMPT="U-Boot > "
Patrice Chotardd3e0deb2022-04-27 13:53:55 +0200[diff] [blame]15CONFIG_SPL_SERIAL=y
16CONFIG_SPL_DRIVERS_MISC=y
Patrice Chotardd864acd2022-09-20 18:04:31 +0200[diff] [blame]17CONFIG_SPL_SIZE_LIMIT=0x9000
Yannick Fertréb495e132019-10-07 15:29:10 +0200[diff] [blame]18CONFIG_STM32F7=y
19CONFIG_TARGET_STM32F746_DISCO=y
Patrice Chotardd3e0deb2022-04-27 13:53:55 +0200[diff] [blame]20CONFIG_SPL=y
Patrice Chotardd864acd2022-09-20 18:04:31 +0200[diff] [blame]21CONFIG_SYS_LOAD_ADDR=0x8009000
Tom Rini2e340532022-05-23 13:56:21 -0400[diff] [blame]22CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
Tom Rini4b2fcb32022-04-08 13:36:51 -0400[diff] [blame]23CONFIG_DISTRO_DEFAULTS=y
Tom Rini7f184322022-10-28 20:27:07 -0400[diff] [blame]24CONFIG_SYS_MONITOR_LEN=524288
Yannick Fertréb495e132019-10-07 15:29:10 +0200[diff] [blame]25CONFIG_BOOTDELAY=3
Tom Rinif92b6fa2020-10-09 12:22:06 -0400[diff] [blame]26CONFIG_AUTOBOOT_KEYED=y
27CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n"
28CONFIG_AUTOBOOT_STOP_STR=" "
Yannick Fertréb495e132019-10-07 15:29:10 +0200[diff] [blame]29CONFIG_USE_BOOTARGS=y
30CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel"
Yannick Fertréb495e132019-10-07 15:29:10 +0200[diff] [blame]31# CONFIG_DISPLAY_CPUINFO is not set
Patrice Chotardd864acd2022-09-20 18:04:31 +0200[diff] [blame]32CONFIG_SPL_PAD_TO=0x9000
Tom Rini0cb89e72022-05-19 15:09:22 -0400[diff] [blame]33CONFIG_SPL_NO_BSS_LIMIT=y
Patrice Chotardd3e0deb2022-04-27 13:53:55 +0200[diff] [blame]34CONFIG_SPL_BOARD_INIT=y
35CONFIG_SPL_SYS_MALLOC_SIMPLE=y
36CONFIG_SPL_MTD_SUPPORT=y
37CONFIG_SPL_XIP_SUPPORT=y
Tom Rini2c9d2b52022-05-27 22:06:52 -0400[diff] [blame]38CONFIG_SYS_SPL_ARGS_ADDR=0x81c0000
Patrice Chotardd3e0deb2022-04-27 13:53:55 +0200[diff] [blame]39CONFIG_SPL_DM_RESET=y
Tom Rinicbfa1392022-05-11 17:38:09 -0400[diff] [blame]40CONFIG_SYS_PBSIZE=1050
Yannick Fertréb495e132019-10-07 15:29:10 +0200[diff] [blame]41CONFIG_CMD_GPT=y
42# CONFIG_RANDOM_UUID is not set
43CONFIG_CMD_MMC=y
Yannick Fertréb495e132019-10-07 15:29:10 +0200[diff] [blame]44# CONFIG_CMD_SETEXPR is not set
45CONFIG_CMD_SNTP=y
46CONFIG_CMD_DNS=y
47CONFIG_CMD_LINK_LOCAL=y
48CONFIG_CMD_BMP=y
49CONFIG_CMD_CACHE=y
50CONFIG_CMD_TIMER=y
Yannick Fertréb495e132019-10-07 15:29:10 +0200[diff] [blame]51# CONFIG_ISO_PARTITION is not set
Yannick Fertréb495e132019-10-07 15:29:10 +0200[diff] [blame]52CONFIG_OF_CONTROL=y
Patrice Chotardd3e0deb2022-04-27 13:53:55 +0200[diff] [blame]53CONFIG_SPL_OF_CONTROL=y
Tom Rinica63e712019-11-12 22:46:36 -0500[diff] [blame]54CONFIG_SYS_RELOC_GD_ENV_ADDR=y
Yannick Fertréb495e132019-10-07 15:29:10 +0200[diff] [blame]55CONFIG_NET_RANDOM_ETHADDR=y
56CONFIG_NETCONSOLE=y
Patrice Chotardd3e0deb2022-04-27 13:53:55 +0200[diff] [blame]57CONFIG_SPL_DM=y
58CONFIG_SPL_DM_SEQ_ALIAS=y
59CONFIG_SPL_OF_TRANSLATE=y
60CONFIG_SPL_CLK=y
Yannick Fertréb495e132019-10-07 15:29:10 +0200[diff] [blame]61CONFIG_ARM_PL180_MMCI=y
Tom Rinie799f922019-12-04 17:18:38 -0500[diff] [blame]62CONFIG_MTD=y
Miquel Raynala903be42019-10-03 19:50:04 +0200[diff] [blame]63CONFIG_DM_MTD=y
Yannick Fertréb495e132019-10-07 15:29:10 +0200[diff] [blame]64CONFIG_MTD_NOR_FLASH=y
Patrick Delaunay754ff3b2021-10-04 11:05:52 +0200[diff] [blame]65CONFIG_STM32_FLASH=y
Patrice Chotardf3cf5b12022-09-20 18:04:35 +0200[diff] [blame]66CONFIG_SYS_MAX_FLASH_SECT=12
Yannick Fertréb495e132019-10-07 15:29:10 +0200[diff] [blame]67CONFIG_DM_SPI_FLASH=y
Yannick Fertréb495e132019-10-07 15:29:10 +0200[diff] [blame]68CONFIG_SPI_FLASH_MACRONIX=y
69CONFIG_SPI_FLASH_STMICRO=y
Tom Rini5d154192020-04-24 15:35:53 -0400[diff] [blame]70CONFIG_PHY_SMSC=y
Yannick Fertréb495e132019-10-07 15:29:10 +0200[diff] [blame]71CONFIG_ETH_DESIGNWARE=y
Tom Rini7ac21a32022-06-15 12:03:43 -0400[diff] [blame]72CONFIG_DW_ALTDESCRIPTOR=y
Yannick Fertréb495e132019-10-07 15:29:10 +0200[diff] [blame]73CONFIG_MII=y
74# CONFIG_PINCTRL_FULL is not set
Patrice Chotardd3e0deb2022-04-27 13:53:55 +0200[diff] [blame]75CONFIG_SPL_PINCTRL=y
Tom Rini16970382022-09-19 11:22:26 -0400[diff] [blame]76CONFIG_DM_REGULATOR=y
Patrice Chotardd3e0deb2022-04-27 13:53:55 +0200[diff] [blame]77CONFIG_SPL_RAM=y
78CONFIG_SPECIFY_CONSOLE_INDEX=y
Yannick Fertréb495e132019-10-07 15:29:10 +0200[diff] [blame]79CONFIG_SPI=y
80CONFIG_DM_SPI=y
81CONFIG_STM32_QSPI=y
Patrice Chotardd3e0deb2022-04-27 13:53:55 +0200[diff] [blame]82CONFIG_SPL_TIMER=y
Simon Glass52cb5042022-10-18 07:46:31 -0600[diff] [blame]83CONFIG_VIDEO=y
Tom Rinif6e6e1a2020-01-22 13:38:00 -0500[diff] [blame]84CONFIG_BACKLIGHT_GPIO=y
Yannick Fertréb495e132019-10-07 15:29:10 +0200[diff] [blame]85CONFIG_VIDEO_LCD_ORISETECH_OTM8009A=y
86CONFIG_VIDEO_STM32=y
87CONFIG_VIDEO_STM32_DSI=y
88CONFIG_VIDEO_STM32_MAX_XRES=480
89CONFIG_VIDEO_STM32_MAX_YRES=800
Simon Glass2d7a7942020-08-11 11:23:35 -0600[diff] [blame]90CONFIG_SPLASH_SCREEN=y
91CONFIG_SPLASH_SCREEN_ALIGN=y
Patrick Delaunayc47fe772020-09-28 11:30:15 +0200[diff] [blame]92CONFIG_VIDEO_BMP_RLE8=y
Patrick Delaunayb1f17632020-09-28 11:30:16 +0200[diff] [blame]93CONFIG_BMP_16BPP=y
94CONFIG_BMP_24BPP=y
95CONFIG_BMP_32BPP=y
Yannick Fertréb495e132019-10-07 15:29:10 +0200[diff] [blame]96CONFIG_OF_LIBFDT_OVERLAY=y