blob: 8231dde2bfa602d0ebc0e1ec1e01c2d15856e8ad [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -05001# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/watchdog/intel,keembay-wdt.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Intel Keem Bay SoC non-secure Watchdog Timer
8
9maintainers:
10 - Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com>
11
Tom Rini93743d22024-04-01 09:08:13 -040012allOf:
13 - $ref: watchdog.yaml#
14
Tom Rini53633a82024-02-29 12:33:36 -050015properties:
16 compatible:
17 enum:
18 - intel,keembay-wdt
19
20 reg:
21 maxItems: 1
22
23 clocks:
24 maxItems: 1
25
26 interrupts:
27 items:
28 - description: interrupt specifier for threshold interrupt line
29 - description: interrupt specifier for timeout interrupt line
30
31 interrupt-names:
32 items:
33 - const: threshold
34 - const: timeout
35
36required:
37 - compatible
38 - reg
39 - interrupts
40 - interrupt-names
41 - clocks
42
Tom Rini93743d22024-04-01 09:08:13 -040043unevaluatedProperties: false
Tom Rini53633a82024-02-29 12:33:36 -050044
45examples:
46 - |
47 #include <dt-bindings/interrupt-controller/arm-gic.h>
48 #include <dt-bindings/interrupt-controller/irq.h>
49 #define KEEM_BAY_A53_TIM
50
51 watchdog: watchdog@2033009c {
52 compatible = "intel,keembay-wdt";
53 reg = <0x2033009c 0x10>;
54 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
55 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
56 interrupt-names = "threshold", "timeout";
57 clocks = <&scmi_clk KEEM_BAY_A53_TIM>;
58 };
59
60...