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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0
Li Yang5f999732011-07-26 09:50:46 -05002/*
3 * Copyright 2010-2011 Freescale Semiconductor, Inc.
Li Yang5f999732011-07-26 09:50:46 -05004 */
5
Tom Rinidec7ea02024-05-20 13:35:03 -06006#include <config.h>
Simon Glassf5c208d2019-11-14 12:57:20 -07007#include <vsprintf.h>
Tom Rinidec7ea02024-05-20 13:35:03 -06008#include <linux/string.h>
Li Yang5f999732011-07-26 09:50:46 -05009#include <asm/mmu.h>
10#include <asm/immap_85xx.h>
Tom Rinidec7ea02024-05-20 13:35:03 -060011#include <asm/ppc.h>
York Sunf0626592013-09-30 09:22:09 -070012#include <fsl_ddr_sdram.h>
13#include <fsl_ddr_dimm_params.h>
Li Yang5f999732011-07-26 09:50:46 -050014#include <asm/io.h>
15#include <asm/fsl_law.h>
16
York Sun66f05142012-02-29 12:36:51 +000017#ifdef CONFIG_SYS_DDR_RAW_TIMING
Priyanka Jain5a7834a2020-09-21 15:36:25 +053018#if defined(CONFIG_P1020RDB_PROTO)
Li Yang5f999732011-07-26 09:50:46 -050019/* Micron MT41J256M8_187E */
20dimm_params_t ddr_raw_timing = {
21 .n_ranks = 1,
22 .rank_density = 1073741824u,
23 .capacity = 1073741824u,
24 .primary_sdram_width = 32,
25 .ec_sdram_width = 0,
26 .registered_dimm = 0,
27 .mirrored_dimm = 0,
28 .n_row_addr = 15,
29 .n_col_addr = 10,
30 .n_banks_per_sdram_device = 8,
31 .edc_config = 0,
32 .burst_lengths_bitmask = 0x0c,
33
Priyanka Jain4a717412013-09-25 10:41:19 +053034 .tckmin_x_ps = 1870,
35 .caslat_x = 0x1e << 4, /* 5,6,7,8 */
36 .taa_ps = 13125,
37 .twr_ps = 15000,
38 .trcd_ps = 13125,
39 .trrd_ps = 7500,
40 .trp_ps = 13125,
41 .tras_ps = 37500,
42 .trc_ps = 50625,
43 .trfc_ps = 160000,
44 .twtr_ps = 7500,
45 .trtp_ps = 7500,
Li Yang5f999732011-07-26 09:50:46 -050046 .refresh_rate_ps = 7800000,
Priyanka Jain4a717412013-09-25 10:41:19 +053047 .tfaw_ps = 37500,
Li Yang5f999732011-07-26 09:50:46 -050048};
York Sun9c01ff22016-11-17 14:19:18 -080049#elif defined(CONFIG_TARGET_P2020RDB)
Li Yang5f999732011-07-26 09:50:46 -050050/* Micron MT41J128M16_15E */
51dimm_params_t ddr_raw_timing = {
52 .n_ranks = 1,
53 .rank_density = 1073741824u,
54 .capacity = 1073741824u,
55 .primary_sdram_width = 64,
56 .ec_sdram_width = 0,
57 .registered_dimm = 0,
58 .mirrored_dimm = 0,
59 .n_row_addr = 14,
60 .n_col_addr = 10,
61 .n_banks_per_sdram_device = 8,
62 .edc_config = 0,
63 .burst_lengths_bitmask = 0x0c,
64
Priyanka Jain4a717412013-09-25 10:41:19 +053065 .tckmin_x_ps = 1500,
66 .caslat_x = 0x7e << 4, /* 5,6,7,8,9,10 */
67 .taa_ps = 13500,
68 .twr_ps = 15000,
69 .trcd_ps = 13500,
70 .trrd_ps = 6000,
71 .trp_ps = 13500,
72 .tras_ps = 36000,
73 .trc_ps = 49500,
74 .trfc_ps = 160000,
75 .twtr_ps = 7500,
76 .trtp_ps = 7500,
Li Yang5f999732011-07-26 09:50:46 -050077 .refresh_rate_ps = 7800000,
Priyanka Jain4a717412013-09-25 10:41:19 +053078 .tfaw_ps = 30000,
Li Yang5f999732011-07-26 09:50:46 -050079};
York Sun06732382016-11-17 13:53:33 -080080#elif (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD))
Li Yang5f999732011-07-26 09:50:46 -050081/* Micron MT41J512M8_187E */
82dimm_params_t ddr_raw_timing = {
83 .n_ranks = 2,
84 .rank_density = 1073741824u,
85 .capacity = 2147483648u,
86 .primary_sdram_width = 32,
87 .ec_sdram_width = 0,
88 .registered_dimm = 0,
89 .mirrored_dimm = 0,
90 .n_row_addr = 15,
91 .n_col_addr = 10,
92 .n_banks_per_sdram_device = 8,
93 .edc_config = 0,
94 .burst_lengths_bitmask = 0x0c,
95
Priyanka Jain4a717412013-09-25 10:41:19 +053096 .tckmin_x_ps = 1870,
97 .caslat_x = 0x1e << 4, /* 5,6,7,8 */
98 .taa_ps = 13125,
99 .twr_ps = 15000,
100 .trcd_ps = 13125,
101 .trrd_ps = 7500,
102 .trp_ps = 13125,
103 .tras_ps = 37500,
104 .trc_ps = 50625,
105 .trfc_ps = 160000,
106 .twtr_ps = 7500,
107 .trtp_ps = 7500,
Li Yang5f999732011-07-26 09:50:46 -0500108 .refresh_rate_ps = 7800000,
Priyanka Jain4a717412013-09-25 10:41:19 +0530109 .tfaw_ps = 37500,
Li Yang5f999732011-07-26 09:50:46 -0500110};
York Sun443108bf2016-11-17 13:52:44 -0800111#elif defined(CONFIG_TARGET_P1020RDB_PC)
Li Yang5f999732011-07-26 09:50:46 -0500112/*
113 * Samsung K4B2G0846C-HCF8
114 * The following timing are for "downshift"
115 * i.e. to use CL9 part as CL7
116 * otherwise, tAA, tRCD, tRP will be 13500ps
117 * and tRC will be 49500ps
118 */
119dimm_params_t ddr_raw_timing = {
120 .n_ranks = 1,
121 .rank_density = 1073741824u,
122 .capacity = 1073741824u,
123 .primary_sdram_width = 32,
124 .ec_sdram_width = 0,
125 .registered_dimm = 0,
126 .mirrored_dimm = 0,
127 .n_row_addr = 15,
128 .n_col_addr = 10,
129 .n_banks_per_sdram_device = 8,
130 .edc_config = 0,
131 .burst_lengths_bitmask = 0x0c,
132
Priyanka Jain4a717412013-09-25 10:41:19 +0530133 .tckmin_x_ps = 1875,
134 .caslat_x = 0x1e << 4, /* 5,6,7,8 */
135 .taa_ps = 13125,
136 .twr_ps = 15000,
137 .trcd_ps = 13125,
138 .trrd_ps = 7500,
139 .trp_ps = 13125,
140 .tras_ps = 37500,
141 .trc_ps = 50625,
142 .trfc_ps = 160000,
143 .twtr_ps = 7500,
144 .trtp_ps = 7500,
Li Yang5f999732011-07-26 09:50:46 -0500145 .refresh_rate_ps = 7800000,
Priyanka Jain4a717412013-09-25 10:41:19 +0530146 .tfaw_ps = 37500,
Li Yang5f999732011-07-26 09:50:46 -0500147};
Priyanka Jaindbd83d02020-09-21 15:35:16 +0530148#elif defined(CONFIG_TARGET_P1024RDB)
Li Yang5f999732011-07-26 09:50:46 -0500149/*
150 * Samsung K4B2G0846C-HCH9
151 * The following timing are for "downshift"
152 * i.e. to use CL9 part as CL7
153 * otherwise, tAA, tRCD, tRP will be 13500ps
154 * and tRC will be 49500ps
155 */
156dimm_params_t ddr_raw_timing = {
157 .n_ranks = 1,
158 .rank_density = 1073741824u,
159 .capacity = 1073741824u,
160 .primary_sdram_width = 32,
161 .ec_sdram_width = 0,
162 .registered_dimm = 0,
163 .mirrored_dimm = 0,
164 .n_row_addr = 15,
165 .n_col_addr = 10,
166 .n_banks_per_sdram_device = 8,
167 .edc_config = 0,
168 .burst_lengths_bitmask = 0x0c,
169
Priyanka Jain4a717412013-09-25 10:41:19 +0530170 .tckmin_x_ps = 1500,
171 .caslat_x = 0x3e << 4, /* 5,6,7,8,9 */
172 .taa_ps = 13125,
173 .twr_ps = 15000,
174 .trcd_ps = 13125,
175 .trrd_ps = 6000,
176 .trp_ps = 13125,
177 .tras_ps = 36000,
178 .trc_ps = 49125,
179 .trfc_ps = 160000,
180 .twtr_ps = 7500,
181 .trtp_ps = 7500,
Li Yang5f999732011-07-26 09:50:46 -0500182 .refresh_rate_ps = 7800000,
Priyanka Jain4a717412013-09-25 10:41:19 +0530183 .tfaw_ps = 30000,
Li Yang5f999732011-07-26 09:50:46 -0500184};
185#else
186#error Missing raw timing data for this board
187#endif
188
189int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
190 unsigned int controller_number,
191 unsigned int dimm_number)
192{
193 const char dimm_model[] = "Fixed DDR on board";
194
195 if ((controller_number == 0) && (dimm_number == 0)) {
196 memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
197 memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
198 memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
199 }
200
201 return 0;
202}
York Sun66f05142012-02-29 12:36:51 +0000203#endif /* CONFIG_SYS_DDR_RAW_TIMING */
Li Yang5f999732011-07-26 09:50:46 -0500204
Tom Rini6a5dccc2022-11-16 13:10:41 -0500205#ifdef CFG_SYS_DDR_CS0_BNDS
Li Yang5f999732011-07-26 09:50:46 -0500206/* Fixed sdram init -- doesn't use serial presence detect. */
207phys_size_t fixed_sdram(void)
208{
209 sys_info_t sysinfo;
210 char buf[32];
211 size_t ddr_size;
212 fsl_ddr_cfg_regs_t ddr_cfg_regs = {
Tom Rini6a5dccc2022-11-16 13:10:41 -0500213 .cs[0].bnds = CFG_SYS_DDR_CS0_BNDS,
214 .cs[0].config = CFG_SYS_DDR_CS0_CONFIG,
215 .cs[0].config_2 = CFG_SYS_DDR_CS0_CONFIG_2,
Li Yang5f999732011-07-26 09:50:46 -0500216#if CONFIG_CHIP_SELECTS_PER_CTRL > 1
Tom Rini6a5dccc2022-11-16 13:10:41 -0500217 .cs[1].bnds = CFG_SYS_DDR_CS1_BNDS,
218 .cs[1].config = CFG_SYS_DDR_CS1_CONFIG,
219 .cs[1].config_2 = CFG_SYS_DDR_CS1_CONFIG_2,
Li Yang5f999732011-07-26 09:50:46 -0500220#endif
Tom Rini6a5dccc2022-11-16 13:10:41 -0500221 .timing_cfg_3 = CFG_SYS_DDR_TIMING_3,
222 .timing_cfg_0 = CFG_SYS_DDR_TIMING_0,
223 .timing_cfg_1 = CFG_SYS_DDR_TIMING_1,
224 .timing_cfg_2 = CFG_SYS_DDR_TIMING_2,
225 .ddr_sdram_cfg = CFG_SYS_DDR_CONTROL,
226 .ddr_sdram_cfg_2 = CFG_SYS_DDR_CONTROL_2,
227 .ddr_sdram_mode = CFG_SYS_DDR_MODE_1,
228 .ddr_sdram_mode_2 = CFG_SYS_DDR_MODE_2,
229 .ddr_sdram_md_cntl = CFG_SYS_DDR_MODE_CONTROL,
230 .ddr_sdram_interval = CFG_SYS_DDR_INTERVAL,
Tom Rini2b6c0112022-06-27 13:35:51 -0400231 .ddr_data_init = 0xdeadbeef, /* Poison value */
Tom Rini6a5dccc2022-11-16 13:10:41 -0500232 .ddr_sdram_clk_cntl = CFG_SYS_DDR_CLK_CTRL,
233 .ddr_init_addr = CFG_SYS_DDR_INIT_ADDR,
234 .ddr_init_ext_addr = CFG_SYS_DDR_INIT_EXT_ADDR,
235 .timing_cfg_4 = CFG_SYS_DDR_TIMING_4,
236 .timing_cfg_5 = CFG_SYS_DDR_TIMING_5,
237 .ddr_zq_cntl = CFG_SYS_DDR_ZQ_CONTROL,
238 .ddr_wrlvl_cntl = CFG_SYS_DDR_WRLVL_CONTROL,
239 .ddr_sr_cntr = CFG_SYS_DDR_SR_CNTR,
240 .ddr_sdram_rcw_1 = CFG_SYS_DDR_RCW_1,
241 .ddr_sdram_rcw_2 = CFG_SYS_DDR_RCW_2
Li Yang5f999732011-07-26 09:50:46 -0500242 };
243
244 get_sys_info(&sysinfo);
245 printf("Configuring DDR for %s MT/s data rate\n",
Prabhakar Kushwahad1698082013-08-16 14:52:26 +0530246 strmhz(buf, sysinfo.freq_ddrbus));
Li Yang5f999732011-07-26 09:50:46 -0500247
Tom Rinibb4dd962022-11-16 13:10:37 -0500248 ddr_size = CFG_SYS_SDRAM_SIZE * 1024 * 1024;
Li Yang5f999732011-07-26 09:50:46 -0500249
York Sun5e155552013-06-25 11:37:48 -0700250 fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
Li Yang5f999732011-07-26 09:50:46 -0500251
Tom Rini6a5dccc2022-11-16 13:10:41 -0500252 if (set_ddr_laws(CFG_SYS_DDR_SDRAM_BASE,
Li Yang5f999732011-07-26 09:50:46 -0500253 ddr_size, LAW_TRGT_IF_DDR_1) < 0) {
254 printf("ERROR setting Local Access Windows for DDR\n");
255 return 0;
256 };
257
258 return ddr_size;
259}
Scott Wood03fedda2012-10-12 18:02:24 -0500260#endif
Li Yang5f999732011-07-26 09:50:46 -0500261
262void fsl_ddr_board_options(memctl_options_t *popts,
263 dimm_params_t *pdimm,
264 unsigned int ctrl_num)
265{
266 int i;
267 popts->clk_adjust = 6;
268 popts->cpo_override = 0x1f;
269 popts->write_data_delay = 2;
270 popts->half_strength_driver_enable = 1;
271 /* Write leveling override */
272 popts->wrlvl_en = 1;
273 popts->wrlvl_override = 1;
274 popts->wrlvl_sample = 0xf;
275 popts->wrlvl_start = 0x8;
276 popts->trwt_override = 1;
277 popts->trwt = 0;
278
279 if (pdimm->primary_sdram_width == 64)
280 popts->data_bus_width = 0;
281 else if (pdimm->primary_sdram_width == 32)
282 popts->data_bus_width = 1;
283 else
284 printf("Error in DDR bus width configuration!\n");
285
286 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
287 popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
288 popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
289 }
290}