Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / 9978cd06f2c9fa329cf6e78f4b1a8e5290cd9f12 / . / board / nvidia / harmony / harmony.c
blob: da14e09c40cc4e0a7932d3fb9f00d9eddc29d5e8 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
Tom Warrene1495582011-04-14 12:09:41 +0000[diff] [blame]2/*
3 * (C) Copyright 2010,2011
4 * NVIDIA Corporation <www.nvidia.com>
Tom Warrene1495582011-04-14 12:09:41 +0000[diff] [blame]5 */
6
Tom Warrene1495582011-04-14 12:09:41 +0000[diff] [blame]7#include <asm/io.h>
Simon Glassd677c8e2012-01-11 12:42:27 +0000[diff] [blame]8#include <asm/arch/clock.h>
9#include <asm/arch/funcmux.h>
Stephen Warrenf8eac0d2011-10-31 06:51:35 +0000[diff] [blame]10#include <asm/arch/pinmux.h>
Tom Warrenab371962012-09-19 15:50:56 -0700[diff] [blame]11#include <asm/arch/tegra.h>
Stephen Warrenfba87542011-10-31 06:51:36 +0000[diff] [blame]12#include <asm/gpio.h>
Tom Warren97bf58f2011-09-21 12:40:07 +0000[diff] [blame]13
Masahiro Yamadab2c88682017-01-10 13:32:07 +0900[diff] [blame]14#ifdef CONFIG_MMC_SDHCI_TEGRA
Tom Warren97bf58f2011-09-21 12:40:07 +0000[diff] [blame]15/*
Stephen Warrenf8eac0d2011-10-31 06:51:35 +0000[diff] [blame]16 * Routine: pin_mux_mmc
17 * Description: setup the pin muxes/tristate values for the SDMMC(s)
18 */
Tom Warren9745cf82013-02-21 12:31:30 +0000[diff] [blame]19void pin_mux_mmc(void)
Stephen Warrenf8eac0d2011-10-31 06:51:35 +0000[diff] [blame]20{
Simon Glassd677c8e2012-01-11 12:42:27 +0000[diff] [blame]21 funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_GME_8_BIT);
22 funcmux_select(PERIPH_ID_SDMMC2, FUNCMUX_SDMMC2_DTA_DTD_8BIT);
Stephen Warrenf8eac0d2011-10-31 06:51:35 +0000[diff] [blame]23
24 /* For power GPIO PI6 */
Stephen Warrenf27f4e82014-03-21 12:28:58 -0600[diff] [blame]25 pinmux_tristate_disable(PMUX_PINGRP_ATA);
Stephen Warrenf8eac0d2011-10-31 06:51:35 +0000[diff] [blame]26 /* For CD GPIO PH2 */
Stephen Warrenf27f4e82014-03-21 12:28:58 -0600[diff] [blame]27 pinmux_tristate_disable(PMUX_PINGRP_ATD);
Stephen Warrenf8eac0d2011-10-31 06:51:35 +0000[diff] [blame]28
Stephen Warrenf8eac0d2011-10-31 06:51:35 +0000[diff] [blame]29 /* For power GPIO PT3 */
Stephen Warrenf27f4e82014-03-21 12:28:58 -0600[diff] [blame]30 pinmux_tristate_disable(PMUX_PINGRP_DTB);
Stephen Warrenf8eac0d2011-10-31 06:51:35 +0000[diff] [blame]31 /* For CD GPIO PI5 */
Stephen Warrenf27f4e82014-03-21 12:28:58 -0600[diff] [blame]32 pinmux_tristate_disable(PMUX_PINGRP_ATC);
Stephen Warrenf8eac0d2011-10-31 06:51:35 +0000[diff] [blame]33}
Tom Warren97bf58f2011-09-21 12:40:07 +0000[diff] [blame]34#endif
Stephen Warrenb03192e2012-10-12 09:45:48 +0000[diff] [blame]35
36void pin_mux_usb(void)
37{
38 funcmux_select(PERIPH_ID_USB2, FUNCMUX_USB2_ULPI);
Stephen Warrenf27f4e82014-03-21 12:28:58 -0600[diff] [blame]39 pinmux_set_func(PMUX_PINGRP_CDEV2, PMUX_FUNC_PLLP_OUT4);
40 pinmux_tristate_disable(PMUX_PINGRP_CDEV2);
Stephen Warrenb03192e2012-10-12 09:45:48 +0000[diff] [blame]41 /* USB2 PHY reset GPIO */
Stephen Warrenf27f4e82014-03-21 12:28:58 -0600[diff] [blame]42 pinmux_tristate_disable(PMUX_PINGRP_UAC);
Stephen Warrenb03192e2012-10-12 09:45:48 +0000[diff] [blame]43}
Stephen Warrenf0083342013-06-18 09:46:51 -0600[diff] [blame]44
45void pin_mux_display(void)
46{
Stephen Warrenf27f4e82014-03-21 12:28:58 -0600[diff] [blame]47 pinmux_set_func(PMUX_PINGRP_SDC, PMUX_FUNC_PWM);
48 pinmux_tristate_disable(PMUX_PINGRP_SDC);
Stephen Warrenf0083342013-06-18 09:46:51 -0600[diff] [blame]49}