Stefan Roese | d07117e | 2007-02-20 10:27:08 +0100 | [diff] [blame] | 1 | /* |
Stefan Roese | 77c1f1d | 2009-11-19 14:03:17 +0100 | [diff] [blame] | 2 | * (C) Copyright 2007-2009 |
Stefan Roese | d07117e | 2007-02-20 10:27:08 +0100 | [diff] [blame] | 3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. |
| 4 | * |
| 5 | * based on work by Anne Sophie Harnois <anne-sophie.harnois@nextream.fr> |
| 6 | * |
| 7 | * (C) Copyright 2001 |
| 8 | * Bill Hunter, Wave 7 Optics, williamhunter@mediaone.net |
| 9 | * |
| 10 | * See file CREDITS for list of people who contributed to this |
| 11 | * project. |
| 12 | * |
| 13 | * This program is free software; you can redistribute it and/or |
| 14 | * modify it under the terms of the GNU General Public License as |
| 15 | * published by the Free Software Foundation; either version 2 of |
| 16 | * the License, or (at your option) any later version. |
| 17 | * |
| 18 | * This program is distributed in the hope that it will be useful, |
| 19 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 20 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 21 | * GNU General Public License for more details. |
| 22 | * |
| 23 | * You should have received a copy of the GNU General Public License |
| 24 | * along with this program; if not, write to the Free Software |
| 25 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 26 | * MA 02111-1307 USA |
| 27 | */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 28 | |
| 29 | #include <common.h> |
Stefan Roese | 247e9d7 | 2010-09-09 19:18:00 +0200 | [diff] [blame] | 30 | #include <asm/ppc4xx.h> |
| 31 | #include <asm/ppc4xx-i2c.h> |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 32 | #include <i2c.h> |
Peter Tyser | 133c0fe | 2010-04-12 22:28:07 -0500 | [diff] [blame] | 33 | #include <asm/io.h> |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 34 | |
| 35 | #ifdef CONFIG_HARD_I2C |
| 36 | |
Wolfgang Denk | 6405a15 | 2006-03-31 18:32:53 +0200 | [diff] [blame] | 37 | DECLARE_GLOBAL_DATA_PTR; |
| 38 | |
Stefan Roese | d07117e | 2007-02-20 10:27:08 +0100 | [diff] [blame] | 39 | #if defined(CONFIG_I2C_MULTI_BUS) |
Stefan Roese | 77c1f1d | 2009-11-19 14:03:17 +0100 | [diff] [blame] | 40 | /* |
| 41 | * Initialize the bus pointer to whatever one the SPD EEPROM is on. |
Stefan Roese | d07117e | 2007-02-20 10:27:08 +0100 | [diff] [blame] | 42 | * Default is bus 0. This is necessary because the DDR initialization |
| 43 | * runs from ROM, and we can't switch buses because we can't modify |
| 44 | * the global variables. |
| 45 | */ |
Trent Piepho | 3e9dabd | 2008-11-12 17:29:48 -0800 | [diff] [blame] | 46 | #ifndef CONFIG_SYS_SPD_BUS_NUM |
| 47 | #define CONFIG_SYS_SPD_BUS_NUM 0 |
Stefan Roese | d07117e | 2007-02-20 10:27:08 +0100 | [diff] [blame] | 48 | #endif |
Stefan Roese | 77c1f1d | 2009-11-19 14:03:17 +0100 | [diff] [blame] | 49 | static unsigned int i2c_bus_num __attribute__ ((section (".data"))) = |
| 50 | CONFIG_SYS_SPD_BUS_NUM; |
Stefan Roese | d07117e | 2007-02-20 10:27:08 +0100 | [diff] [blame] | 51 | #endif /* CONFIG_I2C_MULTI_BUS */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 52 | |
Stefan Roese | d07117e | 2007-02-20 10:27:08 +0100 | [diff] [blame] | 53 | static void _i2c_bus_reset(void) |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 54 | { |
Stefan Roese | 77c1f1d | 2009-11-19 14:03:17 +0100 | [diff] [blame] | 55 | struct ppc4xx_i2c *i2c = (struct ppc4xx_i2c *)I2C_BASE_ADDR; |
Stefan Roese | d07117e | 2007-02-20 10:27:08 +0100 | [diff] [blame] | 56 | int i; |
| 57 | u8 dc; |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 58 | |
| 59 | /* Reset status register */ |
| 60 | /* write 1 in SCMP and IRQA to clear these fields */ |
Stefan Roese | 77c1f1d | 2009-11-19 14:03:17 +0100 | [diff] [blame] | 61 | out_8(&i2c->sts, 0x0A); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 62 | |
| 63 | /* write 1 in IRQP IRQD LA ICT XFRA to clear these fields */ |
Stefan Roese | 77c1f1d | 2009-11-19 14:03:17 +0100 | [diff] [blame] | 64 | out_8(&i2c->extsts, 0x8F); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 65 | |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 66 | /* Place chip in the reset state */ |
Stefan Roese | 77c1f1d | 2009-11-19 14:03:17 +0100 | [diff] [blame] | 67 | out_8(&i2c->xtcntlss, IIC_XTCNTLSS_SRST); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 68 | |
Stefan Roese | d07117e | 2007-02-20 10:27:08 +0100 | [diff] [blame] | 69 | /* Check if bus is free */ |
Stefan Roese | 77c1f1d | 2009-11-19 14:03:17 +0100 | [diff] [blame] | 70 | dc = in_8(&i2c->directcntl); |
Stefan Roese | d07117e | 2007-02-20 10:27:08 +0100 | [diff] [blame] | 71 | if (!DIRCTNL_FREE(dc)){ |
| 72 | /* Try to set bus free state */ |
Stefan Roese | 77c1f1d | 2009-11-19 14:03:17 +0100 | [diff] [blame] | 73 | out_8(&i2c->directcntl, IIC_DIRCNTL_SDAC | IIC_DIRCNTL_SCC); |
Stefan Roese | d07117e | 2007-02-20 10:27:08 +0100 | [diff] [blame] | 74 | |
| 75 | /* Wait until we regain bus control */ |
| 76 | for (i = 0; i < 100; ++i) { |
Stefan Roese | 77c1f1d | 2009-11-19 14:03:17 +0100 | [diff] [blame] | 77 | dc = in_8(&i2c->directcntl); |
Stefan Roese | d07117e | 2007-02-20 10:27:08 +0100 | [diff] [blame] | 78 | if (DIRCTNL_FREE(dc)) |
| 79 | break; |
| 80 | |
| 81 | /* Toggle SCL line */ |
| 82 | dc ^= IIC_DIRCNTL_SCC; |
Stefan Roese | 77c1f1d | 2009-11-19 14:03:17 +0100 | [diff] [blame] | 83 | out_8(&i2c->directcntl, dc); |
Stefan Roese | d07117e | 2007-02-20 10:27:08 +0100 | [diff] [blame] | 84 | udelay(10); |
| 85 | dc ^= IIC_DIRCNTL_SCC; |
Stefan Roese | 77c1f1d | 2009-11-19 14:03:17 +0100 | [diff] [blame] | 86 | out_8(&i2c->directcntl, dc); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 87 | } |
| 88 | } |
Stefan Roese | d07117e | 2007-02-20 10:27:08 +0100 | [diff] [blame] | 89 | |
| 90 | /* Remove reset */ |
Stefan Roese | 77c1f1d | 2009-11-19 14:03:17 +0100 | [diff] [blame] | 91 | out_8(&i2c->xtcntlss, 0); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 92 | } |
| 93 | |
Stefan Roese | 77c1f1d | 2009-11-19 14:03:17 +0100 | [diff] [blame] | 94 | void i2c_init(int speed, int slaveaddr) |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 95 | { |
Stefan Roese | b1bcb0e | 2010-03-29 15:30:46 +0200 | [diff] [blame] | 96 | struct ppc4xx_i2c *i2c; |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 97 | int val, divisor; |
Stefan Roese | d07117e | 2007-02-20 10:27:08 +0100 | [diff] [blame] | 98 | int bus; |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 99 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 100 | #ifdef CONFIG_SYS_I2C_INIT_BOARD |
Stefan Roese | 77c1f1d | 2009-11-19 14:03:17 +0100 | [diff] [blame] | 101 | /* |
| 102 | * Call board specific i2c bus reset routine before accessing the |
| 103 | * environment, which might be in a chip on that bus. For details |
| 104 | * about this problem see doc/I2C_Edge_Conditions. |
| 105 | */ |
wdenk | cc1e256 | 2003-03-06 13:39:27 +0000 | [diff] [blame] | 106 | i2c_init_board(); |
| 107 | #endif |
| 108 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 109 | for (bus = 0; bus < CONFIG_SYS_MAX_I2C_BUS; bus++) { |
Stefan Roese | d07117e | 2007-02-20 10:27:08 +0100 | [diff] [blame] | 110 | I2C_SET_BUS(bus); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 111 | |
Stefan Roese | b1bcb0e | 2010-03-29 15:30:46 +0200 | [diff] [blame] | 112 | /* Set i2c pointer after calling I2C_SET_BUS() */ |
| 113 | i2c = (struct ppc4xx_i2c *)I2C_BASE_ADDR; |
| 114 | |
Stefan Roese | d07117e | 2007-02-20 10:27:08 +0100 | [diff] [blame] | 115 | /* Handle possible failed I2C state */ |
| 116 | /* FIXME: put this into i2c_init_board()? */ |
| 117 | _i2c_bus_reset(); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 118 | |
Stefan Roese | d07117e | 2007-02-20 10:27:08 +0100 | [diff] [blame] | 119 | /* clear lo master address */ |
Stefan Roese | 77c1f1d | 2009-11-19 14:03:17 +0100 | [diff] [blame] | 120 | out_8(&i2c->lmadr, 0); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 121 | |
Stefan Roese | d07117e | 2007-02-20 10:27:08 +0100 | [diff] [blame] | 122 | /* clear hi master address */ |
Stefan Roese | 77c1f1d | 2009-11-19 14:03:17 +0100 | [diff] [blame] | 123 | out_8(&i2c->hmadr, 0); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 124 | |
Stefan Roese | d07117e | 2007-02-20 10:27:08 +0100 | [diff] [blame] | 125 | /* clear lo slave address */ |
Stefan Roese | 77c1f1d | 2009-11-19 14:03:17 +0100 | [diff] [blame] | 126 | out_8(&i2c->lsadr, 0); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 127 | |
Stefan Roese | d07117e | 2007-02-20 10:27:08 +0100 | [diff] [blame] | 128 | /* clear hi slave address */ |
Stefan Roese | 77c1f1d | 2009-11-19 14:03:17 +0100 | [diff] [blame] | 129 | out_8(&i2c->hsadr, 0); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 130 | |
Stefan Roese | d07117e | 2007-02-20 10:27:08 +0100 | [diff] [blame] | 131 | /* Clock divide Register */ |
Stefan Roese | 77c1f1d | 2009-11-19 14:03:17 +0100 | [diff] [blame] | 132 | /* set divisor according to freq_opb */ |
| 133 | divisor = (get_OPB_freq() - 1) / 10000000; |
Stefan Roese | d07117e | 2007-02-20 10:27:08 +0100 | [diff] [blame] | 134 | if (divisor == 0) |
| 135 | divisor = 1; |
Stefan Roese | 77c1f1d | 2009-11-19 14:03:17 +0100 | [diff] [blame] | 136 | out_8(&i2c->clkdiv, divisor); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 137 | |
Stefan Roese | d07117e | 2007-02-20 10:27:08 +0100 | [diff] [blame] | 138 | /* no interrupts */ |
Stefan Roese | 77c1f1d | 2009-11-19 14:03:17 +0100 | [diff] [blame] | 139 | out_8(&i2c->intrmsk, 0); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 140 | |
Stefan Roese | d07117e | 2007-02-20 10:27:08 +0100 | [diff] [blame] | 141 | /* clear transfer count */ |
Stefan Roese | 77c1f1d | 2009-11-19 14:03:17 +0100 | [diff] [blame] | 142 | out_8(&i2c->xfrcnt, 0); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 143 | |
Stefan Roese | d07117e | 2007-02-20 10:27:08 +0100 | [diff] [blame] | 144 | /* clear extended control & stat */ |
| 145 | /* write 1 in SRC SRS SWC SWS to clear these fields */ |
Stefan Roese | 77c1f1d | 2009-11-19 14:03:17 +0100 | [diff] [blame] | 146 | out_8(&i2c->xtcntlss, 0xF0); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 147 | |
Stefan Roese | d07117e | 2007-02-20 10:27:08 +0100 | [diff] [blame] | 148 | /* Mode Control Register |
| 149 | Flush Slave/Master data buffer */ |
Stefan Roese | 77c1f1d | 2009-11-19 14:03:17 +0100 | [diff] [blame] | 150 | out_8(&i2c->mdcntl, IIC_MDCNTL_FSDB | IIC_MDCNTL_FMDB); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 151 | |
Stefan Roese | 77c1f1d | 2009-11-19 14:03:17 +0100 | [diff] [blame] | 152 | val = in_8(&i2c->mdcntl); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 153 | |
Stefan Roese | d07117e | 2007-02-20 10:27:08 +0100 | [diff] [blame] | 154 | /* Ignore General Call, slave transfers are ignored, |
| 155 | * disable interrupts, exit unknown bus state, enable hold |
| 156 | * SCL 100kHz normaly or FastMode for 400kHz and above |
| 157 | */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 158 | |
Stefan Roese | 77c1f1d | 2009-11-19 14:03:17 +0100 | [diff] [blame] | 159 | val |= IIC_MDCNTL_EUBS | IIC_MDCNTL_HSCL; |
Stefan Roese | d07117e | 2007-02-20 10:27:08 +0100 | [diff] [blame] | 160 | if (speed >= 400000) |
| 161 | val |= IIC_MDCNTL_FSM; |
Stefan Roese | 77c1f1d | 2009-11-19 14:03:17 +0100 | [diff] [blame] | 162 | out_8(&i2c->mdcntl, val); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 163 | |
Stefan Roese | d07117e | 2007-02-20 10:27:08 +0100 | [diff] [blame] | 164 | /* clear control reg */ |
Stefan Roese | 77c1f1d | 2009-11-19 14:03:17 +0100 | [diff] [blame] | 165 | out_8(&i2c->cntl, 0x00); |
Stefan Roese | d07117e | 2007-02-20 10:27:08 +0100 | [diff] [blame] | 166 | } |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 167 | |
Stefan Roese | d07117e | 2007-02-20 10:27:08 +0100 | [diff] [blame] | 168 | /* set to SPD bus as default bus upon powerup */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 169 | I2C_SET_BUS(CONFIG_SYS_SPD_BUS_NUM); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 170 | } |
| 171 | |
| 172 | /* |
Stefan Roese | d07117e | 2007-02-20 10:27:08 +0100 | [diff] [blame] | 173 | * This code tries to use the features of the 405GP i2c |
| 174 | * controller. It will transfer up to 4 bytes in one pass |
| 175 | * on the loop. It only does out_8((u8 *)lbz) to the buffer when it |
| 176 | * is possible to do out16(lhz) transfers. |
| 177 | * |
| 178 | * cmd_type is 0 for write 1 for read. |
| 179 | * |
| 180 | * addr_len can take any value from 0-255, it is only limited |
| 181 | * by the char, we could make it larger if needed. If it is |
| 182 | * 0 we skip the address write cycle. |
| 183 | * |
| 184 | * Typical case is a Write of an addr followd by a Read. The |
| 185 | * IBM FAQ does not cover this. On the last byte of the write |
| 186 | * we don't set the creg CHT bit, and on the first bytes of the |
| 187 | * read we set the RPST bit. |
| 188 | * |
| 189 | * It does not support address only transfers, there must be |
| 190 | * a data part. If you want to write the address yourself, put |
| 191 | * it in the data pointer. |
| 192 | * |
| 193 | * It does not support transfer to/from address 0. |
| 194 | * |
| 195 | * It does not check XFRCNT. |
| 196 | */ |
| 197 | static int i2c_transfer(unsigned char cmd_type, |
| 198 | unsigned char chip, |
| 199 | unsigned char addr[], |
| 200 | unsigned char addr_len, |
| 201 | unsigned char data[], |
| 202 | unsigned short data_len) |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 203 | { |
Stefan Roese | 77c1f1d | 2009-11-19 14:03:17 +0100 | [diff] [blame] | 204 | struct ppc4xx_i2c *i2c = (struct ppc4xx_i2c *)I2C_BASE_ADDR; |
| 205 | u8 *ptr; |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 206 | int reading; |
Stefan Roese | 77c1f1d | 2009-11-19 14:03:17 +0100 | [diff] [blame] | 207 | int tran, cnt; |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 208 | int result; |
| 209 | int status; |
| 210 | int i; |
Stefan Roese | 77c1f1d | 2009-11-19 14:03:17 +0100 | [diff] [blame] | 211 | u8 creg; |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 212 | |
Stefan Roese | d07117e | 2007-02-20 10:27:08 +0100 | [diff] [blame] | 213 | if (data == 0 || data_len == 0) { |
| 214 | /* Don't support data transfer of no length or to address 0 */ |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 215 | printf( "i2c_transfer: bad call\n" ); |
| 216 | return IIC_NOK; |
| 217 | } |
Stefan Roese | d07117e | 2007-02-20 10:27:08 +0100 | [diff] [blame] | 218 | if (addr && addr_len) { |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 219 | ptr = addr; |
| 220 | cnt = addr_len; |
| 221 | reading = 0; |
Stefan Roese | d07117e | 2007-02-20 10:27:08 +0100 | [diff] [blame] | 222 | } else { |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 223 | ptr = data; |
| 224 | cnt = data_len; |
| 225 | reading = cmd_type; |
| 226 | } |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 227 | |
Stefan Roese | d07117e | 2007-02-20 10:27:08 +0100 | [diff] [blame] | 228 | /* Clear Stop Complete Bit */ |
Stefan Roese | 77c1f1d | 2009-11-19 14:03:17 +0100 | [diff] [blame] | 229 | out_8(&i2c->sts, IIC_STS_SCMP); |
| 230 | |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 231 | /* Check init */ |
Stefan Roese | d07117e | 2007-02-20 10:27:08 +0100 | [diff] [blame] | 232 | i = 10; |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 233 | do { |
| 234 | /* Get status */ |
Stefan Roese | 77c1f1d | 2009-11-19 14:03:17 +0100 | [diff] [blame] | 235 | status = in_8(&i2c->sts); |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 236 | i--; |
Stefan Roese | d07117e | 2007-02-20 10:27:08 +0100 | [diff] [blame] | 237 | } while ((status & IIC_STS_PT) && (i > 0)); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 238 | |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 239 | if (status & IIC_STS_PT) { |
| 240 | result = IIC_NOK_TOUT; |
| 241 | return(result); |
| 242 | } |
Stefan Roese | 77c1f1d | 2009-11-19 14:03:17 +0100 | [diff] [blame] | 243 | |
Stefan Roese | d07117e | 2007-02-20 10:27:08 +0100 | [diff] [blame] | 244 | /* flush the Master/Slave Databuffers */ |
Stefan Roese | 77c1f1d | 2009-11-19 14:03:17 +0100 | [diff] [blame] | 245 | out_8(&i2c->mdcntl, in_8(&i2c->mdcntl) | |
| 246 | IIC_MDCNTL_FMDB | IIC_MDCNTL_FSDB); |
| 247 | |
Stefan Roese | d07117e | 2007-02-20 10:27:08 +0100 | [diff] [blame] | 248 | /* need to wait 4 OPB clocks? code below should take that long */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 249 | |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 250 | /* 7-bit adressing */ |
Stefan Roese | 77c1f1d | 2009-11-19 14:03:17 +0100 | [diff] [blame] | 251 | out_8(&i2c->hmadr, 0); |
| 252 | out_8(&i2c->lmadr, chip); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 253 | |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 254 | tran = 0; |
| 255 | result = IIC_OK; |
| 256 | creg = 0; |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 257 | |
Stefan Roese | d07117e | 2007-02-20 10:27:08 +0100 | [diff] [blame] | 258 | while (tran != cnt && (result == IIC_OK)) { |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 259 | int bc,j; |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 260 | |
Stefan Roese | 77c1f1d | 2009-11-19 14:03:17 +0100 | [diff] [blame] | 261 | /* |
| 262 | * Control register = |
| 263 | * Normal transfer, 7-bits adressing, Transfer up to |
| 264 | * bc bytes, Normal start, Transfer is a sequence of transfers |
Stefan Roese | d07117e | 2007-02-20 10:27:08 +0100 | [diff] [blame] | 265 | */ |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 266 | creg |= IIC_CNTL_PT; |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 267 | |
Stefan Roese | d07117e | 2007-02-20 10:27:08 +0100 | [diff] [blame] | 268 | bc = (cnt - tran) > 4 ? 4 : cnt - tran; |
| 269 | creg |= (bc - 1) << 4; |
| 270 | /* if the real cmd type is write continue trans */ |
| 271 | if ((!cmd_type && (ptr == addr)) || ((tran + bc) != cnt)) |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 272 | creg |= IIC_CNTL_CHT; |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 273 | |
Stefan Roese | 77c1f1d | 2009-11-19 14:03:17 +0100 | [diff] [blame] | 274 | if (reading) { |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 275 | creg |= IIC_CNTL_READ; |
Stefan Roese | 77c1f1d | 2009-11-19 14:03:17 +0100 | [diff] [blame] | 276 | } else { |
| 277 | for(j = 0; j < bc; j++) { |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 278 | /* Set buffer */ |
Stefan Roese | 77c1f1d | 2009-11-19 14:03:17 +0100 | [diff] [blame] | 279 | out_8(&i2c->mdbuf, ptr[tran + j]); |
| 280 | } |
| 281 | } |
| 282 | out_8(&i2c->cntl, creg); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 283 | |
Stefan Roese | 77c1f1d | 2009-11-19 14:03:17 +0100 | [diff] [blame] | 284 | /* |
| 285 | * Transfer is in progress |
Stefan Roese | d07117e | 2007-02-20 10:27:08 +0100 | [diff] [blame] | 286 | * we have to wait for upto 5 bytes of data |
| 287 | * 1 byte chip address+r/w bit then bc bytes |
| 288 | * of data. |
| 289 | * udelay(10) is 1 bit time at 100khz |
| 290 | * Doubled for slop. 20 is too small. |
| 291 | */ |
Stefan Roese | 77c1f1d | 2009-11-19 14:03:17 +0100 | [diff] [blame] | 292 | i = 2 * 5 * 8; |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 293 | do { |
| 294 | /* Get status */ |
Stefan Roese | 77c1f1d | 2009-11-19 14:03:17 +0100 | [diff] [blame] | 295 | status = in_8(&i2c->sts); |
Stefan Roese | d07117e | 2007-02-20 10:27:08 +0100 | [diff] [blame] | 296 | udelay(10); |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 297 | i--; |
Stefan Roese | 77c1f1d | 2009-11-19 14:03:17 +0100 | [diff] [blame] | 298 | } while ((status & IIC_STS_PT) && !(status & IIC_STS_ERR) && |
| 299 | (i > 0)); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 300 | |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 301 | if (status & IIC_STS_ERR) { |
| 302 | result = IIC_NOK; |
Stefan Roese | 77c1f1d | 2009-11-19 14:03:17 +0100 | [diff] [blame] | 303 | status = in_8(&i2c->extsts); |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 304 | /* Lost arbitration? */ |
| 305 | if (status & IIC_EXTSTS_LA) |
| 306 | result = IIC_NOK_LA; |
| 307 | /* Incomplete transfer? */ |
| 308 | if (status & IIC_EXTSTS_ICT) |
| 309 | result = IIC_NOK_ICT; |
| 310 | /* Transfer aborted? */ |
| 311 | if (status & IIC_EXTSTS_XFRA) |
| 312 | result = IIC_NOK_XFRA; |
| 313 | } else if ( status & IIC_STS_PT) { |
| 314 | result = IIC_NOK_TOUT; |
| 315 | } |
Stefan Roese | 77c1f1d | 2009-11-19 14:03:17 +0100 | [diff] [blame] | 316 | |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 317 | /* Command is reading => get buffer */ |
| 318 | if ((reading) && (result == IIC_OK)) { |
| 319 | /* Are there data in buffer */ |
| 320 | if (status & IIC_STS_MDBS) { |
| 321 | /* |
Stefan Roese | 77c1f1d | 2009-11-19 14:03:17 +0100 | [diff] [blame] | 322 | * even if we have data we have to wait 4OPB |
| 323 | * clocks for it to hit the front of the FIFO, |
| 324 | * after that we can just read. We should check |
| 325 | * XFCNT here and if the FIFO is full there is |
| 326 | * no need to wait. |
Stefan Roese | d07117e | 2007-02-20 10:27:08 +0100 | [diff] [blame] | 327 | */ |
| 328 | udelay(1); |
Stefan Roese | 77c1f1d | 2009-11-19 14:03:17 +0100 | [diff] [blame] | 329 | for (j = 0; j < bc; j++) |
| 330 | ptr[tran + j] = in_8(&i2c->mdbuf); |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 331 | } else |
| 332 | result = IIC_NOK_DATA; |
| 333 | } |
| 334 | creg = 0; |
Stefan Roese | d07117e | 2007-02-20 10:27:08 +0100 | [diff] [blame] | 335 | tran += bc; |
| 336 | if (ptr == addr && tran == cnt) { |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 337 | ptr = data; |
| 338 | cnt = data_len; |
| 339 | tran = 0; |
| 340 | reading = cmd_type; |
Stefan Roese | d07117e | 2007-02-20 10:27:08 +0100 | [diff] [blame] | 341 | if (reading) |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 342 | creg = IIC_CNTL_RPST; |
| 343 | } |
| 344 | } |
Stefan Roese | 77c1f1d | 2009-11-19 14:03:17 +0100 | [diff] [blame] | 345 | return result; |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 346 | } |
| 347 | |
Stefan Roese | d07117e | 2007-02-20 10:27:08 +0100 | [diff] [blame] | 348 | int i2c_probe(uchar chip) |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 349 | { |
| 350 | uchar buf[1]; |
| 351 | |
| 352 | buf[0] = 0; |
| 353 | |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 354 | /* |
| 355 | * What is needed is to send the chip address and verify that the |
| 356 | * address was <ACK>ed (i.e. there was a chip at that address which |
| 357 | * drove the data line low). |
| 358 | */ |
Stefan Roese | 77c1f1d | 2009-11-19 14:03:17 +0100 | [diff] [blame] | 359 | return (i2c_transfer(1, chip << 1, 0, 0, buf, 1) != 0); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 360 | } |
| 361 | |
Stefan Roese | 77c1f1d | 2009-11-19 14:03:17 +0100 | [diff] [blame] | 362 | static int ppc4xx_i2c_transfer(uchar chip, uint addr, int alen, uchar *buffer, |
| 363 | int len, int read) |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 364 | { |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 365 | uchar xaddr[4]; |
| 366 | int ret; |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 367 | |
Stefan Roese | d07117e | 2007-02-20 10:27:08 +0100 | [diff] [blame] | 368 | if (alen > 4) { |
Stefan Roese | 77c1f1d | 2009-11-19 14:03:17 +0100 | [diff] [blame] | 369 | printf("I2C: addr len %d not supported\n", alen); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 370 | return 1; |
| 371 | } |
| 372 | |
Stefan Roese | d07117e | 2007-02-20 10:27:08 +0100 | [diff] [blame] | 373 | if (alen > 0) { |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 374 | xaddr[0] = (addr >> 24) & 0xFF; |
| 375 | xaddr[1] = (addr >> 16) & 0xFF; |
| 376 | xaddr[2] = (addr >> 8) & 0xFF; |
| 377 | xaddr[3] = addr & 0xFF; |
| 378 | } |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 379 | |
| 380 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 381 | #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 382 | /* |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 383 | * EEPROM chips that implement "address overflow" are ones |
| 384 | * like Catalyst 24WC04/08/16 which has 9/10/11 bits of |
| 385 | * address and the extra bits end up in the "chip address" |
| 386 | * bit slots. This makes a 24WC08 (1Kbyte) chip look like |
| 387 | * four 256 byte chips. |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 388 | * |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 389 | * Note that we consider the length of the address field to |
| 390 | * still be one byte because the extra address bits are |
| 391 | * hidden in the chip address. |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 392 | */ |
Stefan Roese | d07117e | 2007-02-20 10:27:08 +0100 | [diff] [blame] | 393 | if (alen > 0) |
Stefan Roese | 77c1f1d | 2009-11-19 14:03:17 +0100 | [diff] [blame] | 394 | chip |= ((addr >> (alen * 8)) & |
| 395 | CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 396 | #endif |
Stefan Roese | 77c1f1d | 2009-11-19 14:03:17 +0100 | [diff] [blame] | 397 | if ((ret = i2c_transfer(read, chip << 1, &xaddr[4 - alen], alen, |
| 398 | buffer, len)) != 0) { |
Graeme Russ | 70600b0 | 2011-08-29 02:14:05 +0000 | [diff] [blame] | 399 | printf("I2C %s: failed %d\n", read ? "read" : "write", ret); |
Stefan Roese | 77c1f1d | 2009-11-19 14:03:17 +0100 | [diff] [blame] | 400 | |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 401 | return 1; |
| 402 | } |
Stefan Roese | 77c1f1d | 2009-11-19 14:03:17 +0100 | [diff] [blame] | 403 | |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 404 | return 0; |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 405 | } |
| 406 | |
Stefan Roese | 77c1f1d | 2009-11-19 14:03:17 +0100 | [diff] [blame] | 407 | int i2c_read(uchar chip, uint addr, int alen, uchar * buffer, int len) |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 408 | { |
Stefan Roese | 77c1f1d | 2009-11-19 14:03:17 +0100 | [diff] [blame] | 409 | return ppc4xx_i2c_transfer(chip, addr, alen, buffer, len, 1); |
| 410 | } |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 411 | |
Stefan Roese | 77c1f1d | 2009-11-19 14:03:17 +0100 | [diff] [blame] | 412 | int i2c_write(uchar chip, uint addr, int alen, uchar * buffer, int len) |
| 413 | { |
| 414 | return ppc4xx_i2c_transfer(chip, addr, alen, buffer, len, 0); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 415 | } |
| 416 | |
Stefan Roese | d07117e | 2007-02-20 10:27:08 +0100 | [diff] [blame] | 417 | #if defined(CONFIG_I2C_MULTI_BUS) |
| 418 | /* |
| 419 | * Functions for multiple I2C bus handling |
| 420 | */ |
| 421 | unsigned int i2c_get_bus_num(void) |
| 422 | { |
| 423 | return i2c_bus_num; |
| 424 | } |
| 425 | |
| 426 | int i2c_set_bus_num(unsigned int bus) |
| 427 | { |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 428 | if (bus >= CONFIG_SYS_MAX_I2C_BUS) |
Stefan Roese | d07117e | 2007-02-20 10:27:08 +0100 | [diff] [blame] | 429 | return -1; |
| 430 | |
| 431 | i2c_bus_num = bus; |
| 432 | |
| 433 | return 0; |
| 434 | } |
Matthias Fuchs | 62f0704 | 2007-03-08 16:23:11 +0100 | [diff] [blame] | 435 | #endif /* CONFIG_I2C_MULTI_BUS */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 436 | #endif /* CONFIG_HARD_I2C */ |