Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 2 | /* |
| 3 | * WindRiver SBC8349 U-Boot configuration file. |
| 4 | * Copyright (c) 2006, 2007 Wind River Systems, Inc. |
| 5 | * |
| 6 | * Paul Gortmaker <paul.gortmaker@windriver.com> |
| 7 | * Based on the MPC8349EMDS config. |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 8 | */ |
| 9 | |
| 10 | /* |
| 11 | * sbc8349 board configuration file. |
| 12 | */ |
| 13 | |
| 14 | #ifndef __CONFIG_H |
| 15 | #define __CONFIG_H |
| 16 | |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 17 | /* |
| 18 | * High Level Configuration Options |
| 19 | */ |
| 20 | #define CONFIG_E300 1 /* E300 Family */ |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 21 | |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 22 | /* Don't enable PCI2 on sbc834x - it doesn't exist physically. */ |
| 23 | #undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */ |
| 24 | |
Joe Hershberger | 10c2617 | 2011-10-11 23:57:25 -0500 | [diff] [blame] | 25 | #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 26 | |
| 27 | /* |
| 28 | * DDR Setup |
| 29 | */ |
| 30 | #undef CONFIG_DDR_ECC /* only for ECC DDR module */ |
| 31 | #undef CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ |
| 32 | #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ |
Joe Hershberger | 10c2617 | 2011-10-11 23:57:25 -0500 | [diff] [blame] | 33 | #define CONFIG_SYS_83XX_DDR_USES_CS0 /* WRS; Fsl board uses CS2/CS3 */ |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 34 | |
| 35 | /* |
| 36 | * 32-bit data path mode. |
| 37 | * |
| 38 | * Please note that using this mode for devices with the real density of 64-bit |
| 39 | * effectively reduces the amount of available memory due to the effect of |
| 40 | * wrapping around while translating address to row/columns, for example in the |
| 41 | * 256MB module the upper 128MB get aliased with contents of the lower |
| 42 | * 128MB); normally this define should be used for devices with real 32-bit |
| 43 | * data path. |
| 44 | */ |
| 45 | #undef CONFIG_DDR_32BIT |
| 46 | |
Mario Six | c9f9277 | 2019-01-21 09:18:15 +0100 | [diff] [blame] | 47 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 48 | #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 49 | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) |
| 50 | #define CONFIG_DDR_2T_TIMING |
| 51 | |
| 52 | #if defined(CONFIG_SPD_EEPROM) |
| 53 | /* |
| 54 | * Determine DDR configuration from I2C interface. |
| 55 | */ |
| 56 | #define SPD_EEPROM_ADDRESS 0x52 /* DDR DIMM */ |
| 57 | |
| 58 | #else |
| 59 | /* |
| 60 | * Manually set up DDR parameters |
| 61 | * NB: manual DDR setup untested on sbc834x |
| 62 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 63 | #define CONFIG_SYS_DDR_SIZE 256 /* MB */ |
Joe Hershberger | 5ade390 | 2011-10-11 23:57:31 -0500 | [diff] [blame] | 64 | #define CONFIG_SYS_DDR_CS2_CONFIG (CSCONFIG_EN \ |
Joe Hershberger | 10c2617 | 2011-10-11 23:57:25 -0500 | [diff] [blame] | 65 | | CSCONFIG_ROW_BIT_13 \ |
| 66 | | CSCONFIG_COL_BIT_10) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 67 | #define CONFIG_SYS_DDR_TIMING_1 0x36332321 |
| 68 | #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ |
Joe Hershberger | 10c2617 | 2011-10-11 23:57:25 -0500 | [diff] [blame] | 69 | #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 70 | #define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */ |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 71 | |
| 72 | #if defined(CONFIG_DDR_32BIT) |
| 73 | /* set burst length to 8 for 32-bit data path */ |
Joe Hershberger | 10c2617 | 2011-10-11 23:57:25 -0500 | [diff] [blame] | 74 | /* DLL,normal,seq,4/2.5, 8 burst len */ |
| 75 | #define CONFIG_SYS_DDR_MODE 0x00000023 |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 76 | #else |
| 77 | /* the default burst length is 4 - for 64-bit data path */ |
Joe Hershberger | 10c2617 | 2011-10-11 23:57:25 -0500 | [diff] [blame] | 78 | /* DLL,normal,seq,4/2.5, 4 burst len */ |
| 79 | #define CONFIG_SYS_DDR_MODE 0x00000022 |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 80 | #endif |
| 81 | #endif |
| 82 | |
| 83 | /* |
| 84 | * SDRAM on the Local Bus |
| 85 | */ |
Joe Hershberger | f05b933 | 2011-10-11 23:57:30 -0500 | [diff] [blame] | 86 | #define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */ |
| 87 | #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 88 | |
| 89 | /* |
| 90 | * FLASH on the Local Bus |
| 91 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 92 | #define CONFIG_SYS_FLASH_BASE 0xFF800000 /* start of FLASH */ |
| 93 | #define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */ |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 94 | |
Joe Hershberger | f05b933 | 2011-10-11 23:57:30 -0500 | [diff] [blame] | 95 | |
Joe Hershberger | 10c2617 | 2011-10-11 23:57:25 -0500 | [diff] [blame] | 96 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ |
| 97 | #define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */ |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 98 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 99 | #undef CONFIG_SYS_FLASH_CHECKSUM |
| 100 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ |
| 101 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 102 | |
Wolfgang Denk | 0708bc6 | 2010-10-07 21:51:12 +0200 | [diff] [blame] | 103 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 104 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 105 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
| 106 | #define CONFIG_SYS_RAMBOOT |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 107 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 108 | #undef CONFIG_SYS_RAMBOOT |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 109 | #endif |
| 110 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 111 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
Joe Hershberger | 10c2617 | 2011-10-11 23:57:25 -0500 | [diff] [blame] | 112 | /* Initial RAM address */ |
| 113 | #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 |
| 114 | /* Size of used area in RAM*/ |
| 115 | #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 116 | |
Joe Hershberger | 10c2617 | 2011-10-11 23:57:25 -0500 | [diff] [blame] | 117 | #define CONFIG_SYS_GBL_DATA_OFFSET \ |
| 118 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 119 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 120 | |
Joe Hershberger | 10c2617 | 2011-10-11 23:57:25 -0500 | [diff] [blame] | 121 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
Kim Phillips | 831d2f6 | 2012-06-30 18:29:20 -0500 | [diff] [blame] | 122 | #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 123 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 124 | #undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */ |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 125 | |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 126 | /* |
| 127 | * Serial Port |
| 128 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 129 | #define CONFIG_SYS_NS16550_SERIAL |
| 130 | #define CONFIG_SYS_NS16550_REG_SIZE 1 |
| 131 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 132 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 133 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
Joe Hershberger | 10c2617 | 2011-10-11 23:57:25 -0500 | [diff] [blame] | 134 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 135 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 136 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) |
| 137 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 138 | |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 139 | /* I2C */ |
Heiko Schocher | f285074 | 2012-10-24 13:48:22 +0200 | [diff] [blame] | 140 | #define CONFIG_SYS_I2C |
| 141 | #define CONFIG_SYS_I2C_FSL |
| 142 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 |
| 143 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F |
| 144 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 |
| 145 | #define CONFIG_SYS_FSL_I2C2_SPEED 400000 |
| 146 | #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F |
| 147 | #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 |
| 148 | #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69}, {1, 0x69} } |
Paul Gortmaker | 04684f7 | 2009-10-02 18:54:20 -0400 | [diff] [blame] | 149 | /* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */ |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 150 | |
| 151 | /* TSEC */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 152 | #define CONFIG_SYS_TSEC1_OFFSET 0x24000 |
Joe Hershberger | 10c2617 | 2011-10-11 23:57:25 -0500 | [diff] [blame] | 153 | #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 154 | #define CONFIG_SYS_TSEC2_OFFSET 0x25000 |
Joe Hershberger | 10c2617 | 2011-10-11 23:57:25 -0500 | [diff] [blame] | 155 | #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 156 | |
| 157 | /* |
| 158 | * General PCI |
| 159 | * Addresses are mapped 1-1. |
| 160 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 161 | #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 |
| 162 | #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE |
| 163 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ |
| 164 | #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 |
| 165 | #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE |
| 166 | #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ |
Joe Hershberger | 10c2617 | 2011-10-11 23:57:25 -0500 | [diff] [blame] | 167 | #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 |
| 168 | #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 |
| 169 | #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 170 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 171 | #define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000 |
| 172 | #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE |
| 173 | #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ |
| 174 | #define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000 |
| 175 | #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE |
| 176 | #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ |
Joe Hershberger | 10c2617 | 2011-10-11 23:57:25 -0500 | [diff] [blame] | 177 | #define CONFIG_SYS_PCI2_IO_BASE 0x00000000 |
| 178 | #define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000 |
| 179 | #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 180 | |
| 181 | #if defined(CONFIG_PCI) |
| 182 | |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 183 | #undef CONFIG_TULIP |
| 184 | |
| 185 | #if !defined(CONFIG_PCI_PNP) |
| 186 | #define PCI_ENET0_IOADDR 0xFIXME |
| 187 | #define PCI_ENET0_MEMADDR 0xFIXME |
| 188 | #define PCI_IDSEL_NUMBER 0xFIXME |
| 189 | #endif |
| 190 | |
| 191 | #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 192 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 193 | |
| 194 | #endif /* CONFIG_PCI */ |
| 195 | |
| 196 | /* |
| 197 | * TSEC configuration |
| 198 | */ |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 199 | |
| 200 | #if defined(CONFIG_TSEC_ENET) |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 201 | |
Kim Phillips | 177e58f | 2007-05-16 16:52:19 -0500 | [diff] [blame] | 202 | #define CONFIG_TSEC1 1 |
| 203 | #define CONFIG_TSEC1_NAME "TSEC0" |
| 204 | #define CONFIG_TSEC2 1 |
| 205 | #define CONFIG_TSEC2_NAME "TSEC1" |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 206 | #define CONFIG_PHY_BCM5421S 1 |
| 207 | #define TSEC1_PHY_ADDR 0x19 |
| 208 | #define TSEC2_PHY_ADDR 0x1a |
| 209 | #define TSEC1_PHYIDX 0 |
| 210 | #define TSEC2_PHYIDX 0 |
Andy Fleming | 09b88df | 2007-08-15 20:03:25 -0500 | [diff] [blame] | 211 | #define TSEC1_FLAGS TSEC_GIGABIT |
| 212 | #define TSEC2_FLAGS TSEC_GIGABIT |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 213 | |
| 214 | /* Options are: TSEC[0-1] */ |
| 215 | #define CONFIG_ETHPRIME "TSEC0" |
| 216 | |
| 217 | #endif /* CONFIG_TSEC_ENET */ |
| 218 | |
| 219 | /* |
| 220 | * Environment |
| 221 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 222 | #ifndef CONFIG_SYS_RAMBOOT |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 223 | /* Address and size of Redundant Environment Sector */ |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 224 | #endif |
| 225 | |
| 226 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 227 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 228 | |
Jon Loeliger | 1f166a2 | 2007-07-04 22:30:58 -0500 | [diff] [blame] | 229 | /* |
Jon Loeliger | 5c4ddae | 2007-07-10 10:12:10 -0500 | [diff] [blame] | 230 | * BOOTP options |
| 231 | */ |
| 232 | #define CONFIG_BOOTP_BOOTFILESIZE |
Jon Loeliger | 5c4ddae | 2007-07-10 10:12:10 -0500 | [diff] [blame] | 233 | |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 234 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
| 235 | |
| 236 | /* |
| 237 | * Miscellaneous configurable options |
| 238 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 239 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 240 | |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 241 | /* |
| 242 | * For booting Linux, the board info and command line data |
Ira W. Snyder | c5a22d0 | 2010-09-10 15:42:32 -0700 | [diff] [blame] | 243 | * have to be in the first 256 MB of memory, since this is |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 244 | * the maximum mapped by the Linux kernel during initialization. |
| 245 | */ |
Joe Hershberger | 10c2617 | 2011-10-11 23:57:25 -0500 | [diff] [blame] | 246 | /* Initial Memory map for Linux*/ |
| 247 | #define CONFIG_SYS_BOOTMAPSZ (256 << 20) |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 248 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 249 | #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 250 | |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 251 | /* System IO Config */ |
Kim Phillips | f91cad6 | 2009-06-05 14:11:33 -0500 | [diff] [blame] | 252 | #define CONFIG_SYS_SICRH 0 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 253 | #define CONFIG_SYS_SICRL SICRL_LDP_A |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 254 | |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 255 | #ifdef CONFIG_PCI |
Gabor Juhos | b445873 | 2013-05-30 07:06:12 +0000 | [diff] [blame] | 256 | #define CONFIG_PCI_INDIRECT_BRIDGE |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 257 | #endif |
| 258 | |
Jon Loeliger | 1f166a2 | 2007-07-04 22:30:58 -0500 | [diff] [blame] | 259 | #if defined(CONFIG_CMD_KGDB) |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 260 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 261 | #endif |
| 262 | |
| 263 | /* |
| 264 | * Environment Configuration |
| 265 | */ |
| 266 | #define CONFIG_ENV_OVERWRITE |
| 267 | |
| 268 | #if defined(CONFIG_TSEC_ENET) |
Andy Fleming | 458c389 | 2007-08-16 16:35:02 -0500 | [diff] [blame] | 269 | #define CONFIG_HAS_ETH0 |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 270 | #define CONFIG_HAS_ETH1 |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 271 | #endif |
| 272 | |
Mario Six | 790d844 | 2018-03-28 14:38:20 +0200 | [diff] [blame] | 273 | #define CONFIG_HOSTNAME "SBC8349" |
Joe Hershberger | 257ff78 | 2011-10-13 13:03:47 +0000 | [diff] [blame] | 274 | #define CONFIG_ROOTPATH "/tftpboot/rootfs" |
Joe Hershberger | e4da248 | 2011-10-13 13:03:48 +0000 | [diff] [blame] | 275 | #define CONFIG_BOOTFILE "uImage" |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 276 | |
Joe Hershberger | 10c2617 | 2011-10-11 23:57:25 -0500 | [diff] [blame] | 277 | /* default location for tftp and bootm */ |
| 278 | #define CONFIG_LOADADDR 800000 |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 279 | |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 280 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 281 | "netdev=eth0\0" \ |
Detlev Zundel | 027fa49 | 2008-04-18 14:50:01 +0200 | [diff] [blame] | 282 | "hostname=sbc8349\0" \ |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 283 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ |
| 284 | "nfsroot=${serverip}:${rootpath}\0" \ |
| 285 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ |
| 286 | "addip=setenv bootargs ${bootargs} " \ |
| 287 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ |
| 288 | ":${hostname}:${netdev}:off panic=1\0" \ |
| 289 | "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ |
| 290 | "flash_nfs=run nfsargs addip addtty;" \ |
| 291 | "bootm ${kernel_addr}\0" \ |
| 292 | "flash_self=run ramargs addip addtty;" \ |
| 293 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ |
| 294 | "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ |
| 295 | "bootm\0" \ |
| 296 | "load=tftp 100000 /tftpboot/sbc8349/u-boot.bin\0" \ |
Paul Gortmaker | 80b4bb7 | 2009-07-23 17:10:55 -0400 | [diff] [blame] | 297 | "update=protect off ff800000 ff83ffff; " \ |
Joe Hershberger | 10c2617 | 2011-10-11 23:57:25 -0500 | [diff] [blame] | 298 | "era ff800000 ff83ffff; cp.b 100000 ff800000 ${filesize}\0" \ |
Detlev Zundel | 406e578 | 2008-03-06 16:45:53 +0100 | [diff] [blame] | 299 | "upd=run load update\0" \ |
Kim Phillips | fd3a3fc | 2009-08-21 16:34:38 -0500 | [diff] [blame] | 300 | "fdtaddr=780000\0" \ |
Detlev Zundel | 027fa49 | 2008-04-18 14:50:01 +0200 | [diff] [blame] | 301 | "fdtfile=sbc8349.dtb\0" \ |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 302 | "" |
| 303 | |
Joe Hershberger | 10c2617 | 2011-10-11 23:57:25 -0500 | [diff] [blame] | 304 | #define CONFIG_NFSBOOTCOMMAND \ |
| 305 | "setenv bootargs root=/dev/nfs rw " \ |
| 306 | "nfsroot=$serverip:$rootpath " \ |
| 307 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ |
| 308 | "$netdev:off " \ |
| 309 | "console=$consoledev,$baudrate $othbootargs;" \ |
| 310 | "tftp $loadaddr $bootfile;" \ |
| 311 | "tftp $fdtaddr $fdtfile;" \ |
| 312 | "bootm $loadaddr - $fdtaddr" |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 313 | |
| 314 | #define CONFIG_RAMBOOTCOMMAND \ |
Joe Hershberger | 10c2617 | 2011-10-11 23:57:25 -0500 | [diff] [blame] | 315 | "setenv bootargs root=/dev/ram rw " \ |
| 316 | "console=$consoledev,$baudrate $othbootargs;" \ |
| 317 | "tftp $ramdiskaddr $ramdiskfile;" \ |
| 318 | "tftp $loadaddr $bootfile;" \ |
| 319 | "tftp $fdtaddr $fdtfile;" \ |
| 320 | "bootm $loadaddr $ramdiskaddr $fdtaddr" |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 321 | |
| 322 | #define CONFIG_BOOTCOMMAND "run flash_self" |
| 323 | |
| 324 | #endif /* __CONFIG_H */ |