blob: fe26ced31dcdd5bb42284426ab1d4e7de62696a7 [file] [log] [blame]
Simon Glassb2c1cac2014-02-26 15:59:21 -07001/dts-v1/;
2
Patrick Delaunay23aee612020-01-13 11:35:13 +01003#include <dt-bindings/gpio/gpio.h>
4#include <dt-bindings/gpio/sandbox-gpio.h>
Marek Szyprowskiad398592021-02-18 11:33:18 +01005#include <dt-bindings/input/input.h>
Sean Anderson3438e3b2020-09-14 11:01:57 -04006#include <dt-bindings/pinctrl/sandbox-pinmux.h>
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +05307#include <dt-bindings/mux/mux.h>
Patrick Delaunay23aee612020-01-13 11:35:13 +01008
Simon Glassb2c1cac2014-02-26 15:59:21 -07009/ {
10 model = "sandbox";
11 compatible = "sandbox";
12 #address-cells = <1>;
Simon Glasscf61f742015-07-06 12:54:36 -060013 #size-cells = <1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -070014
Simon Glassfef72b72014-07-23 06:55:03 -060015 aliases {
16 console = &uart0;
Simon Glass5b968632015-05-22 15:42:15 -060017 eth0 = "/eth@10002000";
Claudiu Manoild9eaa922021-03-14 20:14:57 +080018 eth2 = &swp_0;
Bin Meng04a11cb2015-08-27 22:25:53 -070019 eth3 = &eth_3;
Claudiu Manoild9eaa922021-03-14 20:14:57 +080020 eth4 = &dsa_eth0;
Simon Glass5b968632015-05-22 15:42:15 -060021 eth5 = &eth_5;
Simon Glass5620cf82018-10-01 12:22:40 -060022 gpio1 = &gpio_a;
23 gpio2 = &gpio_b;
Patrick Delaunay28bdaa52020-01-13 11:35:14 +010024 gpio3 = &gpio_c;
Simon Glass0ccb0972015-01-25 08:27:05 -070025 i2c0 = "/i2c@0";
Simon Glasse4fef742017-04-23 20:02:07 -060026 mmc0 = "/mmc0";
27 mmc1 = "/mmc1";
Bin Meng408e5902018-08-03 01:14:41 -070028 pci0 = &pci0;
29 pci1 = &pci1;
Bin Meng510dddb2018-08-03 01:14:50 -070030 pci2 = &pci2;
Michael Walle7c41a222020-06-02 01:47:09 +020031 remoteproc0 = &rproc_1;
32 remoteproc1 = &rproc_2;
Simon Glass336b2952015-05-22 15:42:17 -060033 rtc0 = &rtc_0;
34 rtc1 = &rtc_1;
Simon Glass5b968632015-05-22 15:42:15 -060035 spi0 = "/spi@0";
Przemyslaw Marczak3dbb55e2015-05-13 13:38:34 +020036 testfdt6 = "/e-test";
Simon Glass0ccb0972015-01-25 08:27:05 -070037 testbus3 = "/some-bus";
38 testfdt0 = "/some-bus/c-test@0";
Simon Glass7d5e4112020-12-16 21:20:26 -070039 testfdt12 = "/some-bus/c-test@1";
Simon Glass0ccb0972015-01-25 08:27:05 -070040 testfdt3 = "/b-test";
41 testfdt5 = "/some-bus/c-test@5";
42 testfdt8 = "/a-test";
Simon Glass791a17f2020-12-16 21:20:27 -070043 testfdtm1 = &testfdtm1;
Eugeniu Rosca5ba71e52018-05-19 14:13:55 +020044 fdt-dummy0 = "/translation-test@8000/dev@0,0";
45 fdt-dummy1 = "/translation-test@8000/dev@1,100";
46 fdt-dummy2 = "/translation-test@8000/dev@2,200";
47 fdt-dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
Dario Binacchib574d682020-12-30 00:16:21 +010048 fdt-dummy4 = "/translation-test@8000/xlatebus@4,400/devs/dev@19";
Simon Glass31680482015-03-25 12:23:05 -060049 usb0 = &usb_0;
50 usb1 = &usb_1;
51 usb2 = &usb_2;
Mario Six95922152018-08-09 14:51:19 +020052 axi0 = &axi;
Mario Six02ad6fb2018-09-27 09:19:31 +020053 osd0 = "/osd";
Simon Glassfef72b72014-07-23 06:55:03 -060054 };
55
Rasmus Villemoes30d4d2b2021-04-21 11:06:55 +020056 config {
57 environment {
58 from_fdt = "yes";
59 fdt_env_path = "";
60 };
61 };
62
Simon Glassed96cde2018-12-10 10:37:33 -070063 audio: audio-codec {
64 compatible = "sandbox,audio-codec";
65 #sound-dai-cells = <1>;
66 };
67
Philippe Reynes1ee26482020-07-24 18:19:51 +020068 buttons {
69 compatible = "gpio-keys";
70
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +020071 btn1 {
Philippe Reynes1ee26482020-07-24 18:19:51 +020072 gpios = <&gpio_a 3 0>;
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +020073 label = "button1";
Philippe Reynes1ee26482020-07-24 18:19:51 +020074 };
75
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +020076 btn2 {
Philippe Reynes1ee26482020-07-24 18:19:51 +020077 gpios = <&gpio_a 4 0>;
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +020078 label = "button2";
Philippe Reynes1ee26482020-07-24 18:19:51 +020079 };
80 };
81
Marek Szyprowskiad398592021-02-18 11:33:18 +010082 buttons2 {
83 compatible = "adc-keys";
84 io-channels = <&adc 3>;
85 keyup-threshold-microvolt = <3000000>;
86
87 button-up {
88 label = "button3";
89 linux,code = <KEY_F3>;
90 press-threshold-microvolt = <1500000>;
91 };
92
93 button-down {
94 label = "button4";
95 linux,code = <KEY_F4>;
96 press-threshold-microvolt = <1000000>;
97 };
98
99 button-enter {
100 label = "button5";
101 linux,code = <KEY_F5>;
102 press-threshold-microvolt = <500000>;
103 };
104 };
105
Simon Glassc953aaf2018-12-10 10:37:34 -0700106 cros_ec: cros-ec {
Simon Glass699c9ca2018-10-01 12:22:08 -0600107 reg = <0 0>;
108 compatible = "google,cros-ec-sandbox";
109
110 /*
111 * This describes the flash memory within the EC. Note
112 * that the STM32L flash erases to 0, not 0xff.
113 */
114 flash {
115 image-pos = <0x08000000>;
116 size = <0x20000>;
117 erase-value = <0>;
118
119 /* Information for sandbox */
120 ro {
121 image-pos = <0>;
122 size = <0xf000>;
123 };
124 wp-ro {
125 image-pos = <0xf000>;
126 size = <0x1000>;
Simon Glassbf0a6922021-01-21 13:57:14 -0700127 used = <0x884>;
128 compress = "lz4";
129 uncomp-size = <0xcf8>;
130 hash {
131 algo = "sha256";
132 value = [00 01 02 03 04 05 06 07
133 08 09 0a 0b 0c 0d 0e 0f
134 10 11 12 13 14 15 16 17
135 18 19 1a 1b 1c 1d 1e 1f];
136 };
Simon Glass699c9ca2018-10-01 12:22:08 -0600137 };
138 rw {
139 image-pos = <0x10000>;
140 size = <0x10000>;
141 };
142 };
143 };
144
Yannick Fertré9712c822019-10-07 15:29:05 +0200145 dsi_host: dsi_host {
146 compatible = "sandbox,dsi-host";
147 };
148
Simon Glassb2c1cac2014-02-26 15:59:21 -0700149 a-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600150 reg = <0 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700151 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600152 ping-expect = <0>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700153 ping-add = <0>;
Simon Glassfef72b72014-07-23 06:55:03 -0600154 u-boot,dm-pre-reloc;
Patrick Delaunay23aee612020-01-13 11:35:13 +0100155 test-gpios = <&gpio_a 1>, <&gpio_a 4>,
156 <&gpio_b 5 GPIO_ACTIVE_HIGH 3 2 1>,
Simon Glass16e10402015-01-05 20:05:29 -0700157 <0>, <&gpio_a 12>;
Patrick Delaunay23aee612020-01-13 11:35:13 +0100158 test2-gpios = <&gpio_a 1>, <&gpio_a 4>,
159 <&gpio_b 6 GPIO_ACTIVE_LOW 3 2 1>,
160 <&gpio_b 7 GPIO_IN 3 2 1>,
161 <&gpio_b 8 GPIO_OUT 3 2 1>,
162 <&gpio_b 9 (GPIO_OUT|GPIO_OUT_ACTIVE) 3 2 1>;
Patrick Delaunay28bdaa52020-01-13 11:35:14 +0100163 test3-gpios =
164 <&gpio_c 0 (GPIO_OUT|GPIO_OPEN_DRAIN)>,
165 <&gpio_c 1 (GPIO_OUT|GPIO_OPEN_SOURCE)>,
166 <&gpio_c 2 GPIO_OUT>,
167 <&gpio_c 3 (GPIO_IN|GPIO_PULL_UP)>,
168 <&gpio_c 4 (GPIO_IN|GPIO_PULL_DOWN)>,
Neil Armstrong643778b2020-05-05 10:43:18 +0200169 <&gpio_c 5 GPIO_IN>,
170 <&gpio_c 6 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_DRAIN)>,
171 <&gpio_c 7 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_SOURCE)>;
Jean-Jacques Hiblot73873402020-09-11 13:43:35 +0530172 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
173 test5-gpios = <&gpio_a 19>;
174
Simon Glass6df01f92018-12-10 10:37:37 -0700175 int-value = <1234>;
176 uint-value = <(-1234)>;
Dario Binacchi421e81e2020-03-29 18:04:40 +0200177 int64-value = /bits/ 64 <0x1111222233334444>;
Dario Binacchi81d80b52020-03-29 18:04:41 +0200178 int-array = <5678 9123 4567>;
Simon Glassdd0ed902020-07-07 13:11:58 -0600179 str-value = "test string";
Simon Glass515dcff2020-02-06 09:55:00 -0700180 interrupts-extended = <&irq 3 0>;
Simon Glass09642392020-07-07 13:12:11 -0600181 acpi,name = "GHIJ";
Patrick Delaunay8cd28012020-09-25 09:41:16 +0200182 phandle-value = <&gpio_c 10>, <0xFFFFFFFF 20>, <&gpio_a 30>;
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +0530183
184 mux-controls = <&muxcontroller0 0>, <&muxcontroller0 1>,
185 <&muxcontroller0 2>, <&muxcontroller0 3>,
186 <&muxcontroller1>;
187 mux-control-names = "mux0", "mux1", "mux2", "mux3", "mux4";
188 mux-syscon = <&syscon3>;
Dario Binacchi836cc9d2020-12-30 00:16:26 +0100189 display-timings {
190 timing0: 240x320 {
191 clock-frequency = <6500000>;
192 hactive = <240>;
193 vactive = <320>;
194 hfront-porch = <6>;
195 hback-porch = <7>;
196 hsync-len = <1>;
197 vback-porch = <5>;
198 vfront-porch = <8>;
199 vsync-len = <2>;
200 hsync-active = <1>;
201 vsync-active = <0>;
202 de-active = <1>;
203 pixelclk-active = <1>;
204 interlaced;
205 doublescan;
206 doubleclk;
207 };
208 timing1: 480x800 {
209 clock-frequency = <9000000>;
210 hactive = <480>;
211 vactive = <800>;
212 hfront-porch = <10>;
213 hback-porch = <59>;
214 hsync-len = <12>;
215 vback-porch = <15>;
216 vfront-porch = <17>;
217 vsync-len = <16>;
218 hsync-active = <0>;
219 vsync-active = <1>;
220 de-active = <0>;
221 pixelclk-active = <0>;
222 };
223 timing2: 800x480 {
224 clock-frequency = <33500000>;
225 hactive = <800>;
226 vactive = <480>;
227 hback-porch = <89>;
228 hfront-porch = <164>;
229 vback-porch = <23>;
230 vfront-porch = <10>;
231 hsync-len = <11>;
232 vsync-len = <13>;
233 };
234 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700235 };
236
237 junk {
Simon Glasscf61f742015-07-06 12:54:36 -0600238 reg = <1 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700239 compatible = "not,compatible";
240 };
241
242 no-compatible {
Simon Glasscf61f742015-07-06 12:54:36 -0600243 reg = <2 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700244 };
245
Simon Glass5620cf82018-10-01 12:22:40 -0600246 backlight: backlight {
247 compatible = "pwm-backlight";
248 enable-gpios = <&gpio_a 1>;
249 power-supply = <&ldo_1>;
250 pwms = <&pwm 0 1000>;
251 default-brightness-level = <5>;
252 brightness-levels = <0 16 32 64 128 170 202 234 255>;
253 };
254
Jean-Jacques Hiblote83a31b2018-08-09 16:17:46 +0200255 bind-test {
Patrice Chotard7b7f9392020-07-28 09:13:33 +0200256 compatible = "simple-bus";
Jean-Jacques Hiblote83a31b2018-08-09 16:17:46 +0200257 bind-test-child1 {
258 compatible = "sandbox,phy";
259 #phy-cells = <1>;
260 };
261
262 bind-test-child2 {
263 compatible = "simple-bus";
264 };
265 };
266
Simon Glassb2c1cac2014-02-26 15:59:21 -0700267 b-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600268 reg = <3 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700269 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600270 ping-expect = <3>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700271 ping-add = <3>;
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +0530272
273 mux-controls = <&muxcontroller0 0>;
274 mux-control-names = "mux0";
Simon Glassb2c1cac2014-02-26 15:59:21 -0700275 };
276
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200277 phy_provider0: gen_phy@0 {
278 compatible = "sandbox,phy";
279 #phy-cells = <1>;
280 };
281
282 phy_provider1: gen_phy@1 {
283 compatible = "sandbox,phy";
284 #phy-cells = <0>;
285 broken;
286 };
287
developer71092972020-05-02 11:35:12 +0200288 phy_provider2: gen_phy@2 {
289 compatible = "sandbox,phy";
290 #phy-cells = <0>;
291 };
292
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200293 gen_phy_user: gen_phy_user {
294 compatible = "simple-bus";
295 phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>;
296 phy-names = "phy1", "phy2", "phy3";
297 };
298
developer71092972020-05-02 11:35:12 +0200299 gen_phy_user1: gen_phy_user1 {
300 compatible = "simple-bus";
301 phys = <&phy_provider0 0>, <&phy_provider2>;
302 phy-names = "phy1", "phy2";
303 };
304
Simon Glassb2c1cac2014-02-26 15:59:21 -0700305 some-bus {
306 #address-cells = <1>;
307 #size-cells = <0>;
Simon Glass40717422014-07-23 06:55:18 -0600308 compatible = "denx,u-boot-test-bus";
Simon Glasscf61f742015-07-06 12:54:36 -0600309 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600310 ping-expect = <4>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700311 ping-add = <4>;
Simon Glass40717422014-07-23 06:55:18 -0600312 c-test@5 {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700313 compatible = "denx,u-boot-fdt-test";
314 reg = <5>;
Simon Glass40717422014-07-23 06:55:18 -0600315 ping-expect = <5>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700316 ping-add = <5>;
317 };
Simon Glass40717422014-07-23 06:55:18 -0600318 c-test@0 {
319 compatible = "denx,u-boot-fdt-test";
320 reg = <0>;
321 ping-expect = <6>;
322 ping-add = <6>;
323 };
324 c-test@1 {
325 compatible = "denx,u-boot-fdt-test";
326 reg = <1>;
327 ping-expect = <7>;
328 ping-add = <7>;
329 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700330 };
331
332 d-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600333 reg = <3 1>;
Simon Glassdb6f0202014-07-23 06:55:12 -0600334 ping-expect = <6>;
335 ping-add = <6>;
336 compatible = "google,another-fdt-test";
337 };
338
339 e-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600340 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600341 ping-expect = <6>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700342 ping-add = <6>;
343 compatible = "google,another-fdt-test";
344 };
345
Simon Glass0ccb0972015-01-25 08:27:05 -0700346 f-test {
347 compatible = "denx,u-boot-fdt-test";
348 };
349
350 g-test {
351 compatible = "denx,u-boot-fdt-test";
352 };
353
Bin Mengd9d24782018-10-10 22:07:01 -0700354 h-test {
355 compatible = "denx,u-boot-fdt-test1";
356 };
357
developercf8bc132020-05-02 11:35:10 +0200358 i-test {
359 compatible = "mediatek,u-boot-fdt-test";
360 #address-cells = <1>;
361 #size-cells = <0>;
362
363 subnode@0 {
364 reg = <0>;
365 };
366
367 subnode@1 {
368 reg = <1>;
369 };
370
371 subnode@2 {
372 reg = <2>;
373 };
374 };
375
Simon Glass204675c2019-12-29 21:19:25 -0700376 devres-test {
377 compatible = "denx,u-boot-devres-test";
378 };
379
Jean-Jacques Hiblot73873402020-09-11 13:43:35 +0530380 another-test {
381 reg = <0 2>;
382 compatible = "denx,u-boot-fdt-test";
383 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
384 test5-gpios = <&gpio_a 19>;
385 };
386
Nicolas Saenz Julienne22b7f7e2021-01-12 13:55:23 +0100387 mmio-bus@0 {
388 #address-cells = <1>;
389 #size-cells = <1>;
390 compatible = "denx,u-boot-test-bus";
391 dma-ranges = <0x10000000 0x00000000 0x00040000>;
392
393 subnode@0 {
394 compatible = "denx,u-boot-fdt-test";
395 };
396 };
397
398 mmio-bus@1 {
399 #address-cells = <1>;
400 #size-cells = <1>;
401 compatible = "denx,u-boot-test-bus";
Nicolas Saenz Julienne892e9b42021-01-12 13:55:25 +0100402
403 subnode@0 {
404 compatible = "denx,u-boot-fdt-test";
405 };
Nicolas Saenz Julienne22b7f7e2021-01-12 13:55:23 +0100406 };
407
Simon Glass3c601b12020-07-07 13:12:06 -0600408 acpi_test1: acpi-test {
Simon Glass2d67fdf2020-04-08 16:57:34 -0600409 compatible = "denx,u-boot-acpi-test";
Simon Glassd43e0ba2020-07-07 13:12:03 -0600410 acpi-ssdt-test-data = "ab";
Simon Glass990cd5b2020-07-07 13:12:08 -0600411 acpi-dsdt-test-data = "hi";
Simon Glassebb2e832020-07-07 13:11:39 -0600412 child {
413 compatible = "denx,u-boot-acpi-test";
414 };
Simon Glass2d67fdf2020-04-08 16:57:34 -0600415 };
416
Simon Glass3c601b12020-07-07 13:12:06 -0600417 acpi_test2: acpi-test2 {
Simon Glass17968c32020-04-26 09:19:46 -0600418 compatible = "denx,u-boot-acpi-test";
Simon Glassd43e0ba2020-07-07 13:12:03 -0600419 acpi-ssdt-test-data = "cd";
Simon Glass990cd5b2020-07-07 13:12:08 -0600420 acpi-dsdt-test-data = "jk";
Simon Glass17968c32020-04-26 09:19:46 -0600421 };
422
Patrice Chotard9cc2d142017-09-04 14:55:57 +0200423 clocks {
424 clk_fixed: clk-fixed {
425 compatible = "fixed-clock";
426 #clock-cells = <0>;
427 clock-frequency = <1234>;
428 };
Anup Patel8d28c3c2019-02-25 08:14:55 +0000429
430 clk_fixed_factor: clk-fixed-factor {
431 compatible = "fixed-factor-clock";
432 #clock-cells = <0>;
433 clock-div = <3>;
434 clock-mult = <2>;
435 clocks = <&clk_fixed>;
436 };
Lukasz Majewskiccafcdd2019-06-24 15:50:47 +0200437
438 osc {
439 compatible = "fixed-clock";
440 #clock-cells = <0>;
441 clock-frequency = <20000000>;
442 };
Stephen Warrena9622432016-06-17 09:44:00 -0600443 };
444
445 clk_sandbox: clk-sbox {
Simon Glass8cc4d822015-07-06 12:54:24 -0600446 compatible = "sandbox,clk";
Stephen Warrena9622432016-06-17 09:44:00 -0600447 #clock-cells = <1>;
Jean-Jacques Hiblotc1e9c942019-10-22 14:00:07 +0200448 assigned-clocks = <&clk_sandbox 3>;
449 assigned-clock-rates = <321>;
Stephen Warrena9622432016-06-17 09:44:00 -0600450 };
451
452 clk-test {
453 compatible = "sandbox,clk-test";
454 clocks = <&clk_fixed>,
455 <&clk_sandbox 1>,
Jean-Jacques Hiblot98e84182019-10-22 14:00:05 +0200456 <&clk_sandbox 0>,
457 <&clk_sandbox 3>,
458 <&clk_sandbox 2>;
459 clock-names = "fixed", "i2c", "spi", "uart2", "uart1";
Simon Glass8cc4d822015-07-06 12:54:24 -0600460 };
461
Lukasz Majewski8c0709b2019-06-24 15:50:50 +0200462 ccf: clk-ccf {
463 compatible = "sandbox,clk-ccf";
464 };
465
Simon Glass5b968632015-05-22 15:42:15 -0600466 eth@10002000 {
467 compatible = "sandbox,eth";
468 reg = <0x10002000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500469 fake-host-hwaddr = [00 00 66 44 22 00];
Simon Glass5b968632015-05-22 15:42:15 -0600470 };
471
472 eth_5: eth@10003000 {
473 compatible = "sandbox,eth";
474 reg = <0x10003000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500475 fake-host-hwaddr = [00 00 66 44 22 11];
Simon Glass5b968632015-05-22 15:42:15 -0600476 };
477
Bin Meng04a11cb2015-08-27 22:25:53 -0700478 eth_3: sbe5 {
479 compatible = "sandbox,eth";
480 reg = <0x10005000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500481 fake-host-hwaddr = [00 00 66 44 22 33];
Bin Meng04a11cb2015-08-27 22:25:53 -0700482 };
483
Simon Glass5b968632015-05-22 15:42:15 -0600484 eth@10004000 {
485 compatible = "sandbox,eth";
486 reg = <0x10004000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500487 fake-host-hwaddr = [00 00 66 44 22 22];
Simon Glass5b968632015-05-22 15:42:15 -0600488 };
489
Claudiu Manoild9eaa922021-03-14 20:14:57 +0800490 dsa_eth0: dsa-test-eth {
491 compatible = "sandbox,eth";
492 reg = <0x10006000 0x1000>;
493 fake-host-hwaddr = [00 00 66 44 22 66];
494 };
495
496 dsa-test {
497 compatible = "sandbox,dsa";
498
499 ports {
500 #address-cells = <1>;
501 #size-cells = <0>;
502 swp_0: port@0 {
503 reg = <0>;
504 label = "lan0";
505 phy-mode = "rgmii-rxid";
506
507 fixed-link {
508 speed = <100>;
509 full-duplex;
510 };
511 };
512
513 swp_1: port@1 {
514 reg = <1>;
515 label = "lan1";
516 phy-mode = "rgmii-txid";
Bin Meng381ed972021-03-14 20:14:58 +0800517 fixed-link = <0 1 100 0 0>;
Claudiu Manoild9eaa922021-03-14 20:14:57 +0800518 };
519
520 port@2 {
521 reg = <2>;
522 ethernet = <&dsa_eth0>;
523
524 fixed-link {
525 speed = <1000>;
526 full-duplex;
527 };
528 };
529 };
530 };
531
Rajan Vajab3b2ddb2018-09-19 03:43:46 -0700532 firmware {
533 sandbox_firmware: sandbox-firmware {
534 compatible = "sandbox,firmware";
535 };
Etienne Carriere02fd1262020-09-09 18:44:00 +0200536
537 sandbox-scmi-agent@0 {
538 compatible = "sandbox,scmi-agent";
539 #address-cells = <1>;
540 #size-cells = <0>;
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +0200541
542 clk_scmi0: protocol@14 {
543 reg = <0x14>;
544 #clock-cells = <1>;
545 };
Etienne Carriere8b9b6892020-09-09 18:44:07 +0200546
547 reset_scmi0: protocol@16 {
548 reg = <0x16>;
549 #reset-cells = <1>;
550 };
Etienne Carriereb8f15cd2021-03-08 22:38:07 +0100551
552 protocol@17 {
553 reg = <0x17>;
554
555 regulators {
556 #address-cells = <1>;
557 #size-cells = <0>;
558
559 regul0_scmi0: reg@0 {
560 reg = <0>;
561 regulator-name = "sandbox-voltd0";
562 regulator-min-microvolt = <1100000>;
563 regulator-max-microvolt = <3300000>;
564 };
565 regul1_scmi0: reg@1 {
566 reg = <0x1>;
567 regulator-name = "sandbox-voltd1";
568 regulator-min-microvolt = <1800000>;
569 };
570 };
571 };
Etienne Carriere02fd1262020-09-09 18:44:00 +0200572 };
573
574 sandbox-scmi-agent@1 {
575 compatible = "sandbox,scmi-agent";
576 #address-cells = <1>;
577 #size-cells = <0>;
578
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +0200579 clk_scmi1: protocol@14 {
580 reg = <0x14>;
581 #clock-cells = <1>;
582 };
583
Etienne Carriere02fd1262020-09-09 18:44:00 +0200584 protocol@10 {
585 reg = <0x10>;
586 };
587 };
Rajan Vajab3b2ddb2018-09-19 03:43:46 -0700588 };
589
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100590 pinctrl-gpio {
591 compatible = "sandbox,pinctrl-gpio";
Simon Glassb2c1cac2014-02-26 15:59:21 -0700592
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100593 gpio_a: base-gpios {
594 compatible = "sandbox,gpio";
595 gpio-controller;
596 #gpio-cells = <1>;
597 gpio-bank-name = "a";
598 sandbox,gpio-count = <20>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200599 hog_input_active_low {
600 gpio-hog;
601 input;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200602 gpios = <10 GPIO_ACTIVE_LOW>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200603 };
604 hog_input_active_high {
605 gpio-hog;
606 input;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200607 gpios = <11 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200608 };
609 hog_output_low {
610 gpio-hog;
611 output-low;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200612 gpios = <12 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200613 };
614 hog_output_high {
615 gpio-hog;
616 output-high;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200617 gpios = <13 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200618 };
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100619 };
620
621 gpio_b: extra-gpios {
622 compatible = "sandbox,gpio";
623 gpio-controller;
624 #gpio-cells = <5>;
625 gpio-bank-name = "b";
626 sandbox,gpio-count = <10>;
627 };
Simon Glass25348a42014-10-13 23:42:11 -0600628
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100629 gpio_c: pinmux-gpios {
630 compatible = "sandbox,gpio";
631 gpio-controller;
632 #gpio-cells = <2>;
633 gpio-bank-name = "c";
634 sandbox,gpio-count = <10>;
635 };
Patrick Delaunay28bdaa52020-01-13 11:35:14 +0100636 };
637
Simon Glass7df766e2014-12-10 08:55:55 -0700638 i2c@0 {
639 #address-cells = <1>;
640 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -0600641 reg = <0 1>;
Simon Glass7df766e2014-12-10 08:55:55 -0700642 compatible = "sandbox,i2c";
643 clock-frequency = <100000>;
Dario Binacchi20dd9e12021-04-11 09:39:50 +0200644 pinctrl-names = "default";
645 pinctrl-0 = <&pinmux_i2c0_pins>;
646
Simon Glass7df766e2014-12-10 08:55:55 -0700647 eeprom@2c {
648 reg = <0x2c>;
649 compatible = "i2c-eeprom";
Simon Glass17b56f62018-11-18 08:14:34 -0700650 sandbox,emul = <&emul_eeprom>;
Michal Simek4f18f922020-05-28 11:48:55 +0200651 partitions {
652 compatible = "fixed-partitions";
653 #address-cells = <1>;
654 #size-cells = <1>;
655 bootcount_i2c: bootcount@10 {
656 reg = <10 2>;
657 };
658 };
Simon Glass7df766e2014-12-10 08:55:55 -0700659 };
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200660
Simon Glass336b2952015-05-22 15:42:17 -0600661 rtc_0: rtc@43 {
662 reg = <0x43>;
663 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700664 sandbox,emul = <&emul0>;
Simon Glass336b2952015-05-22 15:42:17 -0600665 };
666
667 rtc_1: rtc@61 {
668 reg = <0x61>;
669 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700670 sandbox,emul = <&emul1>;
671 };
672
673 i2c_emul: emul {
674 reg = <0xff>;
675 compatible = "sandbox,i2c-emul-parent";
676 emul_eeprom: emul-eeprom {
677 compatible = "sandbox,i2c-eeprom";
678 sandbox,filename = "i2c.bin";
679 sandbox,size = <256>;
680 };
681 emul0: emul0 {
Simon Glass98af3742021-02-03 06:01:17 -0700682 compatible = "sandbox,i2c-rtc-emul";
Simon Glass17b56f62018-11-18 08:14:34 -0700683 };
684 emul1: emull {
Simon Glass98af3742021-02-03 06:01:17 -0700685 compatible = "sandbox,i2c-rtc-emul";
Simon Glass336b2952015-05-22 15:42:17 -0600686 };
687 };
688
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200689 sandbox_pmic: sandbox_pmic {
690 reg = <0x40>;
Simon Glass17b56f62018-11-18 08:14:34 -0700691 sandbox,emul = <&emul_pmic0>;
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200692 };
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200693
694 mc34708: pmic@41 {
695 reg = <0x41>;
Simon Glass17b56f62018-11-18 08:14:34 -0700696 sandbox,emul = <&emul_pmic1>;
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200697 };
Simon Glass7df766e2014-12-10 08:55:55 -0700698 };
699
Philipp Tomsich1fc53302018-12-14 21:14:29 +0100700 bootcount@0 {
701 compatible = "u-boot,bootcount-rtc";
702 rtc = <&rtc_1>;
703 offset = <0x13>;
704 };
705
Michal Simek4f18f922020-05-28 11:48:55 +0200706 bootcount {
707 compatible = "u-boot,bootcount-i2c-eeprom";
708 i2c-eeprom = <&bootcount_i2c>;
709 };
710
Marek Szyprowskiad398592021-02-18 11:33:18 +0100711 adc: adc@0 {
Przemyslaw Marczak1bc7f232015-10-27 13:08:06 +0100712 compatible = "sandbox,adc";
Marek Szyprowskiad398592021-02-18 11:33:18 +0100713 #io-channel-cells = <1>;
Przemyslaw Marczak1bc7f232015-10-27 13:08:06 +0100714 vdd-supply = <&buck2>;
715 vss-microvolts = <0>;
716 };
717
Simon Glass515dcff2020-02-06 09:55:00 -0700718 irq: irq {
Simon Glass54028bc2019-12-06 21:41:59 -0700719 compatible = "sandbox,irq";
Simon Glass515dcff2020-02-06 09:55:00 -0700720 interrupt-controller;
721 #interrupt-cells = <2>;
Simon Glass54028bc2019-12-06 21:41:59 -0700722 };
723
Simon Glass90b6fef2016-01-18 19:52:26 -0700724 lcd {
725 u-boot,dm-pre-reloc;
726 compatible = "sandbox,lcd-sdl";
Dario Binacchi20dd9e12021-04-11 09:39:50 +0200727 pinctrl-names = "default";
728 pinctrl-0 = <&pinmux_lcd_pins>;
Simon Glass90b6fef2016-01-18 19:52:26 -0700729 xres = <1366>;
730 yres = <768>;
731 };
732
Simon Glassd783eb32015-07-06 12:54:34 -0600733 leds {
734 compatible = "gpio-leds";
735
736 iracibble {
737 gpios = <&gpio_a 1 0>;
738 label = "sandbox:red";
739 };
740
741 martinet {
742 gpios = <&gpio_a 2 0>;
743 label = "sandbox:green";
744 };
Patrick Bruennb58adfe2018-04-11 11:16:29 +0200745
746 default_on {
747 gpios = <&gpio_a 5 0>;
748 label = "sandbox:default_on";
749 default-state = "on";
750 };
751
752 default_off {
753 gpios = <&gpio_a 6 0>;
Sean Andersonfbf8d652020-09-14 11:02:03 -0400754 /* label intentionally omitted */
Patrick Bruennb58adfe2018-04-11 11:16:29 +0200755 default-state = "off";
756 };
Simon Glassd783eb32015-07-06 12:54:34 -0600757 };
758
Stephen Warren62f2c902016-05-16 17:41:37 -0600759 mbox: mbox {
760 compatible = "sandbox,mbox";
761 #mbox-cells = <1>;
762 };
763
764 mbox-test {
765 compatible = "sandbox,mbox-test";
766 mboxes = <&mbox 100>, <&mbox 1>;
767 mbox-names = "other", "test";
768 };
769
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900770 cpus {
Sean Anderson79d3bba2020-09-28 10:52:23 -0400771 timebase-frequency = <2000000>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900772 cpu-test1 {
Sean Anderson79d3bba2020-09-28 10:52:23 -0400773 timebase-frequency = <3000000>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900774 compatible = "sandbox,cpu_sandbox";
775 u-boot,dm-pre-reloc;
776 };
Mario Sixdea5df72018-08-06 10:23:44 +0200777
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900778 cpu-test2 {
779 compatible = "sandbox,cpu_sandbox";
780 u-boot,dm-pre-reloc;
781 };
Mario Sixdea5df72018-08-06 10:23:44 +0200782
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900783 cpu-test3 {
784 compatible = "sandbox,cpu_sandbox";
785 u-boot,dm-pre-reloc;
786 };
Mario Sixdea5df72018-08-06 10:23:44 +0200787 };
788
Dave Gerlach75dbdfc2020-07-15 23:39:58 -0500789 chipid: chipid {
790 compatible = "sandbox,soc";
791 };
792
Simon Glassc953aaf2018-12-10 10:37:34 -0700793 i2s: i2s {
794 compatible = "sandbox,i2s";
795 #sound-dai-cells = <1>;
Simon Glass4d5814c2019-02-16 20:24:56 -0700796 sandbox,silent; /* Don't emit sounds while testing */
Simon Glassc953aaf2018-12-10 10:37:34 -0700797 };
798
Jean-Jacques Hiblotdb97c7f2019-07-05 09:33:57 +0200799 nop-test_0 {
800 compatible = "sandbox,nop_sandbox1";
801 nop-test_1 {
802 compatible = "sandbox,nop_sandbox2";
803 bind = "True";
804 };
805 nop-test_2 {
806 compatible = "sandbox,nop_sandbox2";
807 bind = "False";
808 };
809 };
810
Mario Sixa8ce0ee2018-07-31 14:24:14 +0200811 misc-test {
812 compatible = "sandbox,misc_sandbox";
813 };
814
Simon Glasse4fef742017-04-23 20:02:07 -0600815 mmc2 {
816 compatible = "sandbox,mmc";
817 };
818
819 mmc1 {
820 compatible = "sandbox,mmc";
821 };
822
823 mmc0 {
Simon Glassd3e58e42015-07-06 12:54:32 -0600824 compatible = "sandbox,mmc";
825 };
826
Simon Glass53a68b32019-02-16 20:24:50 -0700827 pch {
828 compatible = "sandbox,pch";
829 };
830
Tom Rini4a3ca482020-02-11 12:41:23 -0500831 pci0: pci@0 {
Simon Glass3a6eae62015-03-05 12:25:34 -0700832 compatible = "sandbox,pci";
833 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -0500834 bus-range = <0x00 0xff>;
Simon Glass3a6eae62015-03-05 12:25:34 -0700835 #address-cells = <3>;
836 #size-cells = <2>;
Simon Glass35464f72019-09-25 08:56:08 -0600837 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000000
Simon Glass3a6eae62015-03-05 12:25:34 -0700838 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Bin Mengcbf071b2018-08-03 01:14:39 -0700839 pci@0,0 {
840 compatible = "pci-generic";
841 reg = <0x0000 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600842 sandbox,emul = <&swap_case_emul0_0>;
Bin Mengcbf071b2018-08-03 01:14:39 -0700843 };
Alex Margineanf1274432019-06-07 11:24:24 +0300844 pci@1,0 {
845 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -0600846 /* reg 0 is at 0x14, using FDT_PCI_SPACE_MEM32 */
847 reg = <0x02000814 0 0 0 0
848 0x01000810 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600849 sandbox,emul = <&swap_case_emul0_1>;
Alex Margineanf1274432019-06-07 11:24:24 +0300850 };
Simon Glass937bb472019-12-06 21:41:57 -0700851 p2sb-pci@2,0 {
852 compatible = "sandbox,p2sb";
853 reg = <0x02001010 0 0 0 0>;
854 sandbox,emul = <&p2sb_emul>;
855
856 adder {
857 intel,p2sb-port-id = <3>;
858 compatible = "sandbox,adder";
859 };
860 };
Simon Glass8c501022019-12-06 21:41:54 -0700861 pci@1e,0 {
862 compatible = "sandbox,pmc";
863 reg = <0xf000 0 0 0 0>;
864 sandbox,emul = <&pmc_emul1e>;
865 acpi-base = <0x400>;
866 gpe0-dwx-mask = <0xf>;
867 gpe0-dwx-shift-base = <4>;
868 gpe0-dw = <6 7 9>;
869 gpe0-sts = <0x20>;
870 gpe0-en = <0x30>;
871 };
Simon Glass3a6eae62015-03-05 12:25:34 -0700872 pci@1f,0 {
873 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -0600874 /* reg 0 is at 0x10, using FDT_PCI_SPACE_IO */
875 reg = <0x0100f810 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600876 sandbox,emul = <&swap_case_emul0_1f>;
Simon Glass3a6eae62015-03-05 12:25:34 -0700877 };
878 };
879
Simon Glassb98ba4c2019-09-25 08:56:10 -0600880 pci-emul0 {
881 compatible = "sandbox,pci-emul-parent";
882 swap_case_emul0_0: emul0@0,0 {
883 compatible = "sandbox,swap-case";
884 };
885 swap_case_emul0_1: emul0@1,0 {
886 compatible = "sandbox,swap-case";
887 use-ea;
888 };
889 swap_case_emul0_1f: emul0@1f,0 {
890 compatible = "sandbox,swap-case";
891 };
Simon Glass937bb472019-12-06 21:41:57 -0700892 p2sb_emul: emul@2,0 {
893 compatible = "sandbox,p2sb-emul";
894 };
Simon Glass8c501022019-12-06 21:41:54 -0700895 pmc_emul1e: emul@1e,0 {
896 compatible = "sandbox,pmc-emul";
897 };
Simon Glassb98ba4c2019-09-25 08:56:10 -0600898 };
899
Tom Rini4a3ca482020-02-11 12:41:23 -0500900 pci1: pci@1 {
Bin Meng408e5902018-08-03 01:14:41 -0700901 compatible = "sandbox,pci";
902 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -0500903 bus-range = <0x00 0xff>;
Bin Meng408e5902018-08-03 01:14:41 -0700904 #address-cells = <3>;
905 #size-cells = <2>;
Suneel Garapati3ac3aec2019-10-19 17:10:20 -0700906 ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000 // MEM0
907 0x02000000 0 0x31000000 0x31000000 0 0x2000 // MEM1
908 0x01000000 0 0x40000000 0x40000000 0 0x2000>;
Bin Meng5fed5362018-08-03 01:14:47 -0700909 sandbox,dev-info = <0x08 0x00 0x1234 0x5678
Marek Vasute5733222018-10-10 21:27:08 +0200910 0x0c 0x00 0x1234 0x5678
911 0x10 0x00 0x1234 0x5678>;
912 pci@10,0 {
913 reg = <0x8000 0 0 0 0>;
914 };
Bin Meng408e5902018-08-03 01:14:41 -0700915 };
916
Tom Rini4a3ca482020-02-11 12:41:23 -0500917 pci2: pci@2 {
Bin Meng510dddb2018-08-03 01:14:50 -0700918 compatible = "sandbox,pci";
919 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -0500920 bus-range = <0x00 0xff>;
Bin Meng510dddb2018-08-03 01:14:50 -0700921 #address-cells = <3>;
922 #size-cells = <2>;
923 ranges = <0x02000000 0 0x50000000 0x50000000 0 0x2000
924 0x01000000 0 0x60000000 0x60000000 0 0x2000>;
925 sandbox,dev-info = <0x08 0x00 0x1234 0x5678>;
926 pci@1f,0 {
927 compatible = "pci-generic";
928 reg = <0xf800 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600929 sandbox,emul = <&swap_case_emul2_1f>;
930 };
931 };
932
933 pci-emul2 {
934 compatible = "sandbox,pci-emul-parent";
935 swap_case_emul2_1f: emul2@1f,0 {
936 compatible = "sandbox,swap-case";
Bin Meng510dddb2018-08-03 01:14:50 -0700937 };
938 };
939
Ramon Friedc64f19b2019-04-27 11:15:23 +0300940 pci_ep: pci_ep {
941 compatible = "sandbox,pci_ep";
942 };
943
Simon Glass9c433fe2017-04-23 20:10:44 -0600944 probing {
945 compatible = "simple-bus";
946 test1 {
947 compatible = "denx,u-boot-probe-test";
948 };
949
950 test2 {
951 compatible = "denx,u-boot-probe-test";
952 };
953
954 test3 {
955 compatible = "denx,u-boot-probe-test";
956 };
957
958 test4 {
959 compatible = "denx,u-boot-probe-test";
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +0100960 first-syscon = <&syscon0>;
961 second-sys-ctrl = <&another_system_controller>;
Patrick Delaunayee010432019-03-07 09:57:13 +0100962 third-syscon = <&syscon2>;
Simon Glass9c433fe2017-04-23 20:10:44 -0600963 };
964 };
965
Stephen Warren92c67fa2016-07-13 13:45:31 -0600966 pwrdom: power-domain {
967 compatible = "sandbox,power-domain";
968 #power-domain-cells = <1>;
969 };
970
971 power-domain-test {
972 compatible = "sandbox,power-domain-test";
973 power-domains = <&pwrdom 2>;
974 };
975
Simon Glass5620cf82018-10-01 12:22:40 -0600976 pwm: pwm {
Simon Glasse62f4be2017-04-16 21:01:11 -0600977 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -0600978 #pwm-cells = <2>;
Dario Binacchi20dd9e12021-04-11 09:39:50 +0200979 pinctrl-names = "default";
980 pinctrl-0 = <&pinmux_pwm_pins>;
Simon Glasse62f4be2017-04-16 21:01:11 -0600981 };
982
983 pwm2 {
984 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -0600985 #pwm-cells = <2>;
Simon Glasse62f4be2017-04-16 21:01:11 -0600986 };
987
Simon Glass3d355e62015-07-06 12:54:31 -0600988 ram {
989 compatible = "sandbox,ram";
990 };
991
Simon Glassd860f222015-07-06 12:54:29 -0600992 reset@0 {
993 compatible = "sandbox,warm-reset";
994 };
995
996 reset@1 {
997 compatible = "sandbox,reset";
998 };
999
Stephen Warren6488e642016-06-17 09:43:59 -06001000 resetc: reset-ctl {
1001 compatible = "sandbox,reset-ctl";
1002 #reset-cells = <1>;
1003 };
1004
1005 reset-ctl-test {
1006 compatible = "sandbox,reset-ctl-test";
Neil Armstrong9b4cdef2021-04-20 10:42:25 +02001007 resets = <&resetc 100>, <&resetc 2>, <&resetc 20>, <&resetc 40>;
1008 reset-names = "other", "test", "test2", "test3";
Stephen Warren6488e642016-06-17 09:43:59 -06001009 };
1010
Sughosh Ganu23e37512019-12-28 23:58:31 +05301011 rng {
1012 compatible = "sandbox,sandbox-rng";
1013 };
1014
Nishanth Menonedf85812015-09-17 15:42:41 -05001015 rproc_1: rproc@1 {
1016 compatible = "sandbox,test-processor";
1017 remoteproc-name = "remoteproc-test-dev1";
1018 };
1019
1020 rproc_2: rproc@2 {
1021 compatible = "sandbox,test-processor";
1022 internal-memory-mapped;
1023 remoteproc-name = "remoteproc-test-dev2";
1024 };
1025
Simon Glass5620cf82018-10-01 12:22:40 -06001026 panel {
1027 compatible = "simple-panel";
1028 backlight = <&backlight 0 100>;
1029 };
1030
Ramon Fried26ed32e2018-07-02 02:57:59 +03001031 smem@0 {
1032 compatible = "sandbox,smem";
1033 };
1034
Simon Glass76072ac2018-12-10 10:37:36 -07001035 sound {
1036 compatible = "sandbox,sound";
1037 cpu {
1038 sound-dai = <&i2s 0>;
1039 };
1040
1041 codec {
1042 sound-dai = <&audio 0>;
1043 };
1044 };
1045
Simon Glass25348a42014-10-13 23:42:11 -06001046 spi@0 {
1047 #address-cells = <1>;
1048 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -06001049 reg = <0 1>;
Simon Glass25348a42014-10-13 23:42:11 -06001050 compatible = "sandbox,spi";
Ovidiu Panaitae734732020-12-14 19:06:47 +02001051 cs-gpios = <0>, <0>, <&gpio_a 0>;
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001052 pinctrl-names = "default";
1053 pinctrl-0 = <&pinmux_spi0_pins>;
1054
Simon Glass25348a42014-10-13 23:42:11 -06001055 spi.bin@0 {
1056 reg = <0>;
Neil Armstronga009fa72019-02-10 10:16:20 +00001057 compatible = "spansion,m25p16", "jedec,spi-nor";
Simon Glass25348a42014-10-13 23:42:11 -06001058 spi-max-frequency = <40000000>;
1059 sandbox,filename = "spi.bin";
1060 };
Ovidiu Panaitae734732020-12-14 19:06:47 +02001061 spi.bin@1 {
1062 reg = <1>;
1063 compatible = "spansion,m25p16", "jedec,spi-nor";
1064 spi-max-frequency = <50000000>;
1065 sandbox,filename = "spi.bin";
1066 spi-cpol;
1067 spi-cpha;
1068 };
Simon Glass25348a42014-10-13 23:42:11 -06001069 };
1070
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +01001071 syscon0: syscon@0 {
Simon Glasscd556522015-07-06 12:54:35 -06001072 compatible = "sandbox,syscon0";
Mario Sixe3f59f42018-10-04 09:00:40 +02001073 reg = <0x10 16>;
Simon Glasscd556522015-07-06 12:54:35 -06001074 };
1075
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +01001076 another_system_controller: syscon@1 {
Simon Glasscd556522015-07-06 12:54:35 -06001077 compatible = "sandbox,syscon1";
Simon Glasscf61f742015-07-06 12:54:36 -06001078 reg = <0x20 5
1079 0x28 6
1080 0x30 7
1081 0x38 8>;
Simon Glasscd556522015-07-06 12:54:35 -06001082 };
1083
Patrick Delaunayee010432019-03-07 09:57:13 +01001084 syscon2: syscon@2 {
Masahiro Yamada42ab1072018-04-23 13:26:53 +09001085 compatible = "simple-mfd", "syscon";
1086 reg = <0x40 5
1087 0x48 6
1088 0x50 7
1089 0x58 8>;
1090 };
1091
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +05301092 syscon3: syscon@3 {
1093 compatible = "simple-mfd", "syscon";
1094 reg = <0x000100 0x10>;
1095
1096 muxcontroller0: a-mux-controller {
1097 compatible = "mmio-mux";
1098 #mux-control-cells = <1>;
1099
1100 mux-reg-masks = <0x0 0x30>, /* 0: reg 0x0, bits 5:4 */
1101 <0xc 0x1E>, /* 1: reg 0xc, bits 4:1 */
1102 <0x4 0xFF>; /* 2: reg 0x4, bits 7:0 */
1103 idle-states = <MUX_IDLE_AS_IS>, <0x02>, <0x73>;
1104 u-boot,mux-autoprobe;
1105 };
1106 };
1107
1108 muxcontroller1: emul-mux-controller {
1109 compatible = "mux-emul";
1110 #mux-control-cells = <0>;
1111 u-boot,mux-autoprobe;
1112 idle-state = <0xabcd>;
1113 };
1114
Simon Glass791a17f2020-12-16 21:20:27 -07001115 testfdtm0 {
1116 compatible = "denx,u-boot-fdtm-test";
1117 };
1118
1119 testfdtm1: testfdtm1 {
1120 compatible = "denx,u-boot-fdtm-test";
1121 };
1122
1123 testfdtm2 {
1124 compatible = "denx,u-boot-fdtm-test";
1125 };
1126
Sean Anderson79d3bba2020-09-28 10:52:23 -04001127 timer@0 {
Thomas Chou6f2cfbf2015-12-11 16:27:34 +08001128 compatible = "sandbox,timer";
1129 clock-frequency = <1000000>;
1130 };
1131
Sean Anderson79d3bba2020-09-28 10:52:23 -04001132 timer@1 {
1133 compatible = "sandbox,timer";
1134 sandbox,timebase-frequency-fallback;
1135 };
1136
Miquel Raynal80938c12018-05-15 11:57:27 +02001137 tpm2 {
1138 compatible = "sandbox,tpm2";
1139 };
1140
Simon Glass5b968632015-05-22 15:42:15 -06001141 uart0: serial {
1142 compatible = "sandbox,serial";
1143 u-boot,dm-pre-reloc;
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001144 pinctrl-names = "default";
1145 pinctrl-0 = <&pinmux_uart0_pins>;
Joe Hershberger4c197242015-03-22 17:09:15 -05001146 };
1147
Simon Glass31680482015-03-25 12:23:05 -06001148 usb_0: usb@0 {
1149 compatible = "sandbox,usb";
1150 status = "disabled";
1151 hub {
1152 compatible = "sandbox,usb-hub";
1153 #address-cells = <1>;
1154 #size-cells = <0>;
1155 flash-stick {
1156 reg = <0>;
1157 compatible = "sandbox,usb-flash";
1158 };
1159 };
1160 };
1161
1162 usb_1: usb@1 {
1163 compatible = "sandbox,usb";
1164 hub {
1165 compatible = "usb-hub";
1166 usb,device-class = <9>;
Michael Walle7c961322020-06-02 01:47:07 +02001167 #address-cells = <1>;
1168 #size-cells = <0>;
Simon Glass31680482015-03-25 12:23:05 -06001169 hub-emul {
1170 compatible = "sandbox,usb-hub";
1171 #address-cells = <1>;
1172 #size-cells = <0>;
Simon Glass4700fe52015-11-08 23:48:01 -07001173 flash-stick@0 {
Simon Glass31680482015-03-25 12:23:05 -06001174 reg = <0>;
1175 compatible = "sandbox,usb-flash";
1176 sandbox,filepath = "testflash.bin";
1177 };
1178
Simon Glass4700fe52015-11-08 23:48:01 -07001179 flash-stick@1 {
1180 reg = <1>;
1181 compatible = "sandbox,usb-flash";
1182 sandbox,filepath = "testflash1.bin";
1183 };
1184
1185 flash-stick@2 {
1186 reg = <2>;
1187 compatible = "sandbox,usb-flash";
1188 sandbox,filepath = "testflash2.bin";
1189 };
1190
Simon Glassc0ccc722015-11-08 23:48:08 -07001191 keyb@3 {
1192 reg = <3>;
1193 compatible = "sandbox,usb-keyb";
1194 };
1195
Simon Glass31680482015-03-25 12:23:05 -06001196 };
Michael Walle7c961322020-06-02 01:47:07 +02001197
1198 usbstor@1 {
1199 reg = <1>;
1200 };
1201 usbstor@3 {
1202 reg = <3>;
1203 };
Simon Glass31680482015-03-25 12:23:05 -06001204 };
1205 };
1206
1207 usb_2: usb@2 {
1208 compatible = "sandbox,usb";
1209 status = "disabled";
1210 };
1211
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001212 spmi: spmi@0 {
1213 compatible = "sandbox,spmi";
1214 #address-cells = <0x1>;
1215 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -06001216 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001217 pm8916@0 {
1218 compatible = "qcom,spmi-pmic";
1219 reg = <0x0 0x1>;
1220 #address-cells = <0x1>;
1221 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -06001222 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001223
1224 spmi_gpios: gpios@c000 {
1225 compatible = "qcom,pm8916-gpio";
1226 reg = <0xc000 0x400>;
1227 gpio-controller;
1228 gpio-count = <4>;
1229 #gpio-cells = <2>;
1230 gpio-bank-name="spmi";
1231 };
1232 };
1233 };
maxims@google.comdaea6d42017-04-17 12:00:21 -07001234
1235 wdt0: wdt@0 {
1236 compatible = "sandbox,wdt";
1237 };
Rob Clarka471b672018-01-10 11:33:30 +01001238
Mario Six95922152018-08-09 14:51:19 +02001239 axi: axi@0 {
1240 compatible = "sandbox,axi";
1241 #address-cells = <0x1>;
1242 #size-cells = <0x1>;
1243 store@0 {
1244 compatible = "sandbox,sandbox_store";
1245 reg = <0x0 0x400>;
1246 };
1247 };
1248
Rob Clarka471b672018-01-10 11:33:30 +01001249 chosen {
Simon Glass305ac9a2018-02-03 10:36:58 -07001250 #address-cells = <1>;
1251 #size-cells = <1>;
Simon Glassf3455962020-01-27 08:49:43 -07001252 setting = "sunrise ohoka";
1253 other-node = "/some-bus/c-test@5";
Simon Glasse09223c2020-01-27 08:49:46 -07001254 int-values = <0x1937 72993>;
Simon Glass3c601b12020-07-07 13:12:06 -06001255 u-boot,acpi-ssdt-order = <&acpi_test2 &acpi_test1>;
Rob Clarka471b672018-01-10 11:33:30 +01001256 chosen-test {
1257 compatible = "denx,u-boot-fdt-test";
1258 reg = <9 1>;
1259 };
1260 };
Mario Six35616ef2018-03-12 14:53:33 +01001261
1262 translation-test@8000 {
1263 compatible = "simple-bus";
1264 reg = <0x8000 0x4000>;
1265
1266 #address-cells = <0x2>;
1267 #size-cells = <0x1>;
1268
1269 ranges = <0 0x0 0x8000 0x1000
1270 1 0x100 0x9000 0x1000
1271 2 0x200 0xA000 0x1000
1272 3 0x300 0xB000 0x1000
Dario Binacchib574d682020-12-30 00:16:21 +01001273 4 0x400 0xC000 0x1000
Mario Six35616ef2018-03-12 14:53:33 +01001274 >;
1275
Fabien Dessenne22236e02019-05-31 15:11:30 +02001276 dma-ranges = <0 0x000 0x10000000 0x1000
1277 1 0x100 0x20000000 0x1000
1278 >;
1279
Mario Six35616ef2018-03-12 14:53:33 +01001280 dev@0,0 {
1281 compatible = "denx,u-boot-fdt-dummy";
1282 reg = <0 0x0 0x1000>;
Álvaro Fernández Rojasa3181152018-12-03 19:37:09 +01001283 reg-names = "sandbox-dummy-0";
Mario Six35616ef2018-03-12 14:53:33 +01001284 };
1285
1286 dev@1,100 {
1287 compatible = "denx,u-boot-fdt-dummy";
1288 reg = <1 0x100 0x1000>;
1289
1290 };
1291
1292 dev@2,200 {
1293 compatible = "denx,u-boot-fdt-dummy";
1294 reg = <2 0x200 0x1000>;
1295 };
1296
1297
1298 noxlatebus@3,300 {
1299 compatible = "simple-bus";
1300 reg = <3 0x300 0x1000>;
1301
1302 #address-cells = <0x1>;
1303 #size-cells = <0x0>;
1304
1305 dev@42 {
1306 compatible = "denx,u-boot-fdt-dummy";
1307 reg = <0x42>;
1308 };
1309 };
Dario Binacchib574d682020-12-30 00:16:21 +01001310
1311 xlatebus@4,400 {
1312 compatible = "sandbox,zero-size-cells-bus";
1313 reg = <4 0x400 0x1000>;
1314 #address-cells = <1>;
1315 #size-cells = <1>;
1316 ranges = <0 4 0x400 0x1000>;
1317
1318 devs {
1319 #address-cells = <1>;
1320 #size-cells = <0>;
1321
1322 dev@19 {
1323 compatible = "denx,u-boot-fdt-dummy";
1324 reg = <0x19>;
1325 };
1326 };
1327 };
1328
Mario Six35616ef2018-03-12 14:53:33 +01001329 };
Mario Six02ad6fb2018-09-27 09:19:31 +02001330
1331 osd {
1332 compatible = "sandbox,sandbox_osd";
1333 };
Tom Rinib93eea72018-09-30 18:16:51 -04001334
Jens Wiklander86afaa62018-09-25 16:40:16 +02001335 sandbox_tee {
1336 compatible = "sandbox,tee";
1337 };
Bin Meng1bb290d2018-10-15 02:21:26 -07001338
1339 sandbox_virtio1 {
1340 compatible = "sandbox,virtio1";
1341 };
1342
1343 sandbox_virtio2 {
1344 compatible = "sandbox,virtio2";
1345 };
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001346
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +02001347 sandbox_scmi {
1348 compatible = "sandbox,scmi-devices";
1349 clocks = <&clk_scmi0 7>, <&clk_scmi0 3>, <&clk_scmi1 1>;
Etienne Carriere8b9b6892020-09-09 18:44:07 +02001350 resets = <&reset_scmi0 3>;
Etienne Carriereb8f15cd2021-03-08 22:38:07 +01001351 regul0-supply = <&regul0_scmi0>;
1352 regul1-supply = <&regul1_scmi0>;
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +02001353 };
1354
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001355 pinctrl {
1356 compatible = "sandbox,pinctrl";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001357
Sean Anderson3438e3b2020-09-14 11:01:57 -04001358 pinctrl-names = "default", "alternate";
1359 pinctrl-0 = <&pinctrl_gpios>, <&pinctrl_i2s>;
1360 pinctrl-1 = <&pinctrl_spi>, <&pinctrl_i2c>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001361
Sean Anderson3438e3b2020-09-14 11:01:57 -04001362 pinctrl_gpios: gpios {
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001363 gpio0 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001364 pins = "P5";
1365 function = "GPIO";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001366 bias-pull-up;
1367 input-disable;
1368 };
1369 gpio1 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001370 pins = "P6";
1371 function = "GPIO";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001372 output-high;
1373 drive-open-drain;
1374 };
1375 gpio2 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001376 pinmux = <SANDBOX_PINMUX(7, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001377 bias-pull-down;
1378 input-enable;
1379 };
1380 gpio3 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001381 pinmux = <SANDBOX_PINMUX(8, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001382 bias-disable;
1383 };
1384 };
Sean Anderson3438e3b2020-09-14 11:01:57 -04001385
1386 pinctrl_i2c: i2c {
1387 groups {
1388 groups = "I2C_UART";
1389 function = "I2C";
1390 };
1391
1392 pins {
1393 pins = "P0", "P1";
1394 drive-open-drain;
1395 };
1396 };
1397
1398 pinctrl_i2s: i2s {
1399 groups = "SPI_I2S";
1400 function = "I2S";
1401 };
1402
1403 pinctrl_spi: spi {
1404 groups = "SPI_I2S";
1405 function = "SPI";
1406
1407 cs {
1408 pinmux = <SANDBOX_PINMUX(5, SANDBOX_PINMUX_CS)>,
1409 <SANDBOX_PINMUX(6, SANDBOX_PINMUX_CS)>;
1410 };
1411 };
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001412 };
Benjamin Gaignarda550b542018-11-27 13:49:50 +01001413
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001414 pinctrl-single-no-width {
1415 compatible = "pinctrl-single";
1416 reg = <0x0000 0x238>;
1417 #pinctrl-cells = <1>;
1418 pinctrl-single,function-mask = <0x7f>;
1419 };
1420
1421 pinctrl-single-pins {
1422 compatible = "pinctrl-single";
1423 reg = <0x0000 0x238>;
1424 #pinctrl-cells = <1>;
1425 pinctrl-single,register-width = <32>;
1426 pinctrl-single,function-mask = <0x7f>;
1427
1428 pinmux_pwm_pins: pinmux_pwm_pins {
1429 pinctrl-single,pins = < 0x48 0x06 >;
1430 };
1431
1432 pinmux_spi0_pins: pinmux_spi0_pins {
1433 pinctrl-single,pins = <
1434 0x190 0x0c
1435 0x194 0x0c
1436 0x198 0x23
1437 0x19c 0x0c
1438 >;
1439 };
1440
1441 pinmux_uart0_pins: pinmux_uart0_pins {
1442 pinctrl-single,pins = <
1443 0x70 0x30
1444 0x74 0x00
1445 >;
1446 };
1447 };
1448
1449 pinctrl-single-bits {
1450 compatible = "pinctrl-single";
1451 reg = <0x0000 0x50>;
1452 #pinctrl-cells = <2>;
1453 pinctrl-single,bit-per-mux;
1454 pinctrl-single,register-width = <32>;
1455 pinctrl-single,function-mask = <0xf>;
1456
1457 pinmux_i2c0_pins: pinmux_i2c0_pins {
1458 pinctrl-single,bits = <
1459 0x10 0x00002200 0x0000ff00
1460 >;
1461 };
1462
1463 pinmux_lcd_pins: pinmux_lcd_pins {
1464 pinctrl-single,bits = <
1465 0x40 0x22222200 0xffffff00
1466 0x44 0x22222222 0xffffffff
1467 0x48 0x00000022 0x000000ff
1468 0x48 0x02000000 0x0f000000
1469 0x4c 0x02000022 0x0f0000ff
1470 >;
1471 };
1472 };
1473
Benjamin Gaignarda550b542018-11-27 13:49:50 +01001474 hwspinlock@0 {
1475 compatible = "sandbox,hwspinlock";
1476 };
Grygorii Strashko19ebf0b2018-11-28 19:17:51 +01001477
1478 dma: dma {
1479 compatible = "sandbox,dma";
1480 #dma-cells = <1>;
1481
1482 dmas = <&dma 0>, <&dma 1>, <&dma 2>;
1483 dma-names = "m2m", "tx0", "rx0";
1484 };
Alex Marginean0daa53a2019-06-03 19:12:28 +03001485
Alex Marginean0649be52019-07-12 10:13:53 +03001486 /*
1487 * keep mdio-mux ahead of mdio so that the mux is removed first at the
1488 * end of the test. If parent mdio is removed first, clean-up of the
1489 * mux will trigger a 2nd probe of parent-mdio, leaving parent-mdio
1490 * active at the end of the test. That it turn doesn't allow the mdio
1491 * class to be destroyed, triggering an error.
1492 */
1493 mdio-mux-test {
1494 compatible = "sandbox,mdio-mux";
1495 #address-cells = <1>;
1496 #size-cells = <0>;
1497 mdio-parent-bus = <&mdio>;
1498
1499 mdio-ch-test@0 {
1500 reg = <0>;
1501 };
1502 mdio-ch-test@1 {
1503 reg = <1>;
1504 };
1505 };
1506
1507 mdio: mdio-test {
Alex Marginean0daa53a2019-06-03 19:12:28 +03001508 compatible = "sandbox,mdio";
1509 };
Sean Andersonb7860542020-06-24 06:41:12 -04001510
1511 pm-bus-test {
1512 compatible = "simple-pm-bus";
1513 clocks = <&clk_sandbox 4>;
1514 power-domains = <&pwrdom 1>;
1515 };
Sean Anderson0c1f6bf2020-06-24 06:41:14 -04001516
1517 resetc2: syscon-reset {
1518 compatible = "syscon-reset";
1519 #reset-cells = <1>;
1520 regmap = <&syscon0>;
1521 offset = <1>;
1522 mask = <0x27FFFFFF>;
1523 assert-high = <0>;
1524 };
1525
1526 syscon-reset-test {
1527 compatible = "sandbox,misc_sandbox";
1528 resets = <&resetc2 15>, <&resetc2 30>, <&resetc2 60>;
1529 reset-names = "valid", "no_mask", "out_of_range";
1530 };
Jean-Jacques Hiblot0b89fc52020-09-24 10:04:18 +05301531
Simon Glass458b66a2020-11-05 06:32:05 -07001532 sysinfo {
1533 compatible = "sandbox,sysinfo-sandbox";
1534 };
1535
Sean Anderson1c830672021-04-20 10:50:58 -04001536 sysinfo-gpio {
1537 compatible = "gpio-sysinfo";
1538 gpios = <&gpio_a 15>, <&gpio_a 16>, <&gpio_a 17>;
1539 revisions = <19>, <5>;
1540 names = "rev_a", "foo";
1541 };
1542
Jean-Jacques Hiblot0b89fc52020-09-24 10:04:18 +05301543 some_regmapped-bus {
1544 #address-cells = <0x1>;
1545 #size-cells = <0x1>;
1546
1547 ranges = <0x0 0x0 0x10>;
1548 compatible = "simple-bus";
1549
1550 regmap-test_0 {
1551 reg = <0 0x10>;
1552 compatible = "sandbox,regmap_test";
1553 };
1554 };
Simon Glassb2c1cac2014-02-26 15:59:21 -07001555};
Przemyslaw Marczak77bee052015-05-13 13:38:35 +02001556
1557#include "sandbox_pmic.dtsi"
Heinrich Schuchardte24fdef2021-02-18 13:01:35 +01001558#include "cros-ec-keyboard.dtsi"