blob: a9bf213d8b44e3ffe2bdfcbede33a341bcdb0c87 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Li Yang5f999732011-07-26 09:50:46 -05002/*
3 * Copyright 2010-2011 Freescale Semiconductor, Inc.
Biwen Lib0939dd2020-05-01 20:04:01 +08004 * Copyright 2020 NXP
Li Yang5f999732011-07-26 09:50:46 -05005 */
6
7/*
8 * QorIQ RDB boards configuration file
9 */
10#ifndef __CONFIG_H
11#define __CONFIG_H
12
Simon Glassfb64e362020-05-10 11:40:09 -060013#include <linux/stringify.h>
14
York Sun443108bf2016-11-17 13:52:44 -080015#if defined(CONFIG_TARGET_P1020RDB_PC)
Scott Wood98c02b52012-08-20 13:16:30 +000016#define CONFIG_BOARDNAME "P1020RDB-PC"
Li Yang5f999732011-07-26 09:50:46 -050017#define CONFIG_NAND_FSL_ELBC
Li Yang5f999732011-07-26 09:50:46 -050018#define CONFIG_VSC7385_ENET
19#define CONFIG_SLIC
20#define __SW_BOOT_MASK 0x03
21#define __SW_BOOT_NOR 0x5c
22#define __SW_BOOT_SPI 0x1c
23#define __SW_BOOT_SD 0x9c
24#define __SW_BOOT_NAND 0xec
25#define __SW_BOOT_PCIE 0x6c
Scott Wood03fedda2012-10-12 18:02:24 -050026#define CONFIG_SYS_L2_SIZE (256 << 10)
Li Yang5f999732011-07-26 09:50:46 -050027#endif
28
Haijun.Zhanga434d0a2013-06-28 10:47:09 +080029/*
30 * P1020RDB-PD board has user selectable switches for evaluating different
31 * frequency and boot options for the P1020 device. The table that
32 * follow describe the available options. The front six binary number was in
33 * accordance with SW3[1:6].
34 * 111101 533 533 267 667 NOR Core0 boot; Core1 hold-off
35 * 101101 667 667 333 667 NOR Core0 boot; Core1 hold-off
36 * 011001 800 800 400 667 NOR Core0 boot; Core1 hold-off
37 * 001001 800 800 400 667 SD/MMC Core0 boot; Core1 hold-off
38 * 001101 800 800 400 667 SPI Core0 boot; Core1 hold-off
39 * 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off
40 * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off
41 */
York Sun06732382016-11-17 13:53:33 -080042#if defined(CONFIG_TARGET_P1020RDB_PD)
Haijun.Zhanga434d0a2013-06-28 10:47:09 +080043#define CONFIG_BOARDNAME "P1020RDB-PD"
44#define CONFIG_NAND_FSL_ELBC
Haijun.Zhanga434d0a2013-06-28 10:47:09 +080045#define CONFIG_VSC7385_ENET
46#define CONFIG_SLIC
47#define __SW_BOOT_MASK 0x03
48#define __SW_BOOT_NOR 0x64
49#define __SW_BOOT_SPI 0x34
50#define __SW_BOOT_SD 0x24
51#define __SW_BOOT_NAND 0x44
52#define __SW_BOOT_PCIE 0x74
53#define CONFIG_SYS_L2_SIZE (256 << 10)
Yangbo Lu140b2bb2014-10-16 10:58:55 +080054/*
55 * Dynamic MTD Partition support with mtdparts
56 */
Haijun.Zhanga434d0a2013-06-28 10:47:09 +080057#endif
58
York Sun9c01ff22016-11-17 14:19:18 -080059#if defined(CONFIG_TARGET_P2020RDB)
60#define CONFIG_BOARDNAME "P2020RDB-PC"
Li Yang5f999732011-07-26 09:50:46 -050061#define CONFIG_NAND_FSL_ELBC
Li Yang5f999732011-07-26 09:50:46 -050062#define CONFIG_VSC7385_ENET
63#define __SW_BOOT_MASK 0x03
64#define __SW_BOOT_NOR 0xc8
65#define __SW_BOOT_SPI 0x28
66#define __SW_BOOT_SD 0x68 /* or 0x18 */
67#define __SW_BOOT_NAND 0xe8
68#define __SW_BOOT_PCIE 0xa8
Scott Wood03fedda2012-10-12 18:02:24 -050069#define CONFIG_SYS_L2_SIZE (512 << 10)
Yangbo Lu140b2bb2014-10-16 10:58:55 +080070/*
71 * Dynamic MTD Partition support with mtdparts
72 */
Li Yang5f999732011-07-26 09:50:46 -050073#endif
74
75#ifdef CONFIG_SDCARD
Ying Zhang28027d72013-09-06 17:30:56 +080076#define CONFIG_SPL_FLUSH_IMAGE
77#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
Ying Zhang25daf572014-01-24 15:50:06 +080078#define CONFIG_SPL_PAD_TO 0x20000
79#define CONFIG_SPL_MAX_SIZE (128 * 1024)
Prabhakar Kushwahaf2036562014-01-14 11:34:26 +053080#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
Ying Zhang28027d72013-09-06 17:30:56 +080081#define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
82#define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
Ying Zhang25daf572014-01-24 15:50:06 +080083#define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10)
Ying Zhang28027d72013-09-06 17:30:56 +080084#define CONFIG_SYS_MPC85XX_NO_RESETVEC
Ying Zhang28027d72013-09-06 17:30:56 +080085#ifdef CONFIG_SPL_BUILD
86#define CONFIG_SPL_COMMON_INIT_DDR
87#endif
Li Yang5f999732011-07-26 09:50:46 -050088#endif
89
90#ifdef CONFIG_SPIFLASH
Ying Zhangf74fd4e2013-09-06 17:30:57 +080091#define CONFIG_SPL_SPI_FLASH_MINIMAL
92#define CONFIG_SPL_FLUSH_IMAGE
93#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
Ying Zhang25daf572014-01-24 15:50:06 +080094#define CONFIG_SPL_PAD_TO 0x20000
95#define CONFIG_SPL_MAX_SIZE (128 * 1024)
Prabhakar Kushwahaf2036562014-01-14 11:34:26 +053096#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
Ying Zhangf74fd4e2013-09-06 17:30:57 +080097#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
98#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
Ying Zhang25daf572014-01-24 15:50:06 +080099#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10)
Ying Zhangf74fd4e2013-09-06 17:30:57 +0800100#define CONFIG_SYS_MPC85XX_NO_RESETVEC
Ying Zhangf74fd4e2013-09-06 17:30:57 +0800101#ifdef CONFIG_SPL_BUILD
102#define CONFIG_SPL_COMMON_INIT_DDR
103#endif
Li Yang5f999732011-07-26 09:50:46 -0500104#endif
105
Miquel Raynald0935362019-10-03 19:50:03 +0200106#ifdef CONFIG_MTD_RAW_NAND
Ying Zhangb8b404d2013-09-06 17:30:58 +0800107#ifdef CONFIG_TPL_BUILD
Ying Zhangb8b404d2013-09-06 17:30:58 +0800108#define CONFIG_SPL_FLUSH_IMAGE
Ying Zhangb8b404d2013-09-06 17:30:58 +0800109#define CONFIG_SPL_NAND_INIT
Ying Zhangb8b404d2013-09-06 17:30:58 +0800110#define CONFIG_SPL_COMMON_INIT_DDR
111#define CONFIG_SPL_MAX_SIZE (128 << 10)
Tom Rini0a01a442019-01-22 17:09:24 -0500112#define CONFIG_TPL_TEXT_BASE 0xf8f81000
Ying Zhangb8b404d2013-09-06 17:30:58 +0800113#define CONFIG_SYS_MPC85XX_NO_RESETVEC
Prabhakar Kushwahaf2036562014-01-14 11:34:26 +0530114#define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10)
Ying Zhangb8b404d2013-09-06 17:30:58 +0800115#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
116#define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
117#define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
118#elif defined(CONFIG_SPL_BUILD)
Scott Wood6915cc22012-09-21 16:31:00 -0500119#define CONFIG_SPL_INIT_MINIMAL
Scott Wood6915cc22012-09-21 16:31:00 -0500120#define CONFIG_SPL_FLUSH_IMAGE
121#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
Benoît Thébaudeauf0180722013-04-11 09:35:49 +0000122#define CONFIG_SPL_MAX_SIZE 4096
Ying Zhangb8b404d2013-09-06 17:30:58 +0800123#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
124#define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
125#define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
126#define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
127#endif /* not CONFIG_TPL_BUILD */
Scott Wood03fedda2012-10-12 18:02:24 -0500128
Ying Zhangb8b404d2013-09-06 17:30:58 +0800129#define CONFIG_SPL_PAD_TO 0x20000
130#define CONFIG_TPL_PAD_TO 0x20000
131#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
Li Yang5f999732011-07-26 09:50:46 -0500132#endif
133
Li Yang5f999732011-07-26 09:50:46 -0500134#ifndef CONFIG_RESET_VECTOR_ADDRESS
135#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
136#endif
137
138#ifndef CONFIG_SYS_MONITOR_BASE
Tom Rini0a01a442019-01-22 17:09:24 -0500139#ifdef CONFIG_TPL_BUILD
140#define CONFIG_SYS_MONITOR_BASE CONFIG_TPL_TEXT_BASE
141#elif defined(CONFIG_SPL_BUILD)
Scott Wood6915cc22012-09-21 16:31:00 -0500142#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
143#else
Li Yang5f999732011-07-26 09:50:46 -0500144#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
145#endif
Scott Wood6915cc22012-09-21 16:31:00 -0500146#endif
Li Yang5f999732011-07-26 09:50:46 -0500147
Robert P. J. Daya8099812016-05-03 19:52:49 -0400148#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
149#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
Li Yang5f999732011-07-26 09:50:46 -0500150#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
151
Li Yang5f999732011-07-26 09:50:46 -0500152#define CONFIG_SYS_SATA_MAX_DEVICE 2
Li Yang5f999732011-07-26 09:50:46 -0500153#define CONFIG_LBA48
154
York Sun9c01ff22016-11-17 14:19:18 -0800155#if defined(CONFIG_TARGET_P2020RDB)
Li Yang5f999732011-07-26 09:50:46 -0500156#define CONFIG_SYS_CLK_FREQ 100000000
157#else
158#define CONFIG_SYS_CLK_FREQ 66666666
159#endif
160#define CONFIG_DDR_CLK_FREQ 66666666
161
162#define CONFIG_HWCONFIG
163/*
164 * These can be toggled for performance analysis, otherwise use default.
165 */
166#define CONFIG_L2_CACHE
167#define CONFIG_BTB
168
Li Yang5f999732011-07-26 09:50:46 -0500169#define CONFIG_ENABLE_36BIT_PHYS
Li Yang5f999732011-07-26 09:50:46 -0500170
Li Yang5f999732011-07-26 09:50:46 -0500171#define CONFIG_SYS_CCSRBAR 0xffe00000
172#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
173
174/* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
175 SPL code*/
Scott Wood6915cc22012-09-21 16:31:00 -0500176#ifdef CONFIG_SPL_BUILD
Li Yang5f999732011-07-26 09:50:46 -0500177#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
178#endif
179
180/* DDR Setup */
York Sun66f05142012-02-29 12:36:51 +0000181#define CONFIG_SYS_DDR_RAW_TIMING
Li Yang5f999732011-07-26 09:50:46 -0500182#define CONFIG_DDR_SPD
183#define CONFIG_SYS_SPD_BUS_NUM 1
184#define SPD_EEPROM_ADDRESS 0x52
Li Yang5f999732011-07-26 09:50:46 -0500185
Priyanka Jainb1d24412020-09-21 11:56:39 +0530186#if defined(CONFIG_TARGET_P1020RDB_PD)
Li Yang5f999732011-07-26 09:50:46 -0500187#define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G
188#define CONFIG_CHIP_SELECTS_PER_CTRL 2
189#else
190#define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G
191#define CONFIG_CHIP_SELECTS_PER_CTRL 1
192#endif
193#define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
194#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
195#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
196
Li Yang5f999732011-07-26 09:50:46 -0500197#define CONFIG_DIMM_SLOTS_PER_CTLR 1
198
199/* Default settings for DDR3 */
York Sun9c01ff22016-11-17 14:19:18 -0800200#ifndef CONFIG_TARGET_P2020RDB
Li Yang5f999732011-07-26 09:50:46 -0500201#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
202#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
203#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
204#define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f
205#define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302
206#define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
207
208#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
209#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
210#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
211#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
212
213#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
214#define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608
215#define CONFIG_SYS_DDR_SR_CNTR 0x00000000
216#define CONFIG_SYS_DDR_RCW_1 0x00000000
217#define CONFIG_SYS_DDR_RCW_2 0x00000000
218#define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */
219#define CONFIG_SYS_DDR_CONTROL_2 0x04401050
220#define CONFIG_SYS_DDR_TIMING_4 0x00220001
221#define CONFIG_SYS_DDR_TIMING_5 0x03402400
222
223#define CONFIG_SYS_DDR_TIMING_3 0x00020000
224#define CONFIG_SYS_DDR_TIMING_0 0x00330004
225#define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846
226#define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF
227#define CONFIG_SYS_DDR_CLK_CTRL 0x03000000
228#define CONFIG_SYS_DDR_MODE_1 0x40461520
229#define CONFIG_SYS_DDR_MODE_2 0x8000c000
230#define CONFIG_SYS_DDR_INTERVAL 0x0C300000
231#endif
232
Li Yang5f999732011-07-26 09:50:46 -0500233/*
234 * Memory map
235 *
Scott Wood5e621872012-10-02 19:35:18 -0500236 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable
Li Yang5f999732011-07-26 09:50:46 -0500237 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3)
Scott Wood5e621872012-10-02 19:35:18 -0500238 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1
Scott Wood03fedda2012-10-12 18:02:24 -0500239 * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 512K cacheable
240 * (early boot only)
Scott Wood5e621872012-10-02 19:35:18 -0500241 * 0xff80_0000 0xff80_7fff NAND flash 32K non-cacheable CS1/0
242 * 0xff98_0000 0xff98_ffff PMC 64K non-cacheable CS2
243 * 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable CS3
244 * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable CS2
Li Yang5f999732011-07-26 09:50:46 -0500245 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
Scott Wood5e621872012-10-02 19:35:18 -0500246 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable
Scott Wood5e621872012-10-02 19:35:18 -0500247 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
Li Yang5f999732011-07-26 09:50:46 -0500248 */
249
Li Yang5f999732011-07-26 09:50:46 -0500250/*
251 * Local Bus Definitions
252 */
Priyanka Jainb1d24412020-09-21 11:56:39 +0530253#if defined(CONFIG_TARGET_P1020RDB_PD)
Li Yang5f999732011-07-26 09:50:46 -0500254#define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
255#define CONFIG_SYS_FLASH_BASE 0xec000000
Li Yang5f999732011-07-26 09:50:46 -0500256#else
257#define CONFIG_SYS_MAX_FLASH_SECT 128 /* 16M */
258#define CONFIG_SYS_FLASH_BASE 0xef000000
259#endif
260
Li Yang5f999732011-07-26 09:50:46 -0500261#ifdef CONFIG_PHYS_64BIT
262#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
263#else
264#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
265#endif
266
Timur Tabib56570c2012-07-06 07:39:26 +0000267#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
Li Yang5f999732011-07-26 09:50:46 -0500268 | BR_PS_16 | BR_V)
269
270#define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
271
272#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
273#define CONFIG_SYS_FLASH_QUIET_TEST
274#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
275
276#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
277
278#undef CONFIG_SYS_FLASH_CHECKSUM
279#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
280#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
281
Li Yang5f999732011-07-26 09:50:46 -0500282#define CONFIG_SYS_FLASH_EMPTY_INFO
Li Yang5f999732011-07-26 09:50:46 -0500283
284/* Nand Flash */
285#ifdef CONFIG_NAND_FSL_ELBC
286#define CONFIG_SYS_NAND_BASE 0xff800000
287#ifdef CONFIG_PHYS_64BIT
288#define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
289#else
290#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
291#endif
292
293#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
294#define CONFIG_SYS_MAX_NAND_DEVICE 1
York Sun06732382016-11-17 13:53:33 -0800295#if defined(CONFIG_TARGET_P1020RDB_PD)
Haijun.Zhanga434d0a2013-06-28 10:47:09 +0800296#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
297#else
Li Yang5f999732011-07-26 09:50:46 -0500298#define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
Haijun.Zhanga434d0a2013-06-28 10:47:09 +0800299#endif
Li Yang5f999732011-07-26 09:50:46 -0500300
Timur Tabib56570c2012-07-06 07:39:26 +0000301#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
Li Yang5f999732011-07-26 09:50:46 -0500302 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
303 | BR_PS_8 /* Port Size = 8 bit */ \
304 | BR_MS_FCM /* MSEL = FCM */ \
305 | BR_V) /* valid */
York Sun06732382016-11-17 13:53:33 -0800306#if defined(CONFIG_TARGET_P1020RDB_PD)
Haijun.Zhanga434d0a2013-06-28 10:47:09 +0800307#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \
308 | OR_FCM_PGS /* Large Page*/ \
309 | OR_FCM_CSCT \
310 | OR_FCM_CST \
311 | OR_FCM_CHT \
312 | OR_FCM_SCY_1 \
313 | OR_FCM_TRLX \
314 | OR_FCM_EHTR)
315#else
Li Yang5f999732011-07-26 09:50:46 -0500316#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* small page */ \
317 | OR_FCM_CSCT \
318 | OR_FCM_CST \
319 | OR_FCM_CHT \
320 | OR_FCM_SCY_1 \
321 | OR_FCM_TRLX \
322 | OR_FCM_EHTR)
Haijun.Zhanga434d0a2013-06-28 10:47:09 +0800323#endif
Li Yang5f999732011-07-26 09:50:46 -0500324#endif /* CONFIG_NAND_FSL_ELBC */
325
Li Yang5f999732011-07-26 09:50:46 -0500326#define CONFIG_SYS_INIT_RAM_LOCK
327#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
328#ifdef CONFIG_PHYS_64BIT
329#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
330#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
331/* The assembler doesn't like typecast */
332#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
333 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
334 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
335#else
336/* Initial L1 address */
337#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
338#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
339#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
340#endif
341/* Size of used area in RAM */
342#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
343
344#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
345 GENERATED_GBL_DATA_SIZE)
346#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
347
Prabhakar Kushwahaf4027312014-03-31 15:31:48 +0530348#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
Li Yang5f999732011-07-26 09:50:46 -0500349#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */
350
351#define CONFIG_SYS_CPLD_BASE 0xffa00000
352#ifdef CONFIG_PHYS_64BIT
353#define CONFIG_SYS_CPLD_BASE_PHYS 0xfffa00000ull
354#else
355#define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
356#endif
357/* CPLD config size: 1Mb */
358#define CONFIG_CPLD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | \
359 BR_PS_8 | BR_V)
360#define CONFIG_CPLD_OR_PRELIM (0xfff009f7)
361
362#define CONFIG_SYS_PMC_BASE 0xff980000
363#define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE
364#define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \
365 BR_PS_8 | BR_V)
366#define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
367 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
368 OR_GPCM_EAD)
369
Miquel Raynald0935362019-10-03 19:50:03 +0200370#ifdef CONFIG_MTD_RAW_NAND
Li Yang5f999732011-07-26 09:50:46 -0500371#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
372#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
373#define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
374#define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
375#else
376#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
377#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
378#ifdef CONFIG_NAND_FSL_ELBC
379#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
380#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
381#endif
382#endif
383#define CONFIG_SYS_BR3_PRELIM CONFIG_CPLD_BR_PRELIM /* CPLD Base Address */
384#define CONFIG_SYS_OR3_PRELIM CONFIG_CPLD_OR_PRELIM /* CPLD Options */
385
Li Yang5f999732011-07-26 09:50:46 -0500386/* Vsc7385 switch */
387#ifdef CONFIG_VSC7385_ENET
Hou Zhiqiang0bbc8692020-07-16 18:09:17 +0800388#define __VSCFW_ADDR "vscfw_addr=ef000000"
Li Yang5f999732011-07-26 09:50:46 -0500389#define CONFIG_SYS_VSC7385_BASE 0xffb00000
390
391#ifdef CONFIG_PHYS_64BIT
392#define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull
393#else
394#define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE
395#endif
396
397#define CONFIG_SYS_VSC7385_BR_PRELIM \
398 (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE_PHYS) | BR_PS_8 | BR_V)
399#define CONFIG_SYS_VSC7385_OR_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | \
400 OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | \
401 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
402
403#define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_VSC7385_BR_PRELIM
404#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_VSC7385_OR_PRELIM
405
406/* The size of the VSC7385 firmware image */
407#define CONFIG_VSC7385_IMAGE_SIZE 8192
408#endif
409
Ying Zhang28027d72013-09-06 17:30:56 +0800410/*
411 * Config the L2 Cache as L2 SRAM
412*/
413#if defined(CONFIG_SPL_BUILD)
Ying Zhangf74fd4e2013-09-06 17:30:57 +0800414#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
Ying Zhang28027d72013-09-06 17:30:56 +0800415#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
416#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
417#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
418#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
Ying Zhang28027d72013-09-06 17:30:56 +0800419#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
Ying Zhang354846f2014-01-24 15:50:07 +0800420#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
Ying Zhang354846f2014-01-24 15:50:07 +0800421#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
York Sun9c01ff22016-11-17 14:19:18 -0800422#if defined(CONFIG_TARGET_P2020RDB)
Ying Zhang354846f2014-01-24 15:50:07 +0800423#define CONFIG_SPL_RELOC_MALLOC_SIZE (364 << 10)
424#else
425#define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10)
426#endif
Miquel Raynald0935362019-10-03 19:50:03 +0200427#elif defined(CONFIG_MTD_RAW_NAND)
Ying Zhangb8b404d2013-09-06 17:30:58 +0800428#ifdef CONFIG_TPL_BUILD
429#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
430#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
431#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
432#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
433#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
434#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
435#define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
436#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
437#else
438#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
439#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
440#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
441#define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000)
442#define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
443#endif /* CONFIG_TPL_BUILD */
Ying Zhang28027d72013-09-06 17:30:56 +0800444#endif
445#endif
446
Li Yang5f999732011-07-26 09:50:46 -0500447/* Serial Port - controlled on board with jumper J8
448 * open - index 2
449 * shorted - index 1
450 */
Li Yang5f999732011-07-26 09:50:46 -0500451#undef CONFIG_SERIAL_SOFTWARE_FIFO
Li Yang5f999732011-07-26 09:50:46 -0500452#define CONFIG_SYS_NS16550_SERIAL
453#define CONFIG_SYS_NS16550_REG_SIZE 1
454#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Ying Zhang28027d72013-09-06 17:30:56 +0800455#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
Li Yang5f999732011-07-26 09:50:46 -0500456#define CONFIG_NS16550_MIN_FUNCTIONS
457#endif
458
459#define CONFIG_SYS_BAUDRATE_TABLE \
460 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
461
462#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
463#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
464
Li Yang5f999732011-07-26 09:50:46 -0500465/* I2C */
Biwen Lib0939dd2020-05-01 20:04:01 +0800466#ifndef CONFIG_DM_I2C
Heiko Schocherf2850742012-10-24 13:48:22 +0200467#define CONFIG_SYS_I2C
Heiko Schocherf2850742012-10-24 13:48:22 +0200468#define CONFIG_SYS_FSL_I2C_SPEED 400000
469#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
470#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
471#define CONFIG_SYS_FSL_I2C2_SPEED 400000
472#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
473#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
474#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
Biwen Lib0939dd2020-05-01 20:04:01 +0800475#else
476#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
477#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
478#endif
479
480#define CONFIG_SYS_I2C_FSL
Li Yang5f999732011-07-26 09:50:46 -0500481#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
Li Yang5f999732011-07-26 09:50:46 -0500482#define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */
483
484/*
485 * I2C2 EEPROM
486 */
487#undef CONFIG_ID_EEPROM
488
489#define CONFIG_RTC_PT7C4338
490#define CONFIG_SYS_I2C_RTC_ADDR 0x68
491#define CONFIG_SYS_I2C_PCA9557_ADDR 0x18
492
493/* enable read and write access to EEPROM */
Li Yang5f999732011-07-26 09:50:46 -0500494#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
495#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
496#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
497
Li Yang5f999732011-07-26 09:50:46 -0500498#if defined(CONFIG_PCI)
499/*
500 * General PCI
501 * Memory space is mapped 1-1, but I/O space must start from 0.
502 */
503
504/* controller 2, direct to uli, tgtid 2, Base address 9000 */
Li Yang5f999732011-07-26 09:50:46 -0500505#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
506#ifdef CONFIG_PHYS_64BIT
Li Yang5f999732011-07-26 09:50:46 -0500507#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
508#else
Li Yang5f999732011-07-26 09:50:46 -0500509#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
510#endif
Li Yang5f999732011-07-26 09:50:46 -0500511#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
Li Yang5f999732011-07-26 09:50:46 -0500512#ifdef CONFIG_PHYS_64BIT
513#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
514#else
515#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
516#endif
Li Yang5f999732011-07-26 09:50:46 -0500517
518/* controller 1, Slot 2, tgtid 1, Base address a000 */
Li Yang5f999732011-07-26 09:50:46 -0500519#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
520#ifdef CONFIG_PHYS_64BIT
Li Yang5f999732011-07-26 09:50:46 -0500521#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
522#else
Li Yang5f999732011-07-26 09:50:46 -0500523#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
524#endif
Li Yang5f999732011-07-26 09:50:46 -0500525#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
Li Yang5f999732011-07-26 09:50:46 -0500526#ifdef CONFIG_PHYS_64BIT
527#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
528#else
529#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
530#endif
Hou Zhiqiang047860d2019-08-27 11:04:08 +0000531
532#if !defined(CONFIG_DM_PCI)
533#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
534#define CONFIG_PCI_INDIRECT_BRIDGE
535#define CONFIG_SYS_PCIE2_NAME "PCIe SLOT"
536#ifdef CONFIG_PHYS_64BIT
537#define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
538#else
539#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
540#endif
541#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
542#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
543#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
544
545#define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT"
546#ifdef CONFIG_PHYS_64BIT
547#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
548#else
549#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
550#endif
551#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
552#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
Li Yang5f999732011-07-26 09:50:46 -0500553#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
Hou Zhiqiang047860d2019-08-27 11:04:08 +0000554#endif
Li Yang5f999732011-07-26 09:50:46 -0500555
Li Yang5f999732011-07-26 09:50:46 -0500556#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Li Yang5f999732011-07-26 09:50:46 -0500557#endif /* CONFIG_PCI */
558
559#if defined(CONFIG_TSEC_ENET)
Li Yang5f999732011-07-26 09:50:46 -0500560#define CONFIG_TSEC1
561#define CONFIG_TSEC1_NAME "eTSEC1"
562#define CONFIG_TSEC2
563#define CONFIG_TSEC2_NAME "eTSEC2"
564#define CONFIG_TSEC3
565#define CONFIG_TSEC3_NAME "eTSEC3"
566
567#define TSEC1_PHY_ADDR 2
568#define TSEC2_PHY_ADDR 0
569#define TSEC3_PHY_ADDR 1
570
571#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
572#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
573#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
574
575#define TSEC1_PHYIDX 0
576#define TSEC2_PHYIDX 0
577#define TSEC3_PHYIDX 0
578
579#define CONFIG_ETHPRIME "eTSEC1"
580
Li Yang5f999732011-07-26 09:50:46 -0500581#define CONFIG_HAS_ETH0
582#define CONFIG_HAS_ETH1
583#define CONFIG_HAS_ETH2
584#endif /* CONFIG_TSEC_ENET */
585
586#ifdef CONFIG_QE
587/* QE microcode/firmware address */
Zhao Qiang83a90842014-03-21 16:21:44 +0800588#define CONFIG_SYS_QE_FW_ADDR 0xefec0000
Timur Tabi275f4bb2011-11-22 09:21:25 -0600589#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
Li Yang5f999732011-07-26 09:50:46 -0500590#endif /* CONFIG_QE */
591
Li Yang5f999732011-07-26 09:50:46 -0500592/*
593 * Environment
594 */
Tom Rini5cd7ece2019-11-18 20:02:10 -0500595#if defined(CONFIG_SDCARD)
Fabio Estevamae8c45e2012-01-11 09:20:50 +0000596#define CONFIG_FSL_FIXED_MMC_LOCATION
Miquel Raynald0935362019-10-03 19:50:03 +0200597#elif defined(CONFIG_MTD_RAW_NAND)
Tom Rini5cd7ece2019-11-18 20:02:10 -0500598#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
Ying Zhangb8b404d2013-09-06 17:30:58 +0800599#ifdef CONFIG_TPL_BUILD
Tom Rini5cd7ece2019-11-18 20:02:10 -0500600#define SPL_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
Ying Zhangb8b404d2013-09-06 17:30:58 +0800601#endif
Scott Wood6915cc22012-09-21 16:31:00 -0500602#elif defined(CONFIG_SYS_RAMBOOT)
Tom Rini5cd7ece2019-11-18 20:02:10 -0500603#define SPL_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
Li Yang5f999732011-07-26 09:50:46 -0500604#endif
605
606#define CONFIG_LOADS_ECHO /* echo on for serial download */
607#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
608
609/*
Li Yang5f999732011-07-26 09:50:46 -0500610 * USB
611 */
612#define CONFIG_HAS_FSL_DR_USB
613
614#if defined(CONFIG_HAS_FSL_DR_USB)
Tom Riniceed5d22017-05-12 22:33:27 -0400615#ifdef CONFIG_USB_EHCI_HCD
Li Yang5f999732011-07-26 09:50:46 -0500616#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
617#define CONFIG_USB_EHCI_FSL
Li Yang5f999732011-07-26 09:50:46 -0500618#endif
619#endif
620
York Sun06732382016-11-17 13:53:33 -0800621#if defined(CONFIG_TARGET_P1020RDB_PD)
ramneek mehresh3ca2b9a2014-05-13 15:36:07 +0530622#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
623#endif
624
Li Yang5f999732011-07-26 09:50:46 -0500625#ifdef CONFIG_MMC
Li Yang5f999732011-07-26 09:50:46 -0500626#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
Li Yang5f999732011-07-26 09:50:46 -0500627#endif
628
Li Yang5f999732011-07-26 09:50:46 -0500629#undef CONFIG_WATCHDOG /* watchdog disabled */
630
631/*
632 * Miscellaneous configurable options
633 */
Li Yang5f999732011-07-26 09:50:46 -0500634#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Li Yang5f999732011-07-26 09:50:46 -0500635
636/*
637 * For booting Linux, the board info and command line data
638 * have to be in the first 64 MB of memory, since this is
639 * the maximum mapped by the Linux kernel during initialization.
640 */
641#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/
642#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
643
644#if defined(CONFIG_CMD_KGDB)
645#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
Li Yang5f999732011-07-26 09:50:46 -0500646#endif
647
648/*
649 * Environment Configuration
650 */
Mario Six790d8442018-03-28 14:38:20 +0200651#define CONFIG_HOSTNAME "unknown"
Joe Hershberger257ff782011-10-13 13:03:47 +0000652#define CONFIG_ROOTPATH "/opt/nfsroot"
Joe Hershbergere4da2482011-10-13 13:03:48 +0000653#define CONFIG_BOOTFILE "uImage"
Li Yang5f999732011-07-26 09:50:46 -0500654#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
655
656/* default location for tftp and bootm */
657#define CONFIG_LOADADDR 1000000
658
Li Yang5f999732011-07-26 09:50:46 -0500659#ifdef __SW_BOOT_NOR
660#define __NOR_RST_CMD \
661norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \
662i2c mw 18 3 __SW_BOOT_MASK 1; reset
663#endif
664#ifdef __SW_BOOT_SPI
665#define __SPI_RST_CMD \
666spiboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SPI 1; \
667i2c mw 18 3 __SW_BOOT_MASK 1; reset
668#endif
669#ifdef __SW_BOOT_SD
670#define __SD_RST_CMD \
671sdboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SD 1; \
672i2c mw 18 3 __SW_BOOT_MASK 1; reset
673#endif
674#ifdef __SW_BOOT_NAND
675#define __NAND_RST_CMD \
676nandboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NAND 1; \
677i2c mw 18 3 __SW_BOOT_MASK 1; reset
678#endif
679#ifdef __SW_BOOT_PCIE
680#define __PCIE_RST_CMD \
681pciboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_PCIE 1; \
682i2c mw 18 3 __SW_BOOT_MASK 1; reset
683#endif
684
685#define CONFIG_EXTRA_ENV_SETTINGS \
686"netdev=eth0\0" \
Marek Vasut0b3176c2012-09-23 17:41:24 +0200687"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
Li Yang5f999732011-07-26 09:50:46 -0500688"loadaddr=1000000\0" \
689"bootfile=uImage\0" \
690"tftpflash=tftpboot $loadaddr $uboot; " \
Marek Vasut0b3176c2012-09-23 17:41:24 +0200691 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
692 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
693 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
694 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
695 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
Li Yang5f999732011-07-26 09:50:46 -0500696"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \
697"consoledev=ttyS0\0" \
698"ramdiskaddr=2000000\0" \
699"ramdiskfile=rootfs.ext2.gz.uboot\0" \
Scott Woodb7f4b852016-07-19 17:52:06 -0500700"fdtaddr=1e00000\0" \
Li Yang5f999732011-07-26 09:50:46 -0500701"bdev=sda1\0" \
702"jffs2nor=mtdblock3\0" \
703"norbootaddr=ef080000\0" \
704"norfdtaddr=ef040000\0" \
705"jffs2nand=mtdblock9\0" \
706"nandbootaddr=100000\0" \
707"nandfdtaddr=80000\0" \
708"ramdisk_size=120000\0" \
709"map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \
710"map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \
Hou Zhiqiang0bbc8692020-07-16 18:09:17 +0800711__stringify(__VSCFW_ADDR)"\0" \
Marek Vasut0b3176c2012-09-23 17:41:24 +0200712__stringify(__NOR_RST_CMD)"\0" \
713__stringify(__SPI_RST_CMD)"\0" \
714__stringify(__SD_RST_CMD)"\0" \
715__stringify(__NAND_RST_CMD)"\0" \
716__stringify(__PCIE_RST_CMD)"\0"
Li Yang5f999732011-07-26 09:50:46 -0500717
718#define CONFIG_NFSBOOTCOMMAND \
719"setenv bootargs root=/dev/nfs rw " \
720"nfsroot=$serverip:$rootpath " \
721"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
722"console=$consoledev,$baudrate $othbootargs;" \
723"tftp $loadaddr $bootfile;" \
724"tftp $fdtaddr $fdtfile;" \
725"bootm $loadaddr - $fdtaddr"
726
727#define CONFIG_HDBOOT \
728"setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
729"console=$consoledev,$baudrate $othbootargs;" \
730"usb start;" \
731"ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
732"ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
733"bootm $loadaddr - $fdtaddr"
734
735#define CONFIG_USB_FAT_BOOT \
736"setenv bootargs root=/dev/ram rw " \
737"console=$consoledev,$baudrate $othbootargs " \
738"ramdisk_size=$ramdisk_size;" \
739"usb start;" \
740"fatload usb 0:2 $loadaddr $bootfile;" \
741"fatload usb 0:2 $fdtaddr $fdtfile;" \
742"fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
743"bootm $loadaddr $ramdiskaddr $fdtaddr"
744
745#define CONFIG_USB_EXT2_BOOT \
746"setenv bootargs root=/dev/ram rw " \
747"console=$consoledev,$baudrate $othbootargs " \
748"ramdisk_size=$ramdisk_size;" \
749"usb start;" \
750"ext2load usb 0:4 $loadaddr $bootfile;" \
751"ext2load usb 0:4 $fdtaddr $fdtfile;" \
752"ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
753"bootm $loadaddr $ramdiskaddr $fdtaddr"
754
755#define CONFIG_NORBOOT \
756"setenv bootargs root=/dev/$jffs2nor rw " \
757"console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
758"bootm $norbootaddr - $norfdtaddr"
759
760#define CONFIG_RAMBOOTCOMMAND \
761"setenv bootargs root=/dev/ram rw " \
762"console=$consoledev,$baudrate $othbootargs " \
763"ramdisk_size=$ramdisk_size;" \
764"tftp $ramdiskaddr $ramdiskfile;" \
765"tftp $loadaddr $bootfile;" \
766"tftp $fdtaddr $fdtfile;" \
767"bootm $loadaddr $ramdiskaddr $fdtaddr"
768
769#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
770
771#endif /* __CONFIG_H */