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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Kumar Gala3ab0b2d2008-08-12 11:13:08 -05002/*
Kumar Galaa9db4ec2011-01-11 00:52:35 -06003 * Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc.
Kumar Gala3ab0b2d2008-08-12 11:13:08 -05004 */
5
6/*
7 * mpc8572ds board configuration file
8 *
9 */
10#ifndef __CONFIG_H
11#define __CONFIG_H
12
Simon Glassfb64e362020-05-10 11:40:09 -060013#include <linux/stringify.h>
14
Kumar Galaf6f382b2010-05-21 04:05:14 -050015#include "../board/freescale/common/ics307_clk.h"
16
Kumar Galae727a362011-01-12 02:48:53 -060017#ifndef CONFIG_RESET_VECTOR_ADDRESS
18#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
19#endif
20
Kumar Gala90a535b2010-11-12 08:22:01 -060021#ifndef CONFIG_SYS_MONITOR_BASE
22#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
23#endif
24
Kumar Gala3ab0b2d2008-08-12 11:13:08 -050025/* High Level Configuration Options */
Kumar Gala3ab0b2d2008-08-12 11:13:08 -050026
Robert P. J. Daya8099812016-05-03 19:52:49 -040027#define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */
28#define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */
29#define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */
Kumar Gala3ab0b2d2008-08-12 11:13:08 -050030#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
Gabor Juhosb4458732013-05-30 07:06:12 +000031#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
Kumar Gala7738d5c2008-10-21 11:33:58 -050032#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
Kumar Gala3ab0b2d2008-08-12 11:13:08 -050033
Kumar Galaf6f382b2010-05-21 04:05:14 -050034#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
35#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() /* ddrclk for MPC85xx */
Haiying Wangbcf35e52008-10-03 12:37:41 -040036#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
Kumar Gala3ab0b2d2008-08-12 11:13:08 -050037
38/*
39 * These can be toggled for performance analysis, otherwise use default.
40 */
41#define CONFIG_L2_CACHE /* toggle L2 cache */
42#define CONFIG_BTB /* toggle branch predition */
Kumar Gala3ab0b2d2008-08-12 11:13:08 -050043
44#define CONFIG_ENABLE_36BIT_PHYS 1
45
Kumar Gala3ab0b2d2008-08-12 11:13:08 -050046/*
Kumar Gala90a535b2010-11-12 08:22:01 -060047 * Config the L2 Cache as L2 SRAM
48 */
49#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
50#ifdef CONFIG_PHYS_64BIT
51#define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull
52#else
53#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
54#endif
55#define CONFIG_SYS_L2_SIZE (512 << 10)
56#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
57
Timur Tabid8f341c2011-08-04 18:03:41 -050058#define CONFIG_SYS_CCSRBAR 0xffe00000
59#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
Kumar Gala3ab0b2d2008-08-12 11:13:08 -050060
Kumar Gala842aa5b2011-11-09 09:10:49 -060061#if defined(CONFIG_NAND_SPL)
Timur Tabid8f341c2011-08-04 18:03:41 -050062#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
Kumar Gala90a535b2010-11-12 08:22:01 -060063#endif
64
Kumar Gala3ab0b2d2008-08-12 11:13:08 -050065/* DDR Setup */
Kumar Gala6630ffb2009-02-06 09:56:35 -060066#define CONFIG_VERY_BIG_RAM
Kumar Gala3ab0b2d2008-08-12 11:13:08 -050067#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
68#define CONFIG_DDR_SPD
Kumar Gala3ab0b2d2008-08-12 11:13:08 -050069
York Sun5e8435a2011-01-25 21:51:29 -080070#define CONFIG_DDR_ECC
Dave Liud3ca1242008-10-28 17:53:38 +080071#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
Kumar Gala3ab0b2d2008-08-12 11:13:08 -050072#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
73
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020074#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
75#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
Kumar Gala3ab0b2d2008-08-12 11:13:08 -050076
Kumar Gala3ab0b2d2008-08-12 11:13:08 -050077#define CONFIG_DIMM_SLOTS_PER_CTLR 1
78#define CONFIG_CHIP_SELECTS_PER_CTRL 2
79
80/* I2C addresses of SPD EEPROMs */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020081#define CONFIG_SYS_SPD_BUS_NUM 1 /* SPD EEPROMS locate on I2C bus 1 */
Kumar Gala3ab0b2d2008-08-12 11:13:08 -050082#define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */
83#define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 1 DIMM 0 */
84
85/* These are used when DDR doesn't use SPD. */
Dave Liu6b78b162008-11-28 20:16:58 +080086#define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */
87#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F
88#define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */
89#define CONFIG_SYS_DDR_TIMING_3 0x00020000
90#define CONFIG_SYS_DDR_TIMING_0 0x00260802
91#define CONFIG_SYS_DDR_TIMING_1 0x626b2634
92#define CONFIG_SYS_DDR_TIMING_2 0x062874cf
93#define CONFIG_SYS_DDR_MODE_1 0x00440462
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020094#define CONFIG_SYS_DDR_MODE_2 0x00000000
Dave Liu6b78b162008-11-28 20:16:58 +080095#define CONFIG_SYS_DDR_INTERVAL 0x0c300100
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020096#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
Dave Liu6b78b162008-11-28 20:16:58 +080097#define CONFIG_SYS_DDR_CLK_CTRL 0x00800000
98#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020099#define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
Dave Liu6b78b162008-11-28 20:16:58 +0800100#define CONFIG_SYS_DDR_CONTROL 0xc3000008 /* Type = DDR2 */
101#define CONFIG_SYS_DDR_CONTROL2 0x24400000
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500102
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200103#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
104#define CONFIG_SYS_DDR_ERR_DIS 0x00000000
105#define CONFIG_SYS_DDR_SBE 0x00010000
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500106
107/*
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500108 * Make sure required options are set
109 */
110#ifndef CONFIG_SPD_EEPROM
111#error ("CONFIG_SPD_EEPROM is required")
112#endif
113
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500114/*
115 * Memory map
116 *
117 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
118 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
119 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
120 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
121 *
122 * Localbus cacheable (TBD)
123 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
124 *
125 * Localbus non-cacheable
126 * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable
127 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable
Wolfgang Denk82f15f32008-11-02 16:14:22 +0100128 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500129 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0
130 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
131 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
132 */
133
134/*
135 * Local Bus Definitions
136 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200137#define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */
Kumar Galae0f97412009-01-23 14:22:14 -0600138#ifdef CONFIG_PHYS_64BIT
139#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
140#else
Kumar Gala4be8b572008-12-02 14:19:34 -0600141#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
Kumar Galae0f97412009-01-23 14:22:14 -0600142#endif
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500143
Kumar Gala90a535b2010-11-12 08:22:01 -0600144#define CONFIG_FLASH_BR_PRELIM \
Timur Tabib56570c2012-07-06 07:39:26 +0000145 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V)
Kumar Gala90a535b2010-11-12 08:22:01 -0600146#define CONFIG_FLASH_OR_PRELIM 0xf8000ff7
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500147
Kumar Gala4be8b572008-12-02 14:19:34 -0600148#define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
149#define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500150
Kumar Galae0f97412009-01-23 14:22:14 -0600151#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200152#define CONFIG_SYS_FLASH_QUIET_TEST
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500153#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
154
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200155#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
156#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
157#undef CONFIG_SYS_FLASH_CHECKSUM
158#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
159#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500160
Kumar Gala90a535b2010-11-12 08:22:01 -0600161#undef CONFIG_SYS_RAMBOOT
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500162
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200163#define CONFIG_SYS_FLASH_EMPTY_INFO
164#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500165
Kumar Gala362b9982010-11-19 08:53:25 -0600166#define CONFIG_HWCONFIG /* enable hwconfig */
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500167#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
168#define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
Kumar Galae0f97412009-01-23 14:22:14 -0600169#ifdef CONFIG_PHYS_64BIT
170#define PIXIS_BASE_PHYS 0xfffdf0000ull
171#else
Kumar Gala0f492b42008-12-02 14:19:33 -0600172#define PIXIS_BASE_PHYS PIXIS_BASE
Kumar Galae0f97412009-01-23 14:22:14 -0600173#endif
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500174
Kumar Gala0f492b42008-12-02 14:19:33 -0600175#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200176#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500177
178#define PIXIS_ID 0x0 /* Board ID at offset 0 */
179#define PIXIS_VER 0x1 /* Board version at offset 1 */
180#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
181#define PIXIS_CSR 0x3 /* PIXIS General control/status register */
182#define PIXIS_RST 0x4 /* PIXIS Reset Control register */
183#define PIXIS_PWR 0x5 /* PIXIS Power status register */
184#define PIXIS_AUX 0x6 /* Auxiliary 1 register */
185#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
186#define PIXIS_AUX2 0x8 /* Auxiliary 2 register */
187#define PIXIS_VCTL 0x10 /* VELA Control Register */
188#define PIXIS_VSTAT 0x11 /* VELA Status Register */
189#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
190#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
191#define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */
192#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
Kumar Galae21db032009-07-14 22:42:01 -0500193#define PIXIS_VBOOT_LBMAP 0xc0 /* VBOOT - CFG_LBMAP */
194#define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */
195#define PIXIS_VBOOT_LBMAP_PJET 0x01 /* cfg_lbmap - boot from projet */
196#define PIXIS_VBOOT_LBMAP_NAND 0x02 /* cfg_lbmap - boot from NAND */
197#define PIXIS_VBOOT_LBMAP_NOR1 0x03 /* cfg_lbmap - boot from NOR 1 */
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500198#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
199#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
200#define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */
201#define PIXIS_VSYSCLK0 0x1C /* VELA SYSCLK0 Register */
202#define PIXIS_VSYSCLK1 0x1D /* VELA SYSCLK1 Register */
203#define PIXIS_VSYSCLK2 0x1E /* VELA SYSCLK2 Register */
204#define PIXIS_VDDRCLK0 0x1F /* VELA DDRCLK0 Register */
205#define PIXIS_VDDRCLK1 0x20 /* VELA DDRCLK1 Register */
206#define PIXIS_VDDRCLK2 0x21 /* VELA DDRCLK2 Register */
207#define PIXIS_VWATCH 0x24 /* Watchdog Register */
208#define PIXIS_LED 0x25 /* LED Register */
209
Kumar Gala90a535b2010-11-12 08:22:01 -0600210#define PIXIS_SPD_SYSCLK_MASK 0x7 /* SYSCLK option */
211
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500212/* old pixis referenced names */
213#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
214#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200215#define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0
Liu Yuc49bce42008-10-10 11:40:59 +0800216#define PIXIS_VSPEED2_TSEC1SER 0x8
217#define PIXIS_VSPEED2_TSEC2SER 0x4
218#define PIXIS_VSPEED2_TSEC3SER 0x2
219#define PIXIS_VSPEED2_TSEC4SER 0x1
220#define PIXIS_VCFGEN1_TSEC1SER 0x20
221#define PIXIS_VCFGEN1_TSEC2SER 0x20
222#define PIXIS_VCFGEN1_TSEC3SER 0x20
223#define PIXIS_VCFGEN1_TSEC4SER 0x20
224#define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER \
225 | PIXIS_VSPEED2_TSEC2SER \
226 | PIXIS_VSPEED2_TSEC3SER \
227 | PIXIS_VSPEED2_TSEC4SER)
228#define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER \
229 | PIXIS_VCFGEN1_TSEC2SER \
230 | PIXIS_VCFGEN1_TSEC3SER \
231 | PIXIS_VCFGEN1_TSEC4SER)
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500232
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200233#define CONFIG_SYS_INIT_RAM_LOCK 1
234#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200235#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500236
Wolfgang Denk0191e472010-10-26 14:34:52 +0200237#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200238#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500239
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200240#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
241#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500242
Kumar Gala90a535b2010-11-12 08:22:01 -0600243#ifndef CONFIG_NAND_SPL
Haiying Wang9fce13f2008-10-29 13:32:59 -0400244#define CONFIG_SYS_NAND_BASE 0xffa00000
Kumar Galae0f97412009-01-23 14:22:14 -0600245#ifdef CONFIG_PHYS_64BIT
246#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
247#else
Haiying Wang9fce13f2008-10-29 13:32:59 -0400248#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
Kumar Galae0f97412009-01-23 14:22:14 -0600249#endif
Kumar Gala90a535b2010-11-12 08:22:01 -0600250#else
251#define CONFIG_SYS_NAND_BASE 0xfff00000
252#ifdef CONFIG_PHYS_64BIT
253#define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull
254#else
255#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
256#endif
257#endif
258
Haiying Wang9fce13f2008-10-29 13:32:59 -0400259#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\
260 CONFIG_SYS_NAND_BASE + 0x40000, \
261 CONFIG_SYS_NAND_BASE + 0x80000,\
262 CONFIG_SYS_NAND_BASE + 0xC0000}
263#define CONFIG_SYS_MAX_NAND_DEVICE 4
Wolfgang Denk82f15f32008-11-02 16:14:22 +0100264#define CONFIG_NAND_FSL_ELBC 1
Haiying Wang9fce13f2008-10-29 13:32:59 -0400265#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
Prabhakar Kushwaha4d2ba172013-10-04 13:47:58 +0530266#define CONFIG_SYS_NAND_MAX_OOBFREE 5
267#define CONFIG_SYS_NAND_MAX_ECCPOS 56
Haiying Wang9fce13f2008-10-29 13:32:59 -0400268
Kumar Gala90a535b2010-11-12 08:22:01 -0600269/* NAND boot: 4K NAND loader config */
270#define CONFIG_SYS_NAND_SPL_SIZE 0x1000
271#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000)
272#define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR)
273#define CONFIG_SYS_NAND_U_BOOT_START \
274 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
275#define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
276#define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000)
277#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
278
Haiying Wang9fce13f2008-10-29 13:32:59 -0400279/* NAND flash config */
Matthew McClintock48aab142011-04-05 14:39:33 -0500280#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
Wolfgang Denk82f15f32008-11-02 16:14:22 +0100281 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
282 | BR_PS_8 /* Port Size = 8 bit */ \
283 | BR_MS_FCM /* MSEL = FCM */ \
284 | BR_V) /* valid */
Matthew McClintock48aab142011-04-05 14:39:33 -0500285#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
Wolfgang Denk82f15f32008-11-02 16:14:22 +0100286 | OR_FCM_PGS /* Large Page*/ \
287 | OR_FCM_CSCT \
288 | OR_FCM_CST \
289 | OR_FCM_CHT \
290 | OR_FCM_SCY_1 \
291 | OR_FCM_TRLX \
292 | OR_FCM_EHTR)
Haiying Wang9fce13f2008-10-29 13:32:59 -0400293
Kumar Gala90a535b2010-11-12 08:22:01 -0600294#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
295#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
Matthew McClintock48aab142011-04-05 14:39:33 -0500296#define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
297#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
Timur Tabib56570c2012-07-06 07:39:26 +0000298#define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \
Wolfgang Denk82f15f32008-11-02 16:14:22 +0100299 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
300 | BR_PS_8 /* Port Size = 8 bit */ \
301 | BR_MS_FCM /* MSEL = FCM */ \
302 | BR_V) /* valid */
Matthew McClintock48aab142011-04-05 14:39:33 -0500303#define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
Timur Tabib56570c2012-07-06 07:39:26 +0000304#define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000)\
Wolfgang Denk82f15f32008-11-02 16:14:22 +0100305 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
306 | BR_PS_8 /* Port Size = 8 bit */ \
307 | BR_MS_FCM /* MSEL = FCM */ \
308 | BR_V) /* valid */
Matthew McClintock48aab142011-04-05 14:39:33 -0500309#define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
Haiying Wang9fce13f2008-10-29 13:32:59 -0400310
Timur Tabib56570c2012-07-06 07:39:26 +0000311#define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000)\
Wolfgang Denk82f15f32008-11-02 16:14:22 +0100312 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
313 | BR_PS_8 /* Port Size = 8 bit */ \
314 | BR_MS_FCM /* MSEL = FCM */ \
315 | BR_V) /* valid */
Matthew McClintock48aab142011-04-05 14:39:33 -0500316#define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
Haiying Wang9fce13f2008-10-29 13:32:59 -0400317
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500318/* Serial Port - controlled on board with jumper J8
319 * open - index 2
320 * shorted - index 1
321 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200322#define CONFIG_SYS_NS16550_SERIAL
323#define CONFIG_SYS_NS16550_REG_SIZE 1
324#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Kumar Gala90a535b2010-11-12 08:22:01 -0600325#ifdef CONFIG_NAND_SPL
326#define CONFIG_NS16550_MIN_FUNCTIONS
327#endif
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500328
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200329#define CONFIG_SYS_BAUDRATE_TABLE \
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500330 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
331
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200332#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
333#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500334
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500335/* I2C */
Heiko Schocherf2850742012-10-24 13:48:22 +0200336#define CONFIG_SYS_I2C
337#define CONFIG_SYS_I2C_FSL
338#define CONFIG_SYS_FSL_I2C_SPEED 400000
339#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
340#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
341#define CONFIG_SYS_FSL_I2C2_SPEED 400000
342#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
343#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
344#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200345#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500346
347/*
Haiying Wang374130f2008-10-03 11:47:30 -0400348 * I2C2 EEPROM
349 */
350#define CONFIG_ID_EEPROM
351#ifdef CONFIG_ID_EEPROM
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200352#define CONFIG_SYS_I2C_EEPROM_NXID
Haiying Wang374130f2008-10-03 11:47:30 -0400353#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200354#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
355#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
356#define CONFIG_SYS_EEPROM_BUS_NUM 1
Haiying Wang374130f2008-10-03 11:47:30 -0400357
358/*
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500359 * General PCI
360 * Memory space is mapped 1-1, but I/O space must start from 0.
361 */
362
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500363/* controller 3, direct to uli, tgtid 3, Base address 8000 */
Kumar Galad165dc52010-12-17 06:53:52 -0600364#define CONFIG_SYS_PCIE3_NAME "ULI"
Kumar Galaef43b6e2008-12-02 16:08:39 -0600365#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
Kumar Galae0f97412009-01-23 14:22:14 -0600366#ifdef CONFIG_PHYS_64BIT
Kumar Galae1cb3db2009-06-18 08:39:42 -0500367#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
Kumar Galae0f97412009-01-23 14:22:14 -0600368#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull
369#else
Kumar Gala2275d0e2009-02-09 22:03:05 -0600370#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
Kumar Galaef43b6e2008-12-02 16:08:39 -0600371#define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
Kumar Galae0f97412009-01-23 14:22:14 -0600372#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200373#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
Kumar Gala60ff4642008-12-02 16:08:40 -0600374#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
Kumar Gala64bb6d12008-12-02 16:08:37 -0600375#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
Kumar Galae0f97412009-01-23 14:22:14 -0600376#ifdef CONFIG_PHYS_64BIT
377#define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull
378#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200379#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000
Kumar Galae0f97412009-01-23 14:22:14 -0600380#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200381#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500382
383/* controller 2, Slot 2, tgtid 2, Base address 9000 */
Kumar Galad165dc52010-12-17 06:53:52 -0600384#define CONFIG_SYS_PCIE2_NAME "Slot 1"
Kumar Galaef43b6e2008-12-02 16:08:39 -0600385#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
Kumar Galae0f97412009-01-23 14:22:14 -0600386#ifdef CONFIG_PHYS_64BIT
Kumar Galae1cb3db2009-06-18 08:39:42 -0500387#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
Kumar Galae0f97412009-01-23 14:22:14 -0600388#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
389#else
Kumar Gala2275d0e2009-02-09 22:03:05 -0600390#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
Kumar Galaef43b6e2008-12-02 16:08:39 -0600391#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
Kumar Galae0f97412009-01-23 14:22:14 -0600392#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200393#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
Kumar Gala60ff4642008-12-02 16:08:40 -0600394#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
Kumar Gala64bb6d12008-12-02 16:08:37 -0600395#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
Kumar Galae0f97412009-01-23 14:22:14 -0600396#ifdef CONFIG_PHYS_64BIT
397#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
398#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200399#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
Kumar Galae0f97412009-01-23 14:22:14 -0600400#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200401#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500402
403/* controller 1, Slot 1, tgtid 1, Base address a000 */
Kumar Galad165dc52010-12-17 06:53:52 -0600404#define CONFIG_SYS_PCIE1_NAME "Slot 2"
Kumar Galaef43b6e2008-12-02 16:08:39 -0600405#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
Kumar Galae0f97412009-01-23 14:22:14 -0600406#ifdef CONFIG_PHYS_64BIT
Kumar Galae1cb3db2009-06-18 08:39:42 -0500407#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
Kumar Galae0f97412009-01-23 14:22:14 -0600408#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
409#else
Kumar Gala2275d0e2009-02-09 22:03:05 -0600410#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
Kumar Galaef43b6e2008-12-02 16:08:39 -0600411#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
Kumar Galae0f97412009-01-23 14:22:14 -0600412#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200413#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
Kumar Gala60ff4642008-12-02 16:08:40 -0600414#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
Kumar Gala64bb6d12008-12-02 16:08:37 -0600415#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
Kumar Galae0f97412009-01-23 14:22:14 -0600416#ifdef CONFIG_PHYS_64BIT
417#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull
418#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200419#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
Kumar Galae0f97412009-01-23 14:22:14 -0600420#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200421#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500422
423#if defined(CONFIG_PCI)
424
425/*PCIE video card used*/
Kumar Gala60ff4642008-12-02 16:08:40 -0600426#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500427
428/* video */
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500429
430#if defined(CONFIG_VIDEO)
431#define CONFIG_BIOSEMU
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500432#define CONFIG_ATI_RADEON_FB
433#define CONFIG_VIDEO_LOGO
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200434#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500435#endif
436
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500437
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500438#ifndef CONFIG_PCI_PNP
Kumar Gala64bb6d12008-12-02 16:08:37 -0600439 #define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS
440 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BUS
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500441 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */
442#endif
443
444#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500445
446#ifdef CONFIG_SCSI_AHCI
447#define CONFIG_SATA_ULI5288
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200448#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
449#define CONFIG_SYS_SCSI_MAX_LUN 1
450#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500451#endif /* SCSI */
452
453#endif /* CONFIG_PCI */
454
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500455#if defined(CONFIG_TSEC_ENET)
456
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500457#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
458#define CONFIG_TSEC1 1
459#define CONFIG_TSEC1_NAME "eTSEC1"
460#define CONFIG_TSEC2 1
461#define CONFIG_TSEC2_NAME "eTSEC2"
462#define CONFIG_TSEC3 1
463#define CONFIG_TSEC3_NAME "eTSEC3"
464#define CONFIG_TSEC4 1
465#define CONFIG_TSEC4_NAME "eTSEC4"
466
Liu Yuc49bce42008-10-10 11:40:59 +0800467#define CONFIG_PIXIS_SGMII_CMD
468#define CONFIG_FSL_SGMII_RISER 1
469#define SGMII_RISER_PHY_OFFSET 0x1c
470
471#ifdef CONFIG_FSL_SGMII_RISER
472#define CONFIG_SYS_TBIPA_VALUE 0x10 /* avoid conflict with eTSEC4 paddr */
473#endif
474
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500475#define TSEC1_PHY_ADDR 0
476#define TSEC2_PHY_ADDR 1
477#define TSEC3_PHY_ADDR 2
478#define TSEC4_PHY_ADDR 3
479
480#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
481#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
482#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
483#define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
484
485#define TSEC1_PHYIDX 0
486#define TSEC2_PHYIDX 0
487#define TSEC3_PHYIDX 0
488#define TSEC4_PHYIDX 0
489
490#define CONFIG_ETHPRIME "eTSEC1"
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500491#endif /* CONFIG_TSEC_ENET */
492
493/*
494 * Environment
495 */
Kumar Gala90a535b2010-11-12 08:22:01 -0600496
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500497#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200498#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500499
500/*
Zhao Chenhui36f15a82011-03-04 16:31:41 +0800501 * USB
502 */
Zhao Chenhui36f15a82011-03-04 16:31:41 +0800503
Tom Riniceed5d22017-05-12 22:33:27 -0400504#ifdef CONFIG_USB_EHCI_HCD
Zhao Chenhui36f15a82011-03-04 16:31:41 +0800505#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
Zhao Chenhui36f15a82011-03-04 16:31:41 +0800506#define CONFIG_PCI_EHCI_DEVICE 0
Zhao Chenhui36f15a82011-03-04 16:31:41 +0800507#endif
508
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500509#undef CONFIG_WATCHDOG /* watchdog disabled */
510
511/*
512 * Miscellaneous configurable options
513 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200514#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500515
516/*
517 * For booting Linux, the board info and command line data
Kumar Gala39ffcc12011-04-28 10:13:41 -0500518 * have to be in the first 64 MB of memory, since this is
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500519 * the maximum mapped by the Linux kernel during initialization.
520 */
Kumar Gala39ffcc12011-04-28 10:13:41 -0500521#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
522#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500523
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500524#if defined(CONFIG_CMD_KGDB)
525#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500526#endif
527
528/*
529 * Environment Configuration
530 */
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500531#if defined(CONFIG_TSEC_ENET)
532#define CONFIG_HAS_ETH0
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500533#define CONFIG_HAS_ETH1
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500534#define CONFIG_HAS_ETH2
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500535#define CONFIG_HAS_ETH3
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500536#endif
537
538#define CONFIG_IPADDR 192.168.1.254
539
Mario Six790d8442018-03-28 14:38:20 +0200540#define CONFIG_HOSTNAME "unknown"
Joe Hershberger257ff782011-10-13 13:03:47 +0000541#define CONFIG_ROOTPATH "/opt/nfsroot"
Joe Hershbergere4da2482011-10-13 13:03:48 +0000542#define CONFIG_BOOTFILE "uImage"
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500543#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
544
545#define CONFIG_SERVERIP 192.168.1.1
546#define CONFIG_GATEWAYIP 192.168.1.1
547#define CONFIG_NETMASK 255.255.255.0
548
549/* default location for tftp and bootm */
550#define CONFIG_LOADADDR 1000000
551
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500552#define CONFIG_EXTRA_ENV_SETTINGS \
Hongtao Jia39bb2f22012-12-20 19:36:12 +0000553"hwconfig=fsl_ddr:ctlr_intlv=bank,bank_intlv=cs0_cs1,ecc=off\0" \
Marek Vasut0b3176c2012-09-23 17:41:24 +0200554"netdev=eth0\0" \
555"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
556"tftpflash=tftpboot $loadaddr $uboot; " \
557 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
558 " +$filesize; " \
559 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
560 " +$filesize; " \
561 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
562 " $filesize; " \
563 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
564 " +$filesize; " \
565 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
566 " $filesize\0" \
567"consoledev=ttyS0\0" \
568"ramdiskaddr=2000000\0" \
569"ramdiskfile=8572ds/ramdisk.uboot\0" \
Scott Woodb7f4b852016-07-19 17:52:06 -0500570"fdtaddr=1e00000\0" \
Marek Vasut0b3176c2012-09-23 17:41:24 +0200571"fdtfile=8572ds/mpc8572ds.dtb\0" \
572"bdev=sda3\0"
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500573
574#define CONFIG_HDBOOT \
575 "setenv bootargs root=/dev/$bdev rw " \
576 "console=$consoledev,$baudrate $othbootargs;" \
577 "tftp $loadaddr $bootfile;" \
578 "tftp $fdtaddr $fdtfile;" \
579 "bootm $loadaddr - $fdtaddr"
580
581#define CONFIG_NFSBOOTCOMMAND \
582 "setenv bootargs root=/dev/nfs rw " \
583 "nfsroot=$serverip:$rootpath " \
584 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
585 "console=$consoledev,$baudrate $othbootargs;" \
586 "tftp $loadaddr $bootfile;" \
587 "tftp $fdtaddr $fdtfile;" \
588 "bootm $loadaddr - $fdtaddr"
589
590#define CONFIG_RAMBOOTCOMMAND \
591 "setenv bootargs root=/dev/ram rw " \
592 "console=$consoledev,$baudrate $othbootargs;" \
593 "tftp $ramdiskaddr $ramdiskfile;" \
594 "tftp $loadaddr $bootfile;" \
595 "tftp $fdtaddr $fdtfile;" \
596 "bootm $loadaddr $ramdiskaddr $fdtaddr"
597
598#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
599
600#endif /* __CONFIG_H */