blob: 971f76f1cabe3c67152fd9aac94dcce8a37ed864 [file] [log] [blame]
Michal Simek1a79c272018-03-28 15:43:51 +02001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * dts file for Xilinx ZynqMP ZCU106
4 *
Michal Simek4f1b7f62020-02-18 08:38:06 +01005 * (C) Copyright 2016 - 2020, Xilinx, Inc.
Michal Simek1a79c272018-03-28 15:43:51 +02006 *
7 * Michal Simek <michal.simek@xilinx.com>
8 */
9
10/dts-v1/;
11
12#include "zynqmp.dtsi"
13#include "zynqmp-clk-ccf.dtsi"
14#include <dt-bindings/input/input.h>
15#include <dt-bindings/gpio/gpio.h>
16#include <dt-bindings/phy/phy.h>
17
18/ {
19 model = "ZynqMP ZCU106 RevA";
20 compatible = "xlnx,zynqmp-zcu106-revA", "xlnx,zynqmp-zcu106", "xlnx,zynqmp";
21
22 aliases {
23 ethernet0 = &gem3;
24 gpio0 = &gpio;
25 i2c0 = &i2c0;
26 i2c1 = &i2c1;
27 mmc0 = &sdhci1;
28 rtc0 = &rtc;
29 serial0 = &uart0;
30 serial1 = &uart1;
31 serial2 = &dcc;
32 spi0 = &qspi;
33 usb0 = &usb0;
34 };
35
36 chosen {
37 bootargs = "earlycon";
38 stdout-path = "serial0:115200n8";
Michal Simek53b97e62019-01-18 09:10:39 +010039 xlnx,eeprom = &eeprom;
Michal Simek1a79c272018-03-28 15:43:51 +020040 };
41
42 memory@0 {
43 device_type = "memory";
44 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
45 };
46
47 gpio-keys {
48 compatible = "gpio-keys";
Michal Simek1a79c272018-03-28 15:43:51 +020049 autorepeat;
50 sw19 {
51 label = "sw19";
52 gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
53 linux,code = <KEY_DOWN>;
Sudeep Holla13104ce2018-10-24 12:45:40 +010054 wakeup-source;
Michal Simek1a79c272018-03-28 15:43:51 +020055 autorepeat;
56 };
57 };
58
59 leds {
60 compatible = "gpio-leds";
Michal Simek2ef53362018-11-08 10:06:53 +010061 heartbeat-led {
Michal Simek1a79c272018-03-28 15:43:51 +020062 label = "heartbeat";
63 gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
64 linux,default-trigger = "heartbeat";
65 };
66 };
Michal Simek2ec41ef2019-08-26 09:46:36 +020067
68 ina226-u76 {
69 compatible = "iio-hwmon";
70 io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>;
71 };
72 ina226-u77 {
73 compatible = "iio-hwmon";
74 io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;
75 };
76 ina226-u78 {
77 compatible = "iio-hwmon";
78 io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>;
79 };
80 ina226-u87 {
81 compatible = "iio-hwmon";
82 io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>;
83 };
84 ina226-u85 {
85 compatible = "iio-hwmon";
86 io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>;
87 };
88 ina226-u86 {
89 compatible = "iio-hwmon";
90 io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>;
91 };
92 ina226-u93 {
93 compatible = "iio-hwmon";
94 io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>;
95 };
96 ina226-u88 {
97 compatible = "iio-hwmon";
98 io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>;
99 };
100 ina226-u15 {
101 compatible = "iio-hwmon";
102 io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>;
103 };
104 ina226-u92 {
105 compatible = "iio-hwmon";
106 io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>;
107 };
108 ina226-u79 {
109 compatible = "iio-hwmon";
110 io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;
111 };
112 ina226-u81 {
113 compatible = "iio-hwmon";
114 io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>;
115 };
116 ina226-u80 {
117 compatible = "iio-hwmon";
118 io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>;
119 };
120 ina226-u84 {
121 compatible = "iio-hwmon";
122 io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>;
123 };
124 ina226-u16 {
125 compatible = "iio-hwmon";
126 io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>;
127 };
128 ina226-u65 {
129 compatible = "iio-hwmon";
130 io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;
131 };
132 ina226-u74 {
133 compatible = "iio-hwmon";
134 io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>;
135 };
136 ina226-u75 {
137 compatible = "iio-hwmon";
138 io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;
139 };
Michal Simek958c0e92020-11-26 14:25:02 +0100140
141 /* 48MHz reference crystal */
142 ref48: ref48M {
143 compatible = "fixed-clock";
144 #clock-cells = <0>;
145 clock-frequency = <48000000>;
146 };
147
148 refhdmi: refhdmi {
149 compatible = "fixed-clock";
150 #clock-cells = <0>;
151 clock-frequency = <114285000>;
152 };
Michal Simek1a79c272018-03-28 15:43:51 +0200153};
154
155&can1 {
156 status = "okay";
157};
158
159&dcc {
160 status = "okay";
Michal Simek958c0e92020-11-26 14:25:02 +0100161};
162
163&zynqmp_dpdma {
164 status = "okay";
165};
166
167&zynqmp_dpsub {
168 status = "okay";
169 phy-names = "dp-phy0", "dp-phy1";
170 phys = <&psgtr 1 PHY_TYPE_DP 0 3>,
171 <&psgtr 0 PHY_TYPE_DP 1 3>;
Michal Simek1a79c272018-03-28 15:43:51 +0200172};
173
Michal Simek958c0e92020-11-26 14:25:02 +0100174/* fpd_dma clk 667MHz, lpd_dma 500MHz */
Michal Simek1a79c272018-03-28 15:43:51 +0200175&fpd_dma_chan1 {
176 status = "okay";
177};
178
179&fpd_dma_chan2 {
180 status = "okay";
181};
182
183&fpd_dma_chan3 {
184 status = "okay";
185};
186
187&fpd_dma_chan4 {
188 status = "okay";
189};
190
191&fpd_dma_chan5 {
192 status = "okay";
193};
194
195&fpd_dma_chan6 {
196 status = "okay";
197};
198
199&fpd_dma_chan7 {
200 status = "okay";
201};
202
203&fpd_dma_chan8 {
204 status = "okay";
205};
206
207&gem3 {
208 status = "okay";
209 phy-handle = <&phy0>;
210 phy-mode = "rgmii-id";
Michal Simek393decf2019-08-08 12:44:22 +0200211 phy0: ethernet-phy@c {
Michal Simek1a79c272018-03-28 15:43:51 +0200212 reg = <0xc>;
213 ti,rx-internal-delay = <0x8>;
214 ti,tx-internal-delay = <0xa>;
215 ti,fifo-depth = <0x1>;
Harini Katakam991a1612019-02-13 17:02:21 +0530216 ti,dp83867-rxctrl-strap-quirk;
Michal Simek1a79c272018-03-28 15:43:51 +0200217 };
218};
219
220&gpio {
221 status = "okay";
222};
223
224&gpu {
225 status = "okay";
226};
227
228&i2c0 {
229 status = "okay";
230 clock-frequency = <400000>;
231
232 tca6416_u97: gpio@20 {
233 compatible = "ti,tca6416";
234 reg = <0x20>;
235 gpio-controller; /* interrupt not connected */
236 #gpio-cells = <2>;
237 /*
238 * IRQ not connected
239 * Lines:
240 * 0 - SFP_SI5328_INT_ALM
241 * 1 - HDMI_SI5328_INT_ALM
242 * 5 - IIC_MUX_RESET_B
243 * 6 - GEM3_EXP_RESET_B
244 * 10 - FMC_HPC0_PRSNT_M2C_B
245 * 11 - FMC_HPC1_PRSNT_M2C_B
246 * 2-4, 7, 12-17 - not connected
247 */
248 };
249
250 tca6416_u61: gpio@21 {
251 compatible = "ti,tca6416";
252 reg = <0x21>;
253 gpio-controller;
254 #gpio-cells = <2>;
255 /*
256 * IRQ not connected
257 * Lines:
258 * 0 - VCCPSPLL_EN
259 * 1 - MGTRAVCC_EN
260 * 2 - MGTRAVTT_EN
261 * 3 - VCCPSDDRPLL_EN
262 * 4 - MIO26_PMU_INPUT_LS
263 * 5 - PL_PMBUS_ALERT
264 * 6 - PS_PMBUS_ALERT
265 * 7 - MAXIM_PMBUS_ALERT
266 * 10 - PL_DDR4_VTERM_EN
267 * 11 - PL_DDR4_VPP_2V5_EN
268 * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON
269 * 13 - PS_DIMM_SUSPEND_EN
270 * 14 - PS_DDR4_VTERM_EN
271 * 15 - PS_DDR4_VPP_2V5_EN
272 * 16 - 17 - not connected
273 */
274 };
275
276 i2c-mux@75 { /* u60 */
277 compatible = "nxp,pca9544";
278 #address-cells = <1>;
279 #size-cells = <0>;
280 reg = <0x75>;
281 i2c@0 {
282 #address-cells = <1>;
283 #size-cells = <0>;
284 reg = <0>;
285 /* PS_PMBUS */
Michal Simek2ec41ef2019-08-26 09:46:36 +0200286 u76: ina226@40 { /* u76 */
Michal Simek1a79c272018-03-28 15:43:51 +0200287 compatible = "ti,ina226";
Michal Simek2ec41ef2019-08-26 09:46:36 +0200288 #io-channel-cells = <1>;
Michal Simek9df54d12019-08-26 10:18:13 +0200289 label = "ina226-u76";
Michal Simek1a79c272018-03-28 15:43:51 +0200290 reg = <0x40>;
291 shunt-resistor = <5000>;
292 };
Michal Simek2ec41ef2019-08-26 09:46:36 +0200293 u77: ina226@41 { /* u77 */
Michal Simek1a79c272018-03-28 15:43:51 +0200294 compatible = "ti,ina226";
Michal Simek2ec41ef2019-08-26 09:46:36 +0200295 #io-channel-cells = <1>;
Michal Simek9df54d12019-08-26 10:18:13 +0200296 label = "ina226-u77";
Michal Simek1a79c272018-03-28 15:43:51 +0200297 reg = <0x41>;
298 shunt-resistor = <5000>;
299 };
Michal Simek2ec41ef2019-08-26 09:46:36 +0200300 u78: ina226@42 { /* u78 */
Michal Simek1a79c272018-03-28 15:43:51 +0200301 compatible = "ti,ina226";
Michal Simek2ec41ef2019-08-26 09:46:36 +0200302 #io-channel-cells = <1>;
Michal Simek9df54d12019-08-26 10:18:13 +0200303 label = "ina226-u78";
Michal Simek1a79c272018-03-28 15:43:51 +0200304 reg = <0x42>;
305 shunt-resistor = <5000>;
306 };
Michal Simek2ec41ef2019-08-26 09:46:36 +0200307 u87: ina226@43 { /* u87 */
Michal Simek1a79c272018-03-28 15:43:51 +0200308 compatible = "ti,ina226";
Michal Simek2ec41ef2019-08-26 09:46:36 +0200309 #io-channel-cells = <1>;
Michal Simek9df54d12019-08-26 10:18:13 +0200310 label = "ina226-u87";
Michal Simek1a79c272018-03-28 15:43:51 +0200311 reg = <0x43>;
312 shunt-resistor = <5000>;
313 };
Michal Simek2ec41ef2019-08-26 09:46:36 +0200314 u85: ina226@44 { /* u85 */
Michal Simek1a79c272018-03-28 15:43:51 +0200315 compatible = "ti,ina226";
Michal Simek2ec41ef2019-08-26 09:46:36 +0200316 #io-channel-cells = <1>;
Michal Simek9df54d12019-08-26 10:18:13 +0200317 label = "ina226-u85";
Michal Simek1a79c272018-03-28 15:43:51 +0200318 reg = <0x44>;
319 shunt-resistor = <5000>;
320 };
Michal Simek2ec41ef2019-08-26 09:46:36 +0200321 u86: ina226@45 { /* u86 */
Michal Simek1a79c272018-03-28 15:43:51 +0200322 compatible = "ti,ina226";
Michal Simek2ec41ef2019-08-26 09:46:36 +0200323 #io-channel-cells = <1>;
Michal Simek9df54d12019-08-26 10:18:13 +0200324 label = "ina226-u86";
Michal Simek1a79c272018-03-28 15:43:51 +0200325 reg = <0x45>;
326 shunt-resistor = <5000>;
327 };
Michal Simek2ec41ef2019-08-26 09:46:36 +0200328 u93: ina226@46 { /* u93 */
Michal Simek1a79c272018-03-28 15:43:51 +0200329 compatible = "ti,ina226";
Michal Simek2ec41ef2019-08-26 09:46:36 +0200330 #io-channel-cells = <1>;
Michal Simek9df54d12019-08-26 10:18:13 +0200331 label = "ina226-u93";
Michal Simek1a79c272018-03-28 15:43:51 +0200332 reg = <0x46>;
333 shunt-resistor = <5000>;
334 };
Michal Simek2ec41ef2019-08-26 09:46:36 +0200335 u88: ina226@47 { /* u88 */
Michal Simek1a79c272018-03-28 15:43:51 +0200336 compatible = "ti,ina226";
Michal Simek2ec41ef2019-08-26 09:46:36 +0200337 #io-channel-cells = <1>;
Michal Simek9df54d12019-08-26 10:18:13 +0200338 label = "ina226-u88";
Michal Simek1a79c272018-03-28 15:43:51 +0200339 reg = <0x47>;
340 shunt-resistor = <5000>;
341 };
Michal Simek2ec41ef2019-08-26 09:46:36 +0200342 u15: ina226@4a { /* u15 */
Michal Simek1a79c272018-03-28 15:43:51 +0200343 compatible = "ti,ina226";
Michal Simek2ec41ef2019-08-26 09:46:36 +0200344 #io-channel-cells = <1>;
Michal Simek9df54d12019-08-26 10:18:13 +0200345 label = "ina226-u15";
Michal Simek1a79c272018-03-28 15:43:51 +0200346 reg = <0x4a>;
347 shunt-resistor = <5000>;
348 };
Michal Simek2ec41ef2019-08-26 09:46:36 +0200349 u92: ina226@4b { /* u92 */
Michal Simek1a79c272018-03-28 15:43:51 +0200350 compatible = "ti,ina226";
Michal Simek2ec41ef2019-08-26 09:46:36 +0200351 #io-channel-cells = <1>;
Michal Simek9df54d12019-08-26 10:18:13 +0200352 label = "ina226-u92";
Michal Simek1a79c272018-03-28 15:43:51 +0200353 reg = <0x4b>;
354 shunt-resistor = <5000>;
355 };
356 };
357 i2c@1 {
358 #address-cells = <1>;
359 #size-cells = <0>;
360 reg = <1>;
361 /* PL_PMBUS */
Michal Simek2ec41ef2019-08-26 09:46:36 +0200362 u79: ina226@40 { /* u79 */
Michal Simek1a79c272018-03-28 15:43:51 +0200363 compatible = "ti,ina226";
Michal Simek2ec41ef2019-08-26 09:46:36 +0200364 #io-channel-cells = <1>;
Michal Simek9df54d12019-08-26 10:18:13 +0200365 label = "ina226-u79";
Michal Simek1a79c272018-03-28 15:43:51 +0200366 reg = <0x40>;
367 shunt-resistor = <2000>;
368 };
Michal Simek2ec41ef2019-08-26 09:46:36 +0200369 u81: ina226@41 { /* u81 */
Michal Simek1a79c272018-03-28 15:43:51 +0200370 compatible = "ti,ina226";
Michal Simek2ec41ef2019-08-26 09:46:36 +0200371 #io-channel-cells = <1>;
Michal Simek9df54d12019-08-26 10:18:13 +0200372 label = "ina226-u81";
Michal Simek1a79c272018-03-28 15:43:51 +0200373 reg = <0x41>;
374 shunt-resistor = <5000>;
375 };
Michal Simek2ec41ef2019-08-26 09:46:36 +0200376 u80: ina226@42 { /* u80 */
Michal Simek1a79c272018-03-28 15:43:51 +0200377 compatible = "ti,ina226";
Michal Simek2ec41ef2019-08-26 09:46:36 +0200378 #io-channel-cells = <1>;
Michal Simek9df54d12019-08-26 10:18:13 +0200379 label = "ina226-u80";
Michal Simek1a79c272018-03-28 15:43:51 +0200380 reg = <0x42>;
381 shunt-resistor = <5000>;
382 };
Michal Simek2ec41ef2019-08-26 09:46:36 +0200383 u84: ina226@43 { /* u84 */
Michal Simek1a79c272018-03-28 15:43:51 +0200384 compatible = "ti,ina226";
Michal Simek2ec41ef2019-08-26 09:46:36 +0200385 #io-channel-cells = <1>;
Michal Simek9df54d12019-08-26 10:18:13 +0200386 label = "ina226-u84";
Michal Simek1a79c272018-03-28 15:43:51 +0200387 reg = <0x43>;
388 shunt-resistor = <5000>;
389 };
Michal Simek2ec41ef2019-08-26 09:46:36 +0200390 u16: ina226@44 { /* u16 */
Michal Simek1a79c272018-03-28 15:43:51 +0200391 compatible = "ti,ina226";
Michal Simek2ec41ef2019-08-26 09:46:36 +0200392 #io-channel-cells = <1>;
Michal Simek9df54d12019-08-26 10:18:13 +0200393 label = "ina226-u16";
Michal Simek1a79c272018-03-28 15:43:51 +0200394 reg = <0x44>;
395 shunt-resistor = <5000>;
396 };
Michal Simek2ec41ef2019-08-26 09:46:36 +0200397 u65: ina226@45 { /* u65 */
Michal Simek1a79c272018-03-28 15:43:51 +0200398 compatible = "ti,ina226";
Michal Simek2ec41ef2019-08-26 09:46:36 +0200399 #io-channel-cells = <1>;
Michal Simek9df54d12019-08-26 10:18:13 +0200400 label = "ina226-u65";
Michal Simek1a79c272018-03-28 15:43:51 +0200401 reg = <0x45>;
402 shunt-resistor = <5000>;
403 };
Michal Simek2ec41ef2019-08-26 09:46:36 +0200404 u74: ina226@46 { /* u74 */
Michal Simek1a79c272018-03-28 15:43:51 +0200405 compatible = "ti,ina226";
Michal Simek2ec41ef2019-08-26 09:46:36 +0200406 #io-channel-cells = <1>;
Michal Simek9df54d12019-08-26 10:18:13 +0200407 label = "ina226-u74";
Michal Simek1a79c272018-03-28 15:43:51 +0200408 reg = <0x46>;
409 shunt-resistor = <5000>;
410 };
Michal Simek2ec41ef2019-08-26 09:46:36 +0200411 u75: ina226@47 { /* u75 */
Michal Simek1a79c272018-03-28 15:43:51 +0200412 compatible = "ti,ina226";
Michal Simek2ec41ef2019-08-26 09:46:36 +0200413 #io-channel-cells = <1>;
Michal Simek9df54d12019-08-26 10:18:13 +0200414 label = "ina226-u75";
Michal Simek1a79c272018-03-28 15:43:51 +0200415 reg = <0x47>;
416 shunt-resistor = <5000>;
417 };
418 };
419 i2c@2 {
420 #address-cells = <1>;
421 #size-cells = <0>;
422 reg = <2>;
423 /* MAXIM_PMBUS - 00 */
424 max15301@a { /* u46 */
425 compatible = "maxim,max15301";
426 reg = <0xa>;
427 };
428 max15303@b { /* u4 */
429 compatible = "maxim,max15303";
430 reg = <0xb>;
431 };
432 max15303@10 { /* u13 */
433 compatible = "maxim,max15303";
434 reg = <0x10>;
435 };
436 max15301@13 { /* u47 */
437 compatible = "maxim,max15301";
438 reg = <0x13>;
439 };
440 max15303@14 { /* u7 */
441 compatible = "maxim,max15303";
442 reg = <0x14>;
443 };
444 max15303@15 { /* u6 */
445 compatible = "maxim,max15303";
446 reg = <0x15>;
447 };
448 max15303@16 { /* u10 */
449 compatible = "maxim,max15303";
450 reg = <0x16>;
451 };
452 max15303@17 { /* u9 */
453 compatible = "maxim,max15303";
454 reg = <0x17>;
455 };
456 max15301@18 { /* u63 */
457 compatible = "maxim,max15301";
458 reg = <0x18>;
459 };
460 max15303@1a { /* u49 */
461 compatible = "maxim,max15303";
462 reg = <0x1a>;
463 };
464 max15303@1b { /* u8 */
465 compatible = "maxim,max15303";
466 reg = <0x1b>;
467 };
468 max15303@1d { /* u18 */
469 compatible = "maxim,max15303";
470 reg = <0x1d>;
471 };
472
473 max20751@72 { /* u95 */
474 compatible = "maxim,max20751";
475 reg = <0x72>;
476 };
477 max20751@73 { /* u96 */
478 compatible = "maxim,max20751";
479 reg = <0x73>;
480 };
481 };
482 /* Bus 3 is not connected */
483 };
484};
485
486&i2c1 {
487 status = "okay";
488 clock-frequency = <400000>;
489
490 /* PL i2c via PCA9306 - u45 */
491 i2c-mux@74 { /* u34 */
492 compatible = "nxp,pca9548";
493 #address-cells = <1>;
494 #size-cells = <0>;
495 reg = <0x74>;
496 i2c@0 {
497 #address-cells = <1>;
498 #size-cells = <0>;
499 reg = <0>;
500 /*
501 * IIC_EEPROM 1kB memory which uses 256B blocks
502 * where every block has different address.
503 * 0 - 256B address 0x54
504 * 256B - 512B address 0x55
505 * 512B - 768B address 0x56
506 * 768B - 1024B address 0x57
507 */
508 eeprom: eeprom@54 { /* u23 */
509 compatible = "atmel,24c08";
510 reg = <0x54>;
511 };
512 };
513 i2c@1 {
514 #address-cells = <1>;
515 #size-cells = <0>;
516 reg = <1>;
517 si5341: clock-generator@36 { /* SI5341 - u69 */
Michal Simek958c0e92020-11-26 14:25:02 +0100518 compatible = "silabs,si5341";
Michal Simek1a79c272018-03-28 15:43:51 +0200519 reg = <0x36>;
Michal Simek958c0e92020-11-26 14:25:02 +0100520 #clock-cells = <2>;
521 #address-cells = <1>;
522 #size-cells = <0>;
523 clocks = <&ref48>;
524 clock-names = "xtal";
525 clock-output-names = "si5341";
526
527 si5341_0: out@0 {
528 /* refclk0 for PS-GT, used for DP */
529 reg = <0>;
530 always-on;
531 };
532 si5341_2: out@2 {
533 /* refclk2 for PS-GT, used for USB3 */
534 reg = <2>;
535 always-on;
536 };
537 si5341_3: out@3 {
538 /* refclk3 for PS-GT, used for SATA */
539 reg = <3>;
540 always-on;
541 };
542 si5341_6: out@6 {
543 /* refclk6 PL CLK125 */
544 reg = <6>;
545 always-on;
546 };
547 si5341_7: out@7 {
548 /* refclk7 PL CLK74 */
549 reg = <7>;
550 always-on;
551 };
552 si5341_9: out@9 {
553 /* refclk9 used for PS_REF_CLK 33.3 MHz */
554 reg = <9>;
555 always-on;
556 };
Michal Simek1a79c272018-03-28 15:43:51 +0200557 };
558
559 };
560 i2c@2 {
561 #address-cells = <1>;
562 #size-cells = <0>;
563 reg = <2>;
564 si570_1: clock-generator@5d { /* USER SI570 - u42 */
565 #clock-cells = <0>;
566 compatible = "silabs,si570";
567 reg = <0x5d>;
568 temperature-stability = <50>;
569 factory-fout = <300000000>;
570 clock-frequency = <300000000>;
Michal Simek3cf07bf2018-07-18 12:10:02 +0200571 clock-output-names = "si570_user";
Michal Simek1a79c272018-03-28 15:43:51 +0200572 };
573 };
574 i2c@3 {
575 #address-cells = <1>;
576 #size-cells = <0>;
577 reg = <3>;
578 si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */
579 #clock-cells = <0>;
580 compatible = "silabs,si570";
581 reg = <0x5d>;
582 temperature-stability = <50>; /* copy from zc702 */
583 factory-fout = <156250000>;
584 clock-frequency = <148500000>;
Michal Simek3cf07bf2018-07-18 12:10:02 +0200585 clock-output-names = "si570_mgt";
Michal Simek1a79c272018-03-28 15:43:51 +0200586 };
587 };
588 i2c@4 {
589 #address-cells = <1>;
590 #size-cells = <0>;
591 reg = <4>;
592 si5328: clock-generator@69 {/* SI5328 - u20 */
Michal Simek1a79c272018-03-28 15:43:51 +0200593 reg = <0x69>;
Michal Simek958c0e92020-11-26 14:25:02 +0100594 /*
595 * Chip has interrupt present connected to PL
596 * interrupt-parent = <&>;
597 * interrupts = <>;
598 */
599 #address-cells = <1>;
600 #size-cells = <0>;
601 #clock-cells = <1>;
602 clocks = <&refhdmi>;
603 clock-names = "xtal";
604 clock-output-names = "si5328";
605
606 si5328_clk: clk0@0 {
607 reg = <0>;
608 clock-frequency = <27000000>;
609 };
Michal Simek1a79c272018-03-28 15:43:51 +0200610 };
611 };
612 i2c@5 {
613 #address-cells = <1>;
614 #size-cells = <0>;
615 reg = <5>; /* FAN controller */
616 temp@4c {/* lm96163 - u128 */
617 compatible = "national,lm96163";
618 reg = <0x4c>;
619 };
620 };
621 /* 6 - 7 unconnected */
622 };
623
624 i2c-mux@75 {
625 compatible = "nxp,pca9548"; /* u135 */
626 #address-cells = <1>;
627 #size-cells = <0>;
628 reg = <0x75>;
629
630 i2c@0 {
631 #address-cells = <1>;
632 #size-cells = <0>;
633 reg = <0>;
634 /* HPC0_IIC */
635 };
636 i2c@1 {
637 #address-cells = <1>;
638 #size-cells = <0>;
639 reg = <1>;
640 /* HPC1_IIC */
641 };
642 i2c@2 {
643 #address-cells = <1>;
644 #size-cells = <0>;
645 reg = <2>;
646 /* SYSMON */
647 };
648 i2c@3 {
649 #address-cells = <1>;
650 #size-cells = <0>;
651 reg = <3>;
652 /* DDR4 SODIMM */
Michal Simek1a79c272018-03-28 15:43:51 +0200653 };
654 i2c@4 {
655 #address-cells = <1>;
656 #size-cells = <0>;
657 reg = <4>;
658 /* SEP 3 */
659 };
660 i2c@5 {
661 #address-cells = <1>;
662 #size-cells = <0>;
663 reg = <5>;
664 /* SEP 2 */
665 };
666 i2c@6 {
667 #address-cells = <1>;
668 #size-cells = <0>;
669 reg = <6>;
670 /* SEP 1 */
671 };
672 i2c@7 {
673 #address-cells = <1>;
674 #size-cells = <0>;
675 reg = <7>;
676 /* SEP 0 */
677 };
678 };
679};
680
Michal Simek958c0e92020-11-26 14:25:02 +0100681&psgtr {
682 status = "okay";
683 /* nc, sata, usb3, dp */
684 clocks = <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>;
685 clock-names = "ref1", "ref2", "ref3";
686};
687
Michal Simek1a79c272018-03-28 15:43:51 +0200688&qspi {
689 status = "okay";
690 is-dual = <1>;
691 flash@0 {
Neil Armstronga009fa72019-02-10 10:16:20 +0000692 compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
Michal Simek1a79c272018-03-28 15:43:51 +0200693 #address-cells = <1>;
694 #size-cells = <1>;
695 reg = <0x0>;
696 spi-tx-bus-width = <1>;
697 spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
698 spi-max-frequency = <108000000>; /* Based on DC1 spec */
Michal Simek70fafdf2020-02-14 14:19:56 +0100699 partition@0 { /* for testing purpose */
Michal Simek1a79c272018-03-28 15:43:51 +0200700 label = "qspi-fsbl-uboot";
701 reg = <0x0 0x100000>;
702 };
Michal Simek70fafdf2020-02-14 14:19:56 +0100703 partition@100000 { /* for testing purpose */
Michal Simek1a79c272018-03-28 15:43:51 +0200704 label = "qspi-linux";
705 reg = <0x100000 0x500000>;
706 };
Michal Simek70fafdf2020-02-14 14:19:56 +0100707 partition@600000 { /* for testing purpose */
Michal Simek1a79c272018-03-28 15:43:51 +0200708 label = "qspi-device-tree";
709 reg = <0x600000 0x20000>;
710 };
Michal Simek70fafdf2020-02-14 14:19:56 +0100711 partition@620000 { /* for testing purpose */
Michal Simek1a79c272018-03-28 15:43:51 +0200712 label = "qspi-rootfs";
713 reg = <0x620000 0x5E0000>;
714 };
715 };
716};
717
718&rtc {
719 status = "okay";
720};
721
722&sata {
723 status = "okay";
724 /* SATA OOB timing settings */
725 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
726 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
727 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
728 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
729 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
730 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
731 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
732 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
733 phy-names = "sata-phy";
Michal Simek958c0e92020-11-26 14:25:02 +0100734 phys = <&psgtr 3 PHY_TYPE_SATA 1 1>;
Michal Simek1a79c272018-03-28 15:43:51 +0200735};
736
737/* SD1 with level shifter */
738&sdhci1 {
739 status = "okay";
Manish Naranie2ba0932020-02-13 23:37:30 -0700740 /*
741 * This property should be removed for supporting UHS mode
742 */
743 no-1-8-v;
Michal Simek3b662642020-07-22 17:42:43 +0200744 xlnx,mio-bank = <1>;
Michal Simek1a79c272018-03-28 15:43:51 +0200745};
746
Michal Simek1a79c272018-03-28 15:43:51 +0200747&uart0 {
748 status = "okay";
749};
750
751&uart1 {
752 status = "okay";
753};
754
755/* ULPI SMSC USB3320 */
756&usb0 {
757 status = "okay";
758};
759
760&dwc3_0 {
761 status = "okay";
762 dr_mode = "host";
763 snps,usb3_lpm_capable;
Michal Simek1a79c272018-03-28 15:43:51 +0200764};
765
766&watchdog0 {
767 status = "okay";
768};