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git01.mediatek.com / filogic / uboot / 2ec41ef56ed21d53df02e48c82de219606b8738e / . / arch / arm / dts / zynqmp-zcu106-revA.dts
blob: 1d452e8359090641c447f0f3788665defbdf119c [file] [log] [blame]
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * dts file for Xilinx ZynqMP ZCU106
4 *
5 * (C) Copyright 2016, Xilinx, Inc.
6 *
7 * Michal Simek <michal.simek@xilinx.com>
8 */
9
10/dts-v1/;
11
12#include "zynqmp.dtsi"
13#include "zynqmp-clk-ccf.dtsi"
14#include <dt-bindings/input/input.h>
15#include <dt-bindings/gpio/gpio.h>
16#include <dt-bindings/phy/phy.h>
17
18/ {
19 model = "ZynqMP ZCU106 RevA";
20 compatible = "xlnx,zynqmp-zcu106-revA", "xlnx,zynqmp-zcu106", "xlnx,zynqmp";
21
22 aliases {
23 ethernet0 = &gem3;
24 gpio0 = &gpio;
25 i2c0 = &i2c0;
26 i2c1 = &i2c1;
27 mmc0 = &sdhci1;
28 rtc0 = &rtc;
29 serial0 = &uart0;
30 serial1 = &uart1;
31 serial2 = &dcc;
32 spi0 = &qspi;
33 usb0 = &usb0;
34 };
35
36 chosen {
37 bootargs = "earlycon";
38 stdout-path = "serial0:115200n8";
Michal Simek53b97e62019-01-18 09:10:39 +0100[diff] [blame]39 xlnx,eeprom = &eeprom;
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]40 };
41
42 memory@0 {
43 device_type = "memory";
44 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
45 };
46
47 gpio-keys {
48 compatible = "gpio-keys";
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]49 autorepeat;
50 sw19 {
51 label = "sw19";
52 gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
53 linux,code = <KEY_DOWN>;
54 gpio-key,wakeup;
55 autorepeat;
56 };
57 };
58
59 leds {
60 compatible = "gpio-leds";
61 heartbeat_led {
62 label = "heartbeat";
63 gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
64 linux,default-trigger = "heartbeat";
65 };
66 };
Michal Simek2ec41ef2019-08-26 09:46:36 +0200[diff] [blame^]67
68 ina226-u76 {
69 compatible = "iio-hwmon";
70 io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>;
71 };
72 ina226-u77 {
73 compatible = "iio-hwmon";
74 io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;
75 };
76 ina226-u78 {
77 compatible = "iio-hwmon";
78 io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>;
79 };
80 ina226-u87 {
81 compatible = "iio-hwmon";
82 io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>;
83 };
84 ina226-u85 {
85 compatible = "iio-hwmon";
86 io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>;
87 };
88 ina226-u86 {
89 compatible = "iio-hwmon";
90 io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>;
91 };
92 ina226-u93 {
93 compatible = "iio-hwmon";
94 io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>;
95 };
96 ina226-u88 {
97 compatible = "iio-hwmon";
98 io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>;
99 };
100 ina226-u15 {
101 compatible = "iio-hwmon";
102 io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>;
103 };
104 ina226-u92 {
105 compatible = "iio-hwmon";
106 io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>;
107 };
108 ina226-u79 {
109 compatible = "iio-hwmon";
110 io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;
111 };
112 ina226-u81 {
113 compatible = "iio-hwmon";
114 io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>;
115 };
116 ina226-u80 {
117 compatible = "iio-hwmon";
118 io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>;
119 };
120 ina226-u84 {
121 compatible = "iio-hwmon";
122 io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>;
123 };
124 ina226-u16 {
125 compatible = "iio-hwmon";
126 io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>;
127 };
128 ina226-u65 {
129 compatible = "iio-hwmon";
130 io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;
131 };
132 ina226-u74 {
133 compatible = "iio-hwmon";
134 io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>;
135 };
136 ina226-u75 {
137 compatible = "iio-hwmon";
138 io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;
139 };
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]140};
141
142&can1 {
143 status = "okay";
144};
145
146&dcc {
147 status = "okay";
148};
149
150&fpd_dma_chan1 {
151 status = "okay";
152};
153
154&fpd_dma_chan2 {
155 status = "okay";
156};
157
158&fpd_dma_chan3 {
159 status = "okay";
160};
161
162&fpd_dma_chan4 {
163 status = "okay";
164};
165
166&fpd_dma_chan5 {
167 status = "okay";
168};
169
170&fpd_dma_chan6 {
171 status = "okay";
172};
173
174&fpd_dma_chan7 {
175 status = "okay";
176};
177
178&fpd_dma_chan8 {
179 status = "okay";
180};
181
182&gem3 {
183 status = "okay";
184 phy-handle = <&phy0>;
185 phy-mode = "rgmii-id";
Michal Simek393decf2019-08-08 12:44:22 +0200[diff] [blame]186 phy0: ethernet-phy@c {
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]187 reg = <0xc>;
188 ti,rx-internal-delay = <0x8>;
189 ti,tx-internal-delay = <0xa>;
190 ti,fifo-depth = <0x1>;
191 };
192};
193
194&gpio {
195 status = "okay";
196};
197
198&gpu {
199 status = "okay";
200};
201
202&i2c0 {
203 status = "okay";
204 clock-frequency = <400000>;
205
206 tca6416_u97: gpio@20 {
207 compatible = "ti,tca6416";
208 reg = <0x20>;
209 gpio-controller; /* interrupt not connected */
210 #gpio-cells = <2>;
211 /*
212 * IRQ not connected
213 * Lines:
214 * 0 - SFP_SI5328_INT_ALM
215 * 1 - HDMI_SI5328_INT_ALM
216 * 5 - IIC_MUX_RESET_B
217 * 6 - GEM3_EXP_RESET_B
218 * 10 - FMC_HPC0_PRSNT_M2C_B
219 * 11 - FMC_HPC1_PRSNT_M2C_B
220 * 2-4, 7, 12-17 - not connected
221 */
222 };
223
224 tca6416_u61: gpio@21 {
225 compatible = "ti,tca6416";
226 reg = <0x21>;
227 gpio-controller;
228 #gpio-cells = <2>;
229 /*
230 * IRQ not connected
231 * Lines:
232 * 0 - VCCPSPLL_EN
233 * 1 - MGTRAVCC_EN
234 * 2 - MGTRAVTT_EN
235 * 3 - VCCPSDDRPLL_EN
236 * 4 - MIO26_PMU_INPUT_LS
237 * 5 - PL_PMBUS_ALERT
238 * 6 - PS_PMBUS_ALERT
239 * 7 - MAXIM_PMBUS_ALERT
240 * 10 - PL_DDR4_VTERM_EN
241 * 11 - PL_DDR4_VPP_2V5_EN
242 * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON
243 * 13 - PS_DIMM_SUSPEND_EN
244 * 14 - PS_DDR4_VTERM_EN
245 * 15 - PS_DDR4_VPP_2V5_EN
246 * 16 - 17 - not connected
247 */
248 };
249
250 i2c-mux@75 { /* u60 */
251 compatible = "nxp,pca9544";
252 #address-cells = <1>;
253 #size-cells = <0>;
254 reg = <0x75>;
255 i2c@0 {
256 #address-cells = <1>;
257 #size-cells = <0>;
258 reg = <0>;
259 /* PS_PMBUS */
Michal Simek2ec41ef2019-08-26 09:46:36 +0200[diff] [blame^]260 u76: ina226@40 { /* u76 */
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]261 compatible = "ti,ina226";
Michal Simek2ec41ef2019-08-26 09:46:36 +0200[diff] [blame^]262 #io-channel-cells = <1>;
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]263 reg = <0x40>;
264 shunt-resistor = <5000>;
265 };
Michal Simek2ec41ef2019-08-26 09:46:36 +0200[diff] [blame^]266 u77: ina226@41 { /* u77 */
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]267 compatible = "ti,ina226";
Michal Simek2ec41ef2019-08-26 09:46:36 +0200[diff] [blame^]268 #io-channel-cells = <1>;
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]269 reg = <0x41>;
270 shunt-resistor = <5000>;
271 };
Michal Simek2ec41ef2019-08-26 09:46:36 +0200[diff] [blame^]272 u78: ina226@42 { /* u78 */
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]273 compatible = "ti,ina226";
Michal Simek2ec41ef2019-08-26 09:46:36 +0200[diff] [blame^]274 #io-channel-cells = <1>;
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]275 reg = <0x42>;
276 shunt-resistor = <5000>;
277 };
Michal Simek2ec41ef2019-08-26 09:46:36 +0200[diff] [blame^]278 u87: ina226@43 { /* u87 */
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]279 compatible = "ti,ina226";
Michal Simek2ec41ef2019-08-26 09:46:36 +0200[diff] [blame^]280 #io-channel-cells = <1>;
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]281 reg = <0x43>;
282 shunt-resistor = <5000>;
283 };
Michal Simek2ec41ef2019-08-26 09:46:36 +0200[diff] [blame^]284 u85: ina226@44 { /* u85 */
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]285 compatible = "ti,ina226";
Michal Simek2ec41ef2019-08-26 09:46:36 +0200[diff] [blame^]286 #io-channel-cells = <1>;
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]287 reg = <0x44>;
288 shunt-resistor = <5000>;
289 };
Michal Simek2ec41ef2019-08-26 09:46:36 +0200[diff] [blame^]290 u86: ina226@45 { /* u86 */
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]291 compatible = "ti,ina226";
Michal Simek2ec41ef2019-08-26 09:46:36 +0200[diff] [blame^]292 #io-channel-cells = <1>;
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]293 reg = <0x45>;
294 shunt-resistor = <5000>;
295 };
Michal Simek2ec41ef2019-08-26 09:46:36 +0200[diff] [blame^]296 u93: ina226@46 { /* u93 */
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]297 compatible = "ti,ina226";
Michal Simek2ec41ef2019-08-26 09:46:36 +0200[diff] [blame^]298 #io-channel-cells = <1>;
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]299 reg = <0x46>;
300 shunt-resistor = <5000>;
301 };
Michal Simek2ec41ef2019-08-26 09:46:36 +0200[diff] [blame^]302 u88: ina226@47 { /* u88 */
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]303 compatible = "ti,ina226";
Michal Simek2ec41ef2019-08-26 09:46:36 +0200[diff] [blame^]304 #io-channel-cells = <1>;
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]305 reg = <0x47>;
306 shunt-resistor = <5000>;
307 };
Michal Simek2ec41ef2019-08-26 09:46:36 +0200[diff] [blame^]308 u15: ina226@4a { /* u15 */
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]309 compatible = "ti,ina226";
Michal Simek2ec41ef2019-08-26 09:46:36 +0200[diff] [blame^]310 #io-channel-cells = <1>;
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]311 reg = <0x4a>;
312 shunt-resistor = <5000>;
313 };
Michal Simek2ec41ef2019-08-26 09:46:36 +0200[diff] [blame^]314 u92: ina226@4b { /* u92 */
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]315 compatible = "ti,ina226";
Michal Simek2ec41ef2019-08-26 09:46:36 +0200[diff] [blame^]316 #io-channel-cells = <1>;
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]317 reg = <0x4b>;
318 shunt-resistor = <5000>;
319 };
320 };
321 i2c@1 {
322 #address-cells = <1>;
323 #size-cells = <0>;
324 reg = <1>;
325 /* PL_PMBUS */
Michal Simek2ec41ef2019-08-26 09:46:36 +0200[diff] [blame^]326 u79: ina226@40 { /* u79 */
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]327 compatible = "ti,ina226";
Michal Simek2ec41ef2019-08-26 09:46:36 +0200[diff] [blame^]328 #io-channel-cells = <1>;
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]329 reg = <0x40>;
330 shunt-resistor = <2000>;
331 };
Michal Simek2ec41ef2019-08-26 09:46:36 +0200[diff] [blame^]332 u81: ina226@41 { /* u81 */
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]333 compatible = "ti,ina226";
Michal Simek2ec41ef2019-08-26 09:46:36 +0200[diff] [blame^]334 #io-channel-cells = <1>;
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]335 reg = <0x41>;
336 shunt-resistor = <5000>;
337 };
Michal Simek2ec41ef2019-08-26 09:46:36 +0200[diff] [blame^]338 u80: ina226@42 { /* u80 */
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]339 compatible = "ti,ina226";
Michal Simek2ec41ef2019-08-26 09:46:36 +0200[diff] [blame^]340 #io-channel-cells = <1>;
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]341 reg = <0x42>;
342 shunt-resistor = <5000>;
343 };
Michal Simek2ec41ef2019-08-26 09:46:36 +0200[diff] [blame^]344 u84: ina226@43 { /* u84 */
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]345 compatible = "ti,ina226";
Michal Simek2ec41ef2019-08-26 09:46:36 +0200[diff] [blame^]346 #io-channel-cells = <1>;
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]347 reg = <0x43>;
348 shunt-resistor = <5000>;
349 };
Michal Simek2ec41ef2019-08-26 09:46:36 +0200[diff] [blame^]350 u16: ina226@44 { /* u16 */
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]351 compatible = "ti,ina226";
Michal Simek2ec41ef2019-08-26 09:46:36 +0200[diff] [blame^]352 #io-channel-cells = <1>;
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]353 reg = <0x44>;
354 shunt-resistor = <5000>;
355 };
Michal Simek2ec41ef2019-08-26 09:46:36 +0200[diff] [blame^]356 u65: ina226@45 { /* u65 */
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]357 compatible = "ti,ina226";
Michal Simek2ec41ef2019-08-26 09:46:36 +0200[diff] [blame^]358 #io-channel-cells = <1>;
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]359 reg = <0x45>;
360 shunt-resistor = <5000>;
361 };
Michal Simek2ec41ef2019-08-26 09:46:36 +0200[diff] [blame^]362 u74: ina226@46 { /* u74 */
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]363 compatible = "ti,ina226";
Michal Simek2ec41ef2019-08-26 09:46:36 +0200[diff] [blame^]364 #io-channel-cells = <1>;
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]365 reg = <0x46>;
366 shunt-resistor = <5000>;
367 };
Michal Simek2ec41ef2019-08-26 09:46:36 +0200[diff] [blame^]368 u75: ina226@47 { /* u75 */
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]369 compatible = "ti,ina226";
Michal Simek2ec41ef2019-08-26 09:46:36 +0200[diff] [blame^]370 #io-channel-cells = <1>;
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]371 reg = <0x47>;
372 shunt-resistor = <5000>;
373 };
374 };
375 i2c@2 {
376 #address-cells = <1>;
377 #size-cells = <0>;
378 reg = <2>;
379 /* MAXIM_PMBUS - 00 */
380 max15301@a { /* u46 */
381 compatible = "maxim,max15301";
382 reg = <0xa>;
383 };
384 max15303@b { /* u4 */
385 compatible = "maxim,max15303";
386 reg = <0xb>;
387 };
388 max15303@10 { /* u13 */
389 compatible = "maxim,max15303";
390 reg = <0x10>;
391 };
392 max15301@13 { /* u47 */
393 compatible = "maxim,max15301";
394 reg = <0x13>;
395 };
396 max15303@14 { /* u7 */
397 compatible = "maxim,max15303";
398 reg = <0x14>;
399 };
400 max15303@15 { /* u6 */
401 compatible = "maxim,max15303";
402 reg = <0x15>;
403 };
404 max15303@16 { /* u10 */
405 compatible = "maxim,max15303";
406 reg = <0x16>;
407 };
408 max15303@17 { /* u9 */
409 compatible = "maxim,max15303";
410 reg = <0x17>;
411 };
412 max15301@18 { /* u63 */
413 compatible = "maxim,max15301";
414 reg = <0x18>;
415 };
416 max15303@1a { /* u49 */
417 compatible = "maxim,max15303";
418 reg = <0x1a>;
419 };
420 max15303@1b { /* u8 */
421 compatible = "maxim,max15303";
422 reg = <0x1b>;
423 };
424 max15303@1d { /* u18 */
425 compatible = "maxim,max15303";
426 reg = <0x1d>;
427 };
428
429 max20751@72 { /* u95 */
430 compatible = "maxim,max20751";
431 reg = <0x72>;
432 };
433 max20751@73 { /* u96 */
434 compatible = "maxim,max20751";
435 reg = <0x73>;
436 };
437 };
438 /* Bus 3 is not connected */
439 };
440};
441
442&i2c1 {
443 status = "okay";
444 clock-frequency = <400000>;
445
446 /* PL i2c via PCA9306 - u45 */
447 i2c-mux@74 { /* u34 */
448 compatible = "nxp,pca9548";
449 #address-cells = <1>;
450 #size-cells = <0>;
451 reg = <0x74>;
452 i2c@0 {
453 #address-cells = <1>;
454 #size-cells = <0>;
455 reg = <0>;
456 /*
457 * IIC_EEPROM 1kB memory which uses 256B blocks
458 * where every block has different address.
459 * 0 - 256B address 0x54
460 * 256B - 512B address 0x55
461 * 512B - 768B address 0x56
462 * 768B - 1024B address 0x57
463 */
464 eeprom: eeprom@54 { /* u23 */
465 compatible = "atmel,24c08";
466 reg = <0x54>;
467 };
468 };
469 i2c@1 {
470 #address-cells = <1>;
471 #size-cells = <0>;
472 reg = <1>;
473 si5341: clock-generator@36 { /* SI5341 - u69 */
474 compatible = "si5341";
475 reg = <0x36>;
476 };
477
478 };
479 i2c@2 {
480 #address-cells = <1>;
481 #size-cells = <0>;
482 reg = <2>;
483 si570_1: clock-generator@5d { /* USER SI570 - u42 */
484 #clock-cells = <0>;
485 compatible = "silabs,si570";
486 reg = <0x5d>;
487 temperature-stability = <50>;
488 factory-fout = <300000000>;
489 clock-frequency = <300000000>;
Michal Simek3cf07bf2018-07-18 12:10:02 +0200[diff] [blame]490 clock-output-names = "si570_user";
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]491 };
492 };
493 i2c@3 {
494 #address-cells = <1>;
495 #size-cells = <0>;
496 reg = <3>;
497 si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */
498 #clock-cells = <0>;
499 compatible = "silabs,si570";
500 reg = <0x5d>;
501 temperature-stability = <50>; /* copy from zc702 */
502 factory-fout = <156250000>;
503 clock-frequency = <148500000>;
Michal Simek3cf07bf2018-07-18 12:10:02 +0200[diff] [blame]504 clock-output-names = "si570_mgt";
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]505 };
506 };
507 i2c@4 {
508 #address-cells = <1>;
509 #size-cells = <0>;
510 reg = <4>;
511 si5328: clock-generator@69 {/* SI5328 - u20 */
512 compatible = "silabs,si5328";
513 reg = <0x69>;
514 };
515 };
516 i2c@5 {
517 #address-cells = <1>;
518 #size-cells = <0>;
519 reg = <5>; /* FAN controller */
520 temp@4c {/* lm96163 - u128 */
521 compatible = "national,lm96163";
522 reg = <0x4c>;
523 };
524 };
525 /* 6 - 7 unconnected */
526 };
527
528 i2c-mux@75 {
529 compatible = "nxp,pca9548"; /* u135 */
530 #address-cells = <1>;
531 #size-cells = <0>;
532 reg = <0x75>;
533
534 i2c@0 {
535 #address-cells = <1>;
536 #size-cells = <0>;
537 reg = <0>;
538 /* HPC0_IIC */
539 };
540 i2c@1 {
541 #address-cells = <1>;
542 #size-cells = <0>;
543 reg = <1>;
544 /* HPC1_IIC */
545 };
546 i2c@2 {
547 #address-cells = <1>;
548 #size-cells = <0>;
549 reg = <2>;
550 /* SYSMON */
551 };
552 i2c@3 {
553 #address-cells = <1>;
554 #size-cells = <0>;
555 reg = <3>;
556 /* DDR4 SODIMM */
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]557 };
558 i2c@4 {
559 #address-cells = <1>;
560 #size-cells = <0>;
561 reg = <4>;
562 /* SEP 3 */
563 };
564 i2c@5 {
565 #address-cells = <1>;
566 #size-cells = <0>;
567 reg = <5>;
568 /* SEP 2 */
569 };
570 i2c@6 {
571 #address-cells = <1>;
572 #size-cells = <0>;
573 reg = <6>;
574 /* SEP 1 */
575 };
576 i2c@7 {
577 #address-cells = <1>;
578 #size-cells = <0>;
579 reg = <7>;
580 /* SEP 0 */
581 };
582 };
583};
584
585&qspi {
586 status = "okay";
587 is-dual = <1>;
588 flash@0 {
Neil Armstronga009fa72019-02-10 10:16:20 +0000[diff] [blame]589 compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]590 #address-cells = <1>;
591 #size-cells = <1>;
592 reg = <0x0>;
593 spi-tx-bus-width = <1>;
594 spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
595 spi-max-frequency = <108000000>; /* Based on DC1 spec */
596 partition@qspi-fsbl-uboot { /* for testing purpose */
597 label = "qspi-fsbl-uboot";
598 reg = <0x0 0x100000>;
599 };
600 partition@qspi-linux { /* for testing purpose */
601 label = "qspi-linux";
602 reg = <0x100000 0x500000>;
603 };
604 partition@qspi-device-tree { /* for testing purpose */
605 label = "qspi-device-tree";
606 reg = <0x600000 0x20000>;
607 };
608 partition@qspi-rootfs { /* for testing purpose */
609 label = "qspi-rootfs";
610 reg = <0x620000 0x5E0000>;
611 };
612 };
613};
614
615&rtc {
616 status = "okay";
617};
618
619&sata {
620 status = "okay";
621 /* SATA OOB timing settings */
622 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
623 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
624 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
625 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
626 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
627 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
628 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
629 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
630 phy-names = "sata-phy";
631 phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>;
632};
633
634/* SD1 with level shifter */
635&sdhci1 {
636 status = "okay";
637 no-1-8-v;
638 xlnx,mio_bank = <1>;
639};
640
641&serdes {
642 status = "okay";
643};
644
645&uart0 {
646 status = "okay";
647};
648
649&uart1 {
650 status = "okay";
651};
652
653/* ULPI SMSC USB3320 */
654&usb0 {
655 status = "okay";
656};
657
658&dwc3_0 {
659 status = "okay";
660 dr_mode = "host";
661 snps,usb3_lpm_capable;
662 phy-names = "usb3-phy";
663 phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;
664};
665
666&watchdog0 {
667 status = "okay";
668};