Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Marek Vasut | 3ef6d08 | 2017-10-08 20:41:18 +0200 | [diff] [blame] | 2 | /* |
| 3 | * board/renesas/draak/draak.c |
| 4 | * This file is Draak board support. |
| 5 | * |
| 6 | * Copyright (C) 2017 Marek Vasut <marek.vasut+renesas@gmail.com> |
Marek Vasut | 3ef6d08 | 2017-10-08 20:41:18 +0200 | [diff] [blame] | 7 | */ |
| 8 | |
| 9 | #include <common.h> |
Simon Glass | afb0215 | 2019-12-28 10:45:01 -0700 | [diff] [blame] | 10 | #include <cpu_func.h> |
Simon Glass | f11478f | 2019-12-28 10:45:07 -0700 | [diff] [blame] | 11 | #include <hang.h> |
Simon Glass | 9758973 | 2020-05-10 11:40:02 -0600 | [diff] [blame^] | 12 | #include <init.h> |
Marek Vasut | 3ef6d08 | 2017-10-08 20:41:18 +0200 | [diff] [blame] | 13 | #include <malloc.h> |
| 14 | #include <netdev.h> |
| 15 | #include <dm.h> |
| 16 | #include <dm/platform_data/serial_sh.h> |
| 17 | #include <asm/processor.h> |
| 18 | #include <asm/mach-types.h> |
| 19 | #include <asm/io.h> |
| 20 | #include <linux/errno.h> |
| 21 | #include <asm/arch/sys_proto.h> |
| 22 | #include <asm/gpio.h> |
| 23 | #include <asm/arch/gpio.h> |
| 24 | #include <asm/arch/rmobile.h> |
| 25 | #include <asm/arch/rcar-mstp.h> |
| 26 | #include <asm/arch/sh_sdhi.h> |
| 27 | #include <i2c.h> |
| 28 | #include <mmc.h> |
| 29 | |
| 30 | DECLARE_GLOBAL_DATA_PTR; |
| 31 | |
Marek Vasut | 3ef6d08 | 2017-10-08 20:41:18 +0200 | [diff] [blame] | 32 | void s_init(void) |
| 33 | { |
Marek Vasut | 3ef6d08 | 2017-10-08 20:41:18 +0200 | [diff] [blame] | 34 | } |
| 35 | |
| 36 | #define GSX_MSTP112 BIT(12) /* 3DG */ |
Marek Vasut | 3ef6d08 | 2017-10-08 20:41:18 +0200 | [diff] [blame] | 37 | #define SCIF2_MSTP310 BIT(10) /* SCIF2 */ |
| 38 | #define DVFS_MSTP926 BIT(26) |
| 39 | #define HSUSB_MSTP704 BIT(4) /* HSUSB */ |
| 40 | |
| 41 | int board_early_init_f(void) |
| 42 | { |
Marek Vasut | 3ef6d08 | 2017-10-08 20:41:18 +0200 | [diff] [blame] | 43 | #if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH) |
| 44 | /* DVFS for reset */ |
Hiroyuki Yokoyama | 7e17291 | 2018-09-26 16:00:09 +0900 | [diff] [blame] | 45 | mstp_clrbits_le32(SMSTPCR9, SMSTPCR9, DVFS_MSTP926); |
Marek Vasut | 3ef6d08 | 2017-10-08 20:41:18 +0200 | [diff] [blame] | 46 | #endif |
| 47 | return 0; |
| 48 | } |
| 49 | |
Marek Vasut | 3ef6d08 | 2017-10-08 20:41:18 +0200 | [diff] [blame] | 50 | /* HSUSB block registers */ |
| 51 | #define HSUSB_REG_LPSTS 0xE6590102 |
| 52 | #define HSUSB_REG_LPSTS_SUSPM_NORMAL BIT(14) |
| 53 | #define HSUSB_REG_UGCTRL2 0xE6590184 |
| 54 | #define HSUSB_REG_UGCTRL2_USB0SEL 0x30 |
| 55 | #define HSUSB_REG_UGCTRL2_USB0SEL_EHCI 0x10 |
| 56 | |
| 57 | int board_init(void) |
| 58 | { |
| 59 | /* adress of boot parameters */ |
| 60 | gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000; |
| 61 | |
| 62 | /* USB1 pull-up */ |
| 63 | setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN); |
| 64 | |
| 65 | /* Configure the HSUSB block */ |
Hiroyuki Yokoyama | 7e17291 | 2018-09-26 16:00:09 +0900 | [diff] [blame] | 66 | mstp_clrbits_le32(SMSTPCR7, SMSTPCR7, HSUSB_MSTP704); |
Marek Vasut | 3ef6d08 | 2017-10-08 20:41:18 +0200 | [diff] [blame] | 67 | /* Choice USB0SEL */ |
| 68 | clrsetbits_le32(HSUSB_REG_UGCTRL2, HSUSB_REG_UGCTRL2_USB0SEL, |
| 69 | HSUSB_REG_UGCTRL2_USB0SEL_EHCI); |
| 70 | /* low power status */ |
| 71 | setbits_le16(HSUSB_REG_LPSTS, HSUSB_REG_LPSTS_SUSPM_NORMAL); |
| 72 | |
| 73 | return 0; |
| 74 | } |
| 75 | |
Marek Vasut | 3ef6d08 | 2017-10-08 20:41:18 +0200 | [diff] [blame] | 76 | #define RST_BASE 0xE6160000 |
| 77 | #define RST_CA57RESCNT (RST_BASE + 0x40) |
| 78 | #define RST_CA53RESCNT (RST_BASE + 0x44) |
| 79 | #define RST_RSTOUTCR (RST_BASE + 0x58) |
| 80 | #define RST_CA57_CODE 0xA5A5000F |
| 81 | #define RST_CA53_CODE 0x5A5A000F |
| 82 | |
| 83 | void reset_cpu(ulong addr) |
| 84 | { |
| 85 | unsigned long midr, cputype; |
| 86 | |
| 87 | asm volatile("mrs %0, midr_el1" : "=r" (midr)); |
| 88 | cputype = (midr >> 4) & 0xfff; |
| 89 | |
| 90 | if (cputype == 0xd03) |
| 91 | writel(RST_CA53_CODE, RST_CA53RESCNT); |
| 92 | else if (cputype == 0xd07) |
| 93 | writel(RST_CA57_CODE, RST_CA57RESCNT); |
| 94 | else |
| 95 | hang(); |
| 96 | } |