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git01.mediatek.com / filogic / uboot / 9737944f37c5180add3fd71c11bdc7bff6f5dc5f / . / configs / socfpga_sr1500_defconfig
blob: b07e0a3355ae123c61067f64b7ee23a5ebebc8d1 [file] [log] [blame]
Stefan Roesebf5ed2e2015-11-18 11:06:09 +0100[diff] [blame]1CONFIG_ARM=y
Philip Oberfichtner5833e1b2022-08-17 15:07:12 +0200[diff] [blame]2CONFIG_SYS_L2_PL310=y
Stefan Roesebf5ed2e2015-11-18 11:06:09 +0100[diff] [blame]3CONFIG_ARCH_SOCFPGA=y
Tom Rinie25a03a2021-11-01 12:19:22 +0000[diff] [blame]4CONFIG_SYS_MALLOC_LEN=0x4000000
Tom Rini9924ca12023-02-17 09:58:06 -0500[diff] [blame]5CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
6CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x800000
Tom Rinia77d6f82023-05-01 11:50:26 -0400[diff] [blame]7CONFIG_SF_DEFAULT_SPEED=100000000
Tom Rini5cd7ece2019-11-18 20:02:10 -0500[diff] [blame]8CONFIG_ENV_SIZE=0x4000
9CONFIG_ENV_OFFSET=0xE0000
Tom Rini47dece32020-04-28 16:15:47 -0400[diff] [blame]10CONFIG_ENV_SECT_SIZE=0x10000
Tom Rinif6e6e1a2020-01-22 13:38:00 -0500[diff] [blame]11CONFIG_DM_GPIO=y
Tom Rinia20e51f2021-06-28 10:17:29 -0400[diff] [blame]12CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sr1500"
Tom Rini0332a1a2020-07-06 13:54:25 -0400[diff] [blame]13CONFIG_SPL_TEXT_BASE=0xFFFF0000
Tom Rini9924ca12023-02-17 09:58:06 -0500[diff] [blame]14CONFIG_DM_RESET=y
Tom Rini66ea5c72019-05-26 14:45:25 -0400[diff] [blame]15CONFIG_SYS_BOOTCOUNT_ADDR=0xfffffff8
Tom Rini9924ca12023-02-17 09:58:06 -0500[diff] [blame]16CONFIG_SPL_STACK=0xfffffff8
Tom Rini6bd3b142020-02-06 13:42:52 -0500[diff] [blame]17CONFIG_TARGET_SOCFPGA_SR1500=y
Tom Rinid49f5822020-02-28 13:28:38 -0500[diff] [blame]18CONFIG_ENV_OFFSET_REDUND=0xF0000
Tom Rini76fbc6f2022-04-01 10:33:18 -0400[diff] [blame]19CONFIG_SYS_MEMTEST_START=0x00000000
20CONFIG_SYS_MEMTEST_END=0x40000000
Simon Glassffe19762016-09-12 23:18:22 -0600[diff] [blame]21CONFIG_FIT=y
Simon Glass65831d92021-12-18 11:27:50 -0700[diff] [blame]22CONFIG_TIMESTAMP=y
Tom Riniadb7a192023-03-27 13:39:17 -0400[diff] [blame]23CONFIG_DISTRO_DEFAULTS=y
Tom Rini732aa4a2018-02-10 16:54:38 -0500[diff] [blame]24# CONFIG_USE_BOOTCOMMAND is not set
Tom Rinif92b6fa2020-10-09 12:22:06 -0400[diff] [blame]25CONFIG_DEFAULT_FDT_FILE="socfpga_cyclone5_sr1500.dtb"
Simon Glass9fd2a022016-10-17 20:12:37 -0600[diff] [blame]26CONFIG_SYS_CONSOLE_IS_IN_ENV=y
Simon Glassac3ee422016-10-17 20:12:59 -0600[diff] [blame]27CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
Simon Glass217652f2016-10-17 20:12:58 -0600[diff] [blame]28CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
Simon Glassbd5618d2016-10-17 20:13:00 -0600[diff] [blame]29CONFIG_SYS_CONSOLE_INFO_QUIET=y
Lokesh Vutla94d95e42016-10-11 21:33:46 -0400[diff] [blame]30# CONFIG_DISPLAY_BOARDINFO is not set
Mario Sixf7055442018-03-28 14:38:17 +0200[diff] [blame]31CONFIG_DISPLAY_BOARDINFO_LATE=y
Simon Glass7a99a872017-01-23 13:31:20 -0700[diff] [blame]32CONFIG_BOARD_EARLY_INIT_F=y
Tom Rini2bfc77a2022-03-23 17:20:08 -0400[diff] [blame]33CONFIG_CLOCKS=y
Tom Riniabb0f522022-05-16 17:20:26 -0400[diff] [blame]34CONFIG_SPL_PAD_TO=0x10000
Tom Rini0cb89e72022-05-19 15:09:22 -0400[diff] [blame]35CONFIG_SPL_NO_BSS_LIMIT=y
Tom Rini8a14ac42022-05-26 13:13:21 -0400[diff] [blame]36# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
Marek Vasute2542252018-04-07 16:05:27 +0200[diff] [blame]37CONFIG_SPL_SPI_LOAD=y
Tom Rinie22fa4f2021-08-10 15:08:46 -0400[diff] [blame]38CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
Tom Riniba5c2b02022-05-11 16:21:06 -0400[diff] [blame]39CONFIG_SYS_MAXARGS=32
Tom Rini1d9ac832016-04-24 17:29:26 -0400[diff] [blame]40CONFIG_CMD_ASKENV=y
41CONFIG_CMD_GREPENV=y
Tom Rini0f2dcb92016-04-22 16:41:25 -0400[diff] [blame]42CONFIG_CMD_MEMTEST=y
Stefan Roesebf5ed2e2015-11-18 11:06:09 +0100[diff] [blame]43# CONFIG_CMD_FLASH is not set
Tom Rini78873cd2017-08-14 19:58:53 -0400[diff] [blame]44CONFIG_CMD_GPIO=y
45CONFIG_CMD_I2C=y
Tom Rini1d9ac832016-04-24 17:29:26 -0400[diff] [blame]46CONFIG_CMD_MMC=y
Tom Rini0f2dcb92016-04-22 16:41:25 -0400[diff] [blame]47CONFIG_CMD_SPI=y
Tom Rini1d9ac832016-04-24 17:29:26 -0400[diff] [blame]48CONFIG_CMD_CACHE=y
Tom Rini0f2dcb92016-04-22 16:41:25 -0400[diff] [blame]49CONFIG_CMD_TIME=y
Tom Rini1d9ac832016-04-24 17:29:26 -0400[diff] [blame]50CONFIG_CMD_EXT4_WRITE=y
Tom Rini5ad8e112017-10-22 17:55:07 -0400[diff] [blame]51CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
Marek Vasutc0169f32019-10-02 18:54:45 +0200[diff] [blame]52CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)"
Heiko Schocher09dbb852016-09-21 07:58:19 +0200[diff] [blame]53CONFIG_CMD_UBI=y
Tom Rini2cbc1202018-04-28 10:45:55 -0400[diff] [blame]54# CONFIG_ISO_PARTITION is not set
55# CONFIG_EFI_PARTITION is not set
Tom Rini5b0b0402017-08-28 07:16:32 -0400[diff] [blame]56CONFIG_ENV_IS_IN_SPI_FLASH=y
Tom Rini4bb26a42019-11-10 11:28:03 -0500[diff] [blame]57CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
Tom Rinica63e712019-11-12 22:46:36 -0500[diff] [blame]58CONFIG_SYS_RELOC_GD_ENV_ADDR=y
Tom Rinif92b6fa2020-10-09 12:22:06 -0400[diff] [blame]59CONFIG_VERSION_VARIABLE=y
Simon Glassc08ebf62016-02-22 22:55:40 -0700[diff] [blame]60CONFIG_SPL_DM_SEQ_ALIAS=y
Lukasz Majewski6dd8c902018-02-09 23:50:57 +0100[diff] [blame]61CONFIG_BOOTCOUNT_LIMIT=y
Tom Rini5f4f84e2022-06-25 11:02:49 -0400[diff] [blame]62CONFIG_SYS_BOOTCOUNT_BE=y
Stefan Roesebf5ed2e2015-11-18 11:06:09 +0100[diff] [blame]63CONFIG_DWAPB_GPIO=y
Dinh Nguyena75fcc12018-04-04 17:18:21 -0500[diff] [blame]64CONFIG_DM_I2C=y
Stefan Roese78077b62016-04-28 09:47:18 +0200[diff] [blame]65CONFIG_SYS_I2C_DW=y
Tom Rini91735482022-10-28 20:27:05 -0400[diff] [blame]66CONFIG_SYS_MMC_MAX_BLK_COUNT=256
Masahiro Yamada7942e912017-01-10 13:32:04 +0900[diff] [blame]67CONFIG_MMC_DW=y
Miquel Raynal2e35dbb2019-10-03 19:50:05 +0200[diff] [blame]68CONFIG_MTD=y
Stefan Roese85e84392016-03-03 16:57:39 +0100[diff] [blame]69CONFIG_SPI_FLASH_STMICRO=y
Simon Glassc08ebf62016-02-22 22:55:40 -0700[diff] [blame]70# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
Frieder Schrempfd7be62c2019-10-23 07:41:20 +0000[diff] [blame]71CONFIG_SPI_FLASH_MTD=y
Mario Sixf504d1a2018-04-27 14:52:21 +0200[diff] [blame]72CONFIG_PHY_MARVELL=y
Tom Rinica22e962017-08-07 22:00:34 -0400[diff] [blame]73CONFIG_PHY_GIGE=y
Stefan Roesebf5ed2e2015-11-18 11:06:09 +0100[diff] [blame]74CONFIG_ETH_DESIGNWARE=y
Adam Ford53705472018-07-20 23:03:57 -0500[diff] [blame]75CONFIG_MII=y
Adam Ford4e96ff82018-04-15 13:51:26 -0400[diff] [blame]76CONFIG_SPI=y
Stefan Roese85e84392016-03-03 16:57:39 +0100[diff] [blame]77CONFIG_CADENCE_QSPI=y
Simon Goldschmidtfe6275f2019-10-05 22:10:11 +0200[diff] [blame]78# CONFIG_SPL_WDT is not set
Tom Rini1f173632022-11-16 13:10:38 -0500[diff] [blame]79CONFIG_SYS_TIMER_COUNTS_DOWN=y