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Svyatoslav Ryhel4c5fe372023-06-30 10:29:06 +03001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * T30 HTC Endeavoru SPL stage configuration
4 *
5 * (C) Copyright 2010-2013
6 * NVIDIA Corporation <www.nvidia.com>
7 *
8 * (C) Copyright 2022
9 * Svyatoslav Ryhel <clamor95@gmail.com>
10 */
11
Svyatoslav Ryhel7be80312024-01-05 17:35:26 +020012#include <asm/gpio.h>
13#include <asm/arch/pinmux.h>
Svyatoslav Ryhel8c8fb852023-08-26 18:35:35 +030014#include <asm/arch/tegra.h>
Svyatoslav Ryhel7be80312024-01-05 17:35:26 +020015#include <asm/arch-tegra/pmc.h>
Svyatoslav Ryhel4c5fe372023-06-30 10:29:06 +030016#include <asm/arch-tegra/tegra_i2c.h>
Svyatoslav Ryhele1bc2ff2024-08-09 21:27:58 +030017#include <spl_gpio.h>
Svyatoslav Ryhel4c5fe372023-06-30 10:29:06 +030018#include <linux/delay.h>
19
20/*
21 * Endeavoru uses TPS80032 PMIC with SMPS1 and SMPS2 in strandard
22 * mode with zero offset.
23 */
24
25#define TPS80032_DVS_I2C_ADDR (0x12 << 1)
26#define TPS80032_SMPS1_CFG_VOLTAGE_REG 0x56
27#define TPS80032_SMPS2_CFG_VOLTAGE_REG 0x5C
28#define TPS80032_SMPS1_CFG_VOLTAGE_DATA (0x2100 | TPS80032_SMPS1_CFG_VOLTAGE_REG)
29#define TPS80032_SMPS2_CFG_VOLTAGE_DATA (0x3000 | TPS80032_SMPS2_CFG_VOLTAGE_REG)
30
31#define TPS80032_CTL1_I2C_ADDR (0x48 << 1)
32#define TPS80032_SMPS1_CFG_STATE_REG 0x54
33#define TPS80032_SMPS2_CFG_STATE_REG 0x5A
34#define TPS80032_SMPS1_CFG_STATE_DATA (0x0100 | TPS80032_SMPS1_CFG_STATE_REG)
35#define TPS80032_SMPS2_CFG_STATE_DATA (0x0100 | TPS80032_SMPS2_CFG_STATE_REG)
36
Svyatoslav Ryhel7be80312024-01-05 17:35:26 +020037/*
38 * Unlike all other supported Tegra devices and most known Tegra devices, the
39 * HTC One X has no hardware way to enter APX/RCM mode, which may lead to a
40 * dangerous situation when, if BCT is set correctly and the bootloader is
41 * faulty, the device will hang in a permanent brick state. Exiting from this
42 * state can be done only by disassembling the device and shortening testpad
43 * to the ground.
44 *
45 * To prevent this or to minimize the probability of such an accident, it was
46 * proposed to add the RCM rebooting hook as early into SPL as possible since
47 * SPL is much more robust and has minimal changes that can break bootflow.
48 *
Svyatoslav Ryhele1bc2ff2024-08-09 21:27:58 +030049 * pmic_enable_cpu_vdd() function was chosen as it is the earliest function
Svyatoslav Ryhel7be80312024-01-05 17:35:26 +020050 * exposed for setup by the device. Hook performs a check for volume up
51 * button state and triggers RCM if it is pressed.
52 */
Svyatoslav Ryhele1bc2ff2024-08-09 21:27:58 +030053void apx_hook(void)
Svyatoslav Ryhel7be80312024-01-05 17:35:26 +020054{
Svyatoslav Ryhele1bc2ff2024-08-09 21:27:58 +030055 int value;
Svyatoslav Ryhel7be80312024-01-05 17:35:26 +020056
57 /* Configure pinmux */
58 pinmux_set_func(PMUX_PINGRP_KB_ROW8_PS0, PMUX_FUNC_KBC);
59 pinmux_set_pullupdown(PMUX_PINGRP_KB_ROW8_PS0, PMUX_PULL_UP);
60 pinmux_tristate_disable(PMUX_PINGRP_KB_ROW8_PS0);
61 pinmux_set_io(PMUX_PINGRP_KB_ROW8_PS0, PMUX_PIN_INPUT);
62
Svyatoslav Ryhele1bc2ff2024-08-09 21:27:58 +030063 spl_gpio_input(NULL, TEGRA_GPIO(S, 0));
64 value = spl_gpio_get_value(NULL, TEGRA_GPIO(S, 0));
Svyatoslav Ryhel7be80312024-01-05 17:35:26 +020065
66 /* Enter RCM if button is pressed */
67 if (!value) {
68 tegra_pmc_writel(2, PMC_SCRATCH0);
69 tegra_pmc_writel(PMC_CNTRL_MAIN_RST, PMC_CNTRL);
70 }
71}
Svyatoslav Ryhele1bc2ff2024-08-09 21:27:58 +030072
73void pmic_enable_cpu_vdd(void)
74{
75 /* Check if RCM request is active */
76 apx_hook();
77
78 /* Set VDD_CORE to 1.200V. */
79 tegra_i2c_ll_write(TPS80032_DVS_I2C_ADDR, TPS80032_SMPS2_CFG_VOLTAGE_DATA);
80 udelay(1000);
81 tegra_i2c_ll_write(TPS80032_CTL1_I2C_ADDR, TPS80032_SMPS2_CFG_STATE_DATA);
82
83 udelay(1000);
84
85 /* Bring up VDD_CPU to 1.0125V. */
86 tegra_i2c_ll_write(TPS80032_DVS_I2C_ADDR, TPS80032_SMPS1_CFG_VOLTAGE_DATA);
87 udelay(1000);
88 tegra_i2c_ll_write(TPS80032_CTL1_I2C_ADDR, TPS80032_SMPS1_CFG_STATE_DATA);
89 udelay(10 * 1000);
90}