blob: 7921ff1a733379d9fda5d08a1ced4292e162af04 [file] [log] [blame]
Svyatoslav Ryhel4c5fe372023-06-30 10:29:06 +03001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * T30 HTC Endeavoru SPL stage configuration
4 *
5 * (C) Copyright 2010-2013
6 * NVIDIA Corporation <www.nvidia.com>
7 *
8 * (C) Copyright 2022
9 * Svyatoslav Ryhel <clamor95@gmail.com>
10 */
11
12#include <common.h>
13#include <asm/arch-tegra/tegra_i2c.h>
14#include <linux/delay.h>
15
16/*
17 * Endeavoru uses TPS80032 PMIC with SMPS1 and SMPS2 in strandard
18 * mode with zero offset.
19 */
20
21#define TPS80032_DVS_I2C_ADDR (0x12 << 1)
22#define TPS80032_SMPS1_CFG_VOLTAGE_REG 0x56
23#define TPS80032_SMPS2_CFG_VOLTAGE_REG 0x5C
24#define TPS80032_SMPS1_CFG_VOLTAGE_DATA (0x2100 | TPS80032_SMPS1_CFG_VOLTAGE_REG)
25#define TPS80032_SMPS2_CFG_VOLTAGE_DATA (0x3000 | TPS80032_SMPS2_CFG_VOLTAGE_REG)
26
27#define TPS80032_CTL1_I2C_ADDR (0x48 << 1)
28#define TPS80032_SMPS1_CFG_STATE_REG 0x54
29#define TPS80032_SMPS2_CFG_STATE_REG 0x5A
30#define TPS80032_SMPS1_CFG_STATE_DATA (0x0100 | TPS80032_SMPS1_CFG_STATE_REG)
31#define TPS80032_SMPS2_CFG_STATE_DATA (0x0100 | TPS80032_SMPS2_CFG_STATE_REG)
32
33void pmic_enable_cpu_vdd(void)
34{
35 /* Set VDD_CORE to 1.200V. */
36 tegra_i2c_ll_write(TPS80032_DVS_I2C_ADDR, TPS80032_SMPS2_CFG_VOLTAGE_DATA);
37 udelay(1000);
38 tegra_i2c_ll_write(TPS80032_CTL1_I2C_ADDR, TPS80032_SMPS2_CFG_STATE_DATA);
39
40 udelay(1000);
41
42 /* Bring up VDD_CPU to 1.0125V. */
43 tegra_i2c_ll_write(TPS80032_DVS_I2C_ADDR, TPS80032_SMPS1_CFG_VOLTAGE_DATA);
44 udelay(1000);
45 tegra_i2c_ll_write(TPS80032_CTL1_I2C_ADDR, TPS80032_SMPS1_CFG_STATE_DATA);
46 udelay(10 * 1000);
47}