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git01.mediatek.com / filogic / uboot / 965c01839fc50a3d69f80c82af676ff814623b81 / . / arch / arm / dts / k3-am642-evm-u-boot.dtsi
blob: b84307824368df132540e44964a1ee3027f07107 [file] [log] [blame]
Dave Gerlach278e7ac2021-04-23 11:27:46 -0500[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
4 */
5
Neha Malcom Francis9a1b2712023-07-22 00:14:34 +0530[diff] [blame]6#include "k3-am64x-binman.dtsi"
7
Dave Gerlach278e7ac2021-04-23 11:27:46 -0500[diff] [blame]8/ {
9 chosen {
Roger Quadrosaf6e2a72023-08-05 11:14:40 +0300[diff] [blame]10 tick-timer = &main_timer0;
Dave Gerlach278e7ac2021-04-23 11:27:46 -0500[diff] [blame]11 };
Georgi Vlaevd4d0db12022-05-20 15:30:26 +0300[diff] [blame]12
13 memory@80000000 {
Roger Quadros3405e9c2023-09-29 16:46:41 +0300[diff] [blame]14 bootph-all;
Georgi Vlaevd4d0db12022-05-20 15:30:26 +0300[diff] [blame]15 };
Dave Gerlach278e7ac2021-04-23 11:27:46 -0500[diff] [blame]16};
17
Roger Quadrosaf6e2a72023-08-05 11:14:40 +0300[diff] [blame]18&cbass_main {
Roger Quadros3405e9c2023-09-29 16:46:41 +0300[diff] [blame]19 bootph-all;
Roger Quadrosaf6e2a72023-08-05 11:14:40 +0300[diff] [blame]20};
21
Roger Quadrosaf6e2a72023-08-05 11:14:40 +0300[diff] [blame]22&main_timer0 {
Roger Quadros3405e9c2023-09-29 16:46:41 +0300[diff] [blame]23 bootph-all;
Roger Quadrosaf6e2a72023-08-05 11:14:40 +0300[diff] [blame]24 clock-frequency = <200000000>;
Dave Gerlach278e7ac2021-04-23 11:27:46 -0500[diff] [blame]25};
26
Lokesh Vutla882c7dd2021-05-06 16:44:56 +0530[diff] [blame]27&main_conf {
Roger Quadros3405e9c2023-09-29 16:46:41 +0300[diff] [blame]28 bootph-all;
Lokesh Vutla882c7dd2021-05-06 16:44:56 +0530[diff] [blame]29 chipid@14 {
Roger Quadros3405e9c2023-09-29 16:46:41 +0300[diff] [blame]30 bootph-all;
Lokesh Vutla882c7dd2021-05-06 16:44:56 +0530[diff] [blame]31 };
32};
33
Lokesh Vutla11ba7c22021-05-06 16:44:58 +0530[diff] [blame]34&main_pmx0 {
Roger Quadros3405e9c2023-09-29 16:46:41 +0300[diff] [blame]35 bootph-all;
Roger Quadrosaf6e2a72023-08-05 11:14:40 +0300[diff] [blame]36};
37
38&main_i2c0_pins_default {
Roger Quadros3405e9c2023-09-29 16:46:41 +0300[diff] [blame]39 bootph-all;
Lokesh Vutla11ba7c22021-05-06 16:44:58 +0530[diff] [blame]40};
41
42&main_i2c0 {
Roger Quadros3405e9c2023-09-29 16:46:41 +0300[diff] [blame]43 bootph-all;
Lokesh Vutla11ba7c22021-05-06 16:44:58 +0530[diff] [blame]44};
45
Roger Quadrosaf6e2a72023-08-05 11:14:40 +0300[diff] [blame]46&main_uart0_pins_default {
Roger Quadros3405e9c2023-09-29 16:46:41 +0300[diff] [blame]47 bootph-all;
Roger Quadrosaf6e2a72023-08-05 11:14:40 +0300[diff] [blame]48};
49
Dave Gerlach278e7ac2021-04-23 11:27:46 -0500[diff] [blame]50&main_uart0 {
Roger Quadros3405e9c2023-09-29 16:46:41 +0300[diff] [blame]51 bootph-all;
Dave Gerlach278e7ac2021-04-23 11:27:46 -0500[diff] [blame]52};
53
Roger Quadros12fdc4c2023-09-29 16:46:42 +0300[diff] [blame]54&main_usb0_pins_default {
55 bootph-all;
56};
57
Aswath Govindraju79087742021-06-04 22:00:37 +0530[diff] [blame]58&usb0 {
59 dr_mode="peripheral";
Roger Quadros3405e9c2023-09-29 16:46:41 +0300[diff] [blame]60 bootph-all;
Aswath Govindraju79087742021-06-04 22:00:37 +0530[diff] [blame]61};
62
63&usbss0 {
Roger Quadros3405e9c2023-09-29 16:46:41 +0300[diff] [blame]64 bootph-all;
Aswath Govindraju79087742021-06-04 22:00:37 +0530[diff] [blame]65};
66
Aswath Govindraju1786a7f2021-08-09 22:32:23 +0530[diff] [blame]67&main_mmc1_pins_default {
Roger Quadros3405e9c2023-09-29 16:46:41 +0300[diff] [blame]68 bootph-all;
Aswath Govindraju1786a7f2021-08-09 22:32:23 +0530[diff] [blame]69};
70
Aswath Govindraju79087742021-06-04 22:00:37 +0530[diff] [blame]71&main_usb0_pins_default {
Roger Quadros3405e9c2023-09-29 16:46:41 +0300[diff] [blame]72 bootph-all;
Aswath Govindraju79087742021-06-04 22:00:37 +0530[diff] [blame]73};
74
Dave Gerlach278e7ac2021-04-23 11:27:46 -0500[diff] [blame]75&dmss {
Roger Quadros3405e9c2023-09-29 16:46:41 +0300[diff] [blame]76 bootph-all;
Dave Gerlach278e7ac2021-04-23 11:27:46 -0500[diff] [blame]77};
78
79&secure_proxy_main {
Roger Quadros3405e9c2023-09-29 16:46:41 +0300[diff] [blame]80 bootph-all;
Dave Gerlach278e7ac2021-04-23 11:27:46 -0500[diff] [blame]81};
82
83&dmsc {
Roger Quadros3405e9c2023-09-29 16:46:41 +0300[diff] [blame]84 bootph-all;
Suman Annace4e5662021-05-13 20:10:56 -0500[diff] [blame]85 k3_sysreset: sysreset-controller {
86 compatible = "ti,sci-sysreset";
Roger Quadros3405e9c2023-09-29 16:46:41 +0300[diff] [blame]87 bootph-all;
Suman Annace4e5662021-05-13 20:10:56 -0500[diff] [blame]88 };
Dave Gerlach278e7ac2021-04-23 11:27:46 -0500[diff] [blame]89};
90
91&k3_pds {
Roger Quadros3405e9c2023-09-29 16:46:41 +0300[diff] [blame]92 bootph-all;
Dave Gerlach278e7ac2021-04-23 11:27:46 -0500[diff] [blame]93};
94
95&k3_clks {
Roger Quadros3405e9c2023-09-29 16:46:41 +0300[diff] [blame]96 bootph-all;
Dave Gerlach278e7ac2021-04-23 11:27:46 -0500[diff] [blame]97};
98
99&k3_reset {
Roger Quadros3405e9c2023-09-29 16:46:41 +0300[diff] [blame]100 bootph-all;
Dave Gerlach278e7ac2021-04-23 11:27:46 -0500[diff] [blame]101};
102
103&sdhci0 {
Roger Quadros3405e9c2023-09-29 16:46:41 +0300[diff] [blame]104 bootph-all;
Dave Gerlach278e7ac2021-04-23 11:27:46 -0500[diff] [blame]105};
106
Roger Quadros12fdc4c2023-09-29 16:46:42 +0300[diff] [blame]107&main_mmc1_pins_default {
108 bootph-all;
109};
110
Dave Gerlach278e7ac2021-04-23 11:27:46 -0500[diff] [blame]111&sdhci1 {
Roger Quadros3405e9c2023-09-29 16:46:41 +0300[diff] [blame]112 bootph-all;
Dave Gerlach278e7ac2021-04-23 11:27:46 -0500[diff] [blame]113};
Vignesh Raghavendra759316f2021-05-10 20:06:12 +0530[diff] [blame]114
Roger Quadros12fdc4c2023-09-29 16:46:42 +0300[diff] [blame]115&inta_main_dmss {
116 bootph-all;
117};
118
Siddharth Vadapallie4f41ae2023-10-28 20:36:03 +0300[diff] [blame]119&main_bcdma {
120 reg = <0x00 0x485c0100 0x00 0x100>,
121 <0x00 0x4c000000 0x00 0x20000>,
122 <0x00 0x4a820000 0x00 0x20000>,
123 <0x00 0x4aa40000 0x00 0x20000>,
124 <0x00 0x4bc00000 0x00 0x100000>,
125 <0x00 0x48600000 0x00 0x8000>,
126 <0x00 0x484a4000 0x00 0x2000>,
127 <0x00 0x484c2000 0x00 0x2000>;
128 reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt",
129 "cfg", "tchan", "rchan";
130};
131
Roger Quadros12fdc4c2023-09-29 16:46:42 +0300[diff] [blame]132&main_pktdma {
Siddharth Vadapallie4f41ae2023-10-28 20:36:03 +0300[diff] [blame]133 reg = <0x00 0x485c0000 0x00 0x100>,
134 <0x00 0x4a800000 0x00 0x20000>,
135 <0x00 0x4aa00000 0x00 0x40000>,
136 <0x00 0x4b800000 0x00 0x400000>,
137 <0x00 0x485e0000 0x00 0x20000>,
138 <0x00 0x484a0000 0x00 0x4000>,
139 <0x00 0x484c0000 0x00 0x2000>,
140 <0x00 0x48430000 0x00 0x4000>;
141 reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt", "cfg",
142 "tchan", "rchan", "rflow";
Roger Quadros12fdc4c2023-09-29 16:46:42 +0300[diff] [blame]143 bootph-all;
144};
145
146&mdio1_pins_default {
147 bootph-all;
148};
149
150&cpsw3g_mdio {
151 bootph-all;
152};
153
154&cpsw3g_phy0 {
155 bootph-all;
156};
157
158&rgmii1_pins_default {
159 bootph-all;
160};
161
162&rgmii2_pins_default {
163 bootph-all;
164};
165
Vignesh Raghavendra759316f2021-05-10 20:06:12 +0530[diff] [blame]166&cpsw3g {
Roger Quadros3405e9c2023-09-29 16:46:41 +0300[diff] [blame]167 bootph-all;
Roger Quadros12fdc4c2023-09-29 16:46:42 +0300[diff] [blame]168
169 ethernet-ports {
170 bootph-all;
171 };
172};
173
174&phy_gmii_sel {
175 bootph-all;
176};
177
178&cpsw_port1 {
179 bootph-all;
Vignesh Raghavendra759316f2021-05-10 20:06:12 +0530[diff] [blame]180};
181
182&cpsw_port2 {
183 status = "disabled";
184};