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Paul Burton4ff6b102015-01-29 01:27:57 +00001/*
2 * (C) Copyright 2003
3 * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8#include <common.h>
9#include <asm/cacheops.h>
Paul Burton3d6864a2017-05-12 13:26:11 +020010#ifdef CONFIG_MIPS_L2_CACHE
Paul Burton81560782016-09-21 11:18:54 +010011#include <asm/cm.h>
Paul Burton3d6864a2017-05-12 13:26:11 +020012#endif
Paul Burtonee3c0b82017-11-21 11:18:37 -080013#include <asm/io.h>
Paul Burton4ff6b102015-01-29 01:27:57 +000014#include <asm/mipsregs.h>
Paul Burton834f74e2017-11-21 11:18:38 -080015#include <asm/system.h>
Paul Burton4ff6b102015-01-29 01:27:57 +000016
Paul Burtondc2037e2016-09-21 11:18:48 +010017DECLARE_GLOBAL_DATA_PTR;
Paul Burton4ff6b102015-01-29 01:27:57 +000018
Paul Burton81560782016-09-21 11:18:54 +010019static void probe_l2(void)
20{
21#ifdef CONFIG_MIPS_L2_CACHE
22 unsigned long conf2, sl;
23 bool l2c = false;
24
25 if (!(read_c0_config1() & MIPS_CONF_M))
26 return;
27
28 conf2 = read_c0_config2();
29
30 if (__mips_isa_rev >= 6) {
31 l2c = conf2 & MIPS_CONF_M;
32 if (l2c)
33 l2c = read_c0_config3() & MIPS_CONF_M;
34 if (l2c)
35 l2c = read_c0_config4() & MIPS_CONF_M;
36 if (l2c)
37 l2c = read_c0_config5() & MIPS_CONF5_L2C;
38 }
39
40 if (l2c && config_enabled(CONFIG_MIPS_CM)) {
41 gd->arch.l2_line_size = mips_cm_l2_line_size();
42 } else if (l2c) {
43 /* We don't know how to retrieve L2 config on this system */
44 BUG();
45 } else {
46 sl = (conf2 & MIPS_CONF2_SL) >> MIPS_CONF2_SL_SHF;
47 gd->arch.l2_line_size = sl ? (2 << sl) : 0;
48 }
49#endif
50}
51
Paul Burtondc2037e2016-09-21 11:18:48 +010052void mips_cache_probe(void)
53{
54#ifdef CONFIG_SYS_CACHE_SIZE_AUTO
55 unsigned long conf1, il, dl;
Paul Burton4ff6b102015-01-29 01:27:57 +000056
Paul Burton4ff6b102015-01-29 01:27:57 +000057 conf1 = read_c0_config1();
Paul Burtondc2037e2016-09-21 11:18:48 +010058
Daniel Schwierzecka6dae712016-01-12 21:48:26 +010059 il = (conf1 & MIPS_CONF1_IL) >> MIPS_CONF1_IL_SHF;
Paul Burtondc2037e2016-09-21 11:18:48 +010060 dl = (conf1 & MIPS_CONF1_DL) >> MIPS_CONF1_DL_SHF;
61
62 gd->arch.l1i_line_size = il ? (2 << il) : 0;
63 gd->arch.l1d_line_size = dl ? (2 << dl) : 0;
64#endif
Paul Burton81560782016-09-21 11:18:54 +010065 probe_l2();
Paul Burton4ff6b102015-01-29 01:27:57 +000066}
67
Paul Burtondc2037e2016-09-21 11:18:48 +010068static inline unsigned long icache_line_size(void)
Paul Burton4ff6b102015-01-29 01:27:57 +000069{
Paul Burtondc2037e2016-09-21 11:18:48 +010070#ifdef CONFIG_SYS_CACHE_SIZE_AUTO
71 return gd->arch.l1i_line_size;
72#else
73 return CONFIG_SYS_ICACHE_LINE_SIZE;
74#endif
75}
Paul Burton62f13522016-05-27 14:28:05 +010076
Paul Burtondc2037e2016-09-21 11:18:48 +010077static inline unsigned long dcache_line_size(void)
78{
79#ifdef CONFIG_SYS_CACHE_SIZE_AUTO
80 return gd->arch.l1d_line_size;
81#else
82 return CONFIG_SYS_DCACHE_LINE_SIZE;
83#endif
Paul Burton4ff6b102015-01-29 01:27:57 +000084}
85
Paul Burton81560782016-09-21 11:18:54 +010086static inline unsigned long scache_line_size(void)
87{
88#ifdef CONFIG_MIPS_L2_CACHE
89 return gd->arch.l2_line_size;
90#else
91 return 0;
92#endif
93}
94
Paul Burtona97d5932016-05-27 14:28:06 +010095#define cache_loop(start, end, lsize, ops...) do { \
96 const void *addr = (const void *)(start & ~(lsize - 1)); \
97 const void *aend = (const void *)((end - 1) & ~(lsize - 1)); \
98 const unsigned int cache_ops[] = { ops }; \
99 unsigned int i; \
100 \
Paul Burtoned258e62017-11-21 11:18:39 -0800101 if (!lsize) \
102 break; \
103 \
Paul Burtona97d5932016-05-27 14:28:06 +0100104 for (; addr <= aend; addr += lsize) { \
105 for (i = 0; i < ARRAY_SIZE(cache_ops); i++) \
106 mips_cache(cache_ops[i], addr); \
107 } \
108} while (0)
109
Paul Burton4ff6b102015-01-29 01:27:57 +0000110void flush_cache(ulong start_addr, ulong size)
111{
112 unsigned long ilsize = icache_line_size();
113 unsigned long dlsize = dcache_line_size();
Paul Burton81560782016-09-21 11:18:54 +0100114 unsigned long slsize = scache_line_size();
Paul Burton4ff6b102015-01-29 01:27:57 +0000115
116 /* aend will be miscalculated when size is zero, so we return here */
117 if (size == 0)
118 return;
119
Paul Burton81560782016-09-21 11:18:54 +0100120 if ((ilsize == dlsize) && !slsize) {
Paul Burton4ff6b102015-01-29 01:27:57 +0000121 /* flush I-cache & D-cache simultaneously */
Paul Burtona97d5932016-05-27 14:28:06 +0100122 cache_loop(start_addr, start_addr + size, ilsize,
123 HIT_WRITEBACK_INV_D, HIT_INVALIDATE_I);
Paul Burtonee3c0b82017-11-21 11:18:37 -0800124 goto ops_done;
Paul Burton4ff6b102015-01-29 01:27:57 +0000125 }
126
127 /* flush D-cache */
Paul Burtona97d5932016-05-27 14:28:06 +0100128 cache_loop(start_addr, start_addr + size, dlsize, HIT_WRITEBACK_INV_D);
Paul Burton4ff6b102015-01-29 01:27:57 +0000129
Paul Burton81560782016-09-21 11:18:54 +0100130 /* flush L2 cache */
Paul Burtoned258e62017-11-21 11:18:39 -0800131 cache_loop(start_addr, start_addr + size, slsize, HIT_WRITEBACK_INV_SD);
Paul Burton81560782016-09-21 11:18:54 +0100132
Paul Burton4ff6b102015-01-29 01:27:57 +0000133 /* flush I-cache */
Paul Burtona97d5932016-05-27 14:28:06 +0100134 cache_loop(start_addr, start_addr + size, ilsize, HIT_INVALIDATE_I);
Paul Burtonee3c0b82017-11-21 11:18:37 -0800135
136ops_done:
137 /* ensure cache ops complete before any further memory accesses */
138 sync();
Paul Burton834f74e2017-11-21 11:18:38 -0800139
140 /* ensure the pipeline doesn't contain now-invalid instructions */
141 instruction_hazard_barrier();
Paul Burton4ff6b102015-01-29 01:27:57 +0000142}
143
144void flush_dcache_range(ulong start_addr, ulong stop)
145{
146 unsigned long lsize = dcache_line_size();
Paul Burton81560782016-09-21 11:18:54 +0100147 unsigned long slsize = scache_line_size();
Paul Burton4ff6b102015-01-29 01:27:57 +0000148
Marek Vasut0e50ffc2016-01-27 03:13:59 +0100149 /* aend will be miscalculated when size is zero, so we return here */
150 if (start_addr == stop)
151 return;
152
Paul Burtona97d5932016-05-27 14:28:06 +0100153 cache_loop(start_addr, stop, lsize, HIT_WRITEBACK_INV_D);
Paul Burton81560782016-09-21 11:18:54 +0100154
155 /* flush L2 cache */
Paul Burtoned258e62017-11-21 11:18:39 -0800156 cache_loop(start_addr, stop, slsize, HIT_WRITEBACK_INV_SD);
Paul Burtonee3c0b82017-11-21 11:18:37 -0800157
158 /* ensure cache ops complete before any further memory accesses */
159 sync();
Paul Burton4ff6b102015-01-29 01:27:57 +0000160}
161
162void invalidate_dcache_range(ulong start_addr, ulong stop)
163{
164 unsigned long lsize = dcache_line_size();
Paul Burton81560782016-09-21 11:18:54 +0100165 unsigned long slsize = scache_line_size();
Paul Burton4ff6b102015-01-29 01:27:57 +0000166
Marek Vasut0e50ffc2016-01-27 03:13:59 +0100167 /* aend will be miscalculated when size is zero, so we return here */
168 if (start_addr == stop)
169 return;
170
Paul Burton81560782016-09-21 11:18:54 +0100171 /* invalidate L2 cache */
Paul Burtoned258e62017-11-21 11:18:39 -0800172 cache_loop(start_addr, stop, slsize, HIT_INVALIDATE_SD);
Paul Burton81560782016-09-21 11:18:54 +0100173
Paul Burton1194f942016-06-09 13:09:51 +0100174 cache_loop(start_addr, stop, lsize, HIT_INVALIDATE_D);
Paul Burtonee3c0b82017-11-21 11:18:37 -0800175
176 /* ensure cache ops complete before any further memory accesses */
177 sync();
Paul Burton4ff6b102015-01-29 01:27:57 +0000178}