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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Jon Loeliger5c8aa972006-04-26 17:58:56 -05002/*
Kumar Gala365024c2011-01-31 15:51:20 -06003 * Copyright 2006, 2007, 2010-2011 Freescale Semiconductor.
Jon Loeliger5c8aa972006-04-26 17:58:56 -05004 */
5
6#include <common.h>
Simon Glass18afe102019-11-14 12:57:47 -07007#include <init.h>
Simon Glass0f2af882020-05-10 11:40:05 -06008#include <log.h>
Simon Glass274e0b02020-05-10 11:39:56 -06009#include <net.h>
Jon Loeliger5c8aa972006-04-26 17:58:56 -050010#include <pci.h>
11#include <asm/processor.h>
12#include <asm/immap_86xx.h>
Kumar Gala9bbd6432009-04-02 13:22:48 -050013#include <asm/fsl_pci.h>
York Sunf0626592013-09-30 09:22:09 -070014#include <fsl_ddr_sdram.h>
Kumar Gala3d020382010-12-15 04:55:20 -060015#include <asm/fsl_serdes.h>
Haiying Wang57b6e9c2007-01-22 12:37:30 -060016#include <asm/io.h>
Simon Glassdbd79542020-05-10 11:40:11 -060017#include <linux/delay.h>
Masahiro Yamada75f82d02018-03-05 01:20:11 +090018#include <linux/libfdt.h>
Jon Loeliger6160aa42007-11-28 14:47:18 -060019#include <fdt_support.h>
Ben Warren65b86232008-08-31 21:41:08 -070020#include <netdev.h>
Jon Loeliger5c8aa972006-04-26 17:58:56 -050021
Simon Glass39f90ba2017-03-31 08:40:25 -060022DECLARE_GLOBAL_DATA_PTR;
23
Becky Brucecc064ed2008-10-31 17:13:32 -050024phys_size_t fixed_sdram(void);
Jon Loeliger5c8aa972006-04-26 17:58:56 -050025
Jon Loeliger4fbb09c2006-08-22 12:25:27 -050026int checkboard(void)
Jon Loeliger5c8aa972006-04-26 17:58:56 -050027{
Kumar Galaaba63972009-07-15 13:45:00 -050028 u8 vboot;
29 u8 *pixis_base = (u8 *)PIXIS_BASE;
30
31 printf ("Board: MPC8641HPCN, Sys ID: 0x%02x, "
32 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
33 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
34 in_8(pixis_base + PIXIS_PVER));
35
36 vboot = in_8(pixis_base + PIXIS_VBOOT);
37 if (vboot & PIXIS_VBOOT_FMAP)
38 printf ("vBank: %d\n", ((vboot & PIXIS_VBOOT_FBANK) >> 6));
39 else
40 puts ("Promjet\n");
41
Jon Loeliger5c8aa972006-04-26 17:58:56 -050042 return 0;
43}
44
Simon Glassd35f3382017-04-06 12:47:05 -060045int dram_init(void)
Jon Loeliger5c8aa972006-04-26 17:58:56 -050046{
Becky Brucecc064ed2008-10-31 17:13:32 -050047 phys_size_t dram_size = 0;
Jon Loeliger5c8aa972006-04-26 17:58:56 -050048
49#if defined(CONFIG_SPD_EEPROM)
Kumar Galacad506c2008-08-26 15:01:35 -050050 dram_size = fsl_ddr_sdram();
Jon Loeliger5c8aa972006-04-26 17:58:56 -050051#else
Jon Loeliger4fbb09c2006-08-22 12:25:27 -050052 dram_size = fixed_sdram();
Jon Loeliger5c8aa972006-04-26 17:58:56 -050053#endif
54
Timur Tabi107e9cd2010-03-29 12:51:07 -050055 setup_ddr_bat(dram_size);
56
Wolfgang Denkf2bbb532011-07-25 10:13:53 +020057 debug(" DDR: ");
Simon Glass39f90ba2017-03-31 08:40:25 -060058 gd->ram_size = dram_size;
59
60 return 0;
Jon Loeliger5c8aa972006-04-26 17:58:56 -050061}
62
Jon Loeliger5c8aa972006-04-26 17:58:56 -050063
Jon Loeliger5c8aa972006-04-26 17:58:56 -050064#if !defined(CONFIG_SPD_EEPROM)
Jon Loeliger465b9d82006-04-27 10:15:16 -050065/*
66 * Fixed sdram init -- doesn't use serial presence detect.
67 */
Becky Brucecc064ed2008-10-31 17:13:32 -050068phys_size_t
Jon Loeliger4fbb09c2006-08-22 12:25:27 -050069fixed_sdram(void)
Jon Loeliger5c8aa972006-04-26 17:58:56 -050070{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020071#if !defined(CONFIG_SYS_RAMBOOT)
72 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
York Suna21803d2013-11-18 10:29:32 -080073 struct ccsr_ddr __iomem *ddr = &immap->im_ddr1;
Jon Loeliger5c8aa972006-04-26 17:58:56 -050074
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020075 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
76 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
77 ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
78 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
79 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
80 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
Peter Tyseraf5829cb2009-07-17 10:14:45 -050081 ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020082 ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
83 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
84 ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
85 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
86 ddr->sdram_ocd_cntl = CONFIG_SYS_DDR_OCD_CTRL;
87 ddr->sdram_ocd_status = CONFIG_SYS_DDR_OCD_STATUS;
Jon Loeliger5c8aa972006-04-26 17:58:56 -050088
89#if defined (CONFIG_DDR_ECC)
90 ddr->err_disable = 0x0000008D;
91 ddr->err_sbe = 0x00ff0000;
92#endif
93 asm("sync;isync");
Jon Loeligere65e32e2006-05-31 12:44:44 -050094
Jon Loeliger5c8aa972006-04-26 17:58:56 -050095 udelay(500);
96
97#if defined (CONFIG_DDR_ECC)
98 /* Enable ECC checking */
Peter Tyseraf5829cb2009-07-17 10:14:45 -050099 ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
Jon Loeliger5c8aa972006-04-26 17:58:56 -0500100#else
Peter Tyseraf5829cb2009-07-17 10:14:45 -0500101 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200102 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
Jon Loeliger5c8aa972006-04-26 17:58:56 -0500103#endif
104 asm("sync; isync");
Jon Loeligere65e32e2006-05-31 12:44:44 -0500105
Jon Loeliger5c8aa972006-04-26 17:58:56 -0500106 udelay(500);
107#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200108 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
Jon Loeliger5c8aa972006-04-26 17:58:56 -0500109}
110#endif /* !defined(CONFIG_SPD_EEPROM) */
111
Jon Loeliger4fbb09c2006-08-22 12:25:27 -0500112void pci_init_board(void)
Jon Loeliger5c8aa972006-04-26 17:58:56 -0500113{
Kumar Galadbbfb002010-12-17 10:47:36 -0600114 fsl_pcie_init_board(0);
Peter Tyser8d6f9fa2010-09-29 13:37:26 -0500115
Kumar Galae78f6652010-07-09 00:02:34 -0500116#ifdef CONFIG_PCIE1
Ed Swarthout91080f72007-08-02 14:09:49 -0500117 /*
118 * Activate ULI1575 legacy chip by performing a fake
119 * memory access. Needed to make ULI RTC work.
120 */
Kumar Galae78f6652010-07-09 00:02:34 -0500121 in_be32((unsigned *) ((char *)(CONFIG_SYS_PCIE1_MEM_VIRT
122 + CONFIG_SYS_PCIE1_MEM_SIZE - 0x1000000)));
Kumar Galae78f6652010-07-09 00:02:34 -0500123#endif /* CONFIG_PCIE1 */
Jon Loeliger5c8aa972006-04-26 17:58:56 -0500124}
125
Jon Loeliger84640c92008-02-18 14:01:56 -0600126
Jon Loeliger6160aa42007-11-28 14:47:18 -0600127#if defined(CONFIG_OF_BOARD_SETUP)
Simon Glass2aec3cc2014-10-23 18:58:47 -0600128int ft_board_setup(void *blob, bd_t *bd)
Jon Loeliger5c8aa972006-04-26 17:58:56 -0500129{
Becky Bruce48d3ce22008-11-07 13:46:19 -0600130 int off;
131 u64 *tmp;
Simon Glass9fbc6322014-10-23 18:58:57 -0600132 int addrcells;
Becky Bruce48d3ce22008-11-07 13:46:19 -0600133
Jon Loeliger84640c92008-02-18 14:01:56 -0600134 ft_cpu_setup(blob, bd);
Jon Loeliger6160aa42007-11-28 14:47:18 -0600135
Kumar Galad0f27d32010-07-08 22:37:44 -0500136 FT_FSL_PCI_SETUP;
Becky Bruce48d3ce22008-11-07 13:46:19 -0600137
138 /*
139 * Warn if it looks like the device tree doesn't match u-boot.
140 * This is just an estimation, based on the location of CCSR,
141 * which is defined by the "reg" property in the soc node.
142 */
143 off = fdt_path_offset(blob, "/soc8641");
Simon Glass9fbc6322014-10-23 18:58:57 -0600144 addrcells = fdt_address_cells(blob, 0);
Becky Bruce48d3ce22008-11-07 13:46:19 -0600145 tmp = (u64 *)fdt_getprop(blob, off, "reg", NULL);
146
147 if (tmp) {
148 u64 addr;
Simon Glass9fbc6322014-10-23 18:58:57 -0600149
150 if (addrcells == 1)
Becky Bruce48d3ce22008-11-07 13:46:19 -0600151 addr = *(u32 *)tmp;
Becky Bruceeccb5e72008-11-10 19:45:35 -0600152 else
153 addr = *tmp;
Becky Bruce48d3ce22008-11-07 13:46:19 -0600154
155 if (addr != CONFIG_SYS_CCSRBAR_PHYS)
156 printf("WARNING: The CCSRBAR address in your .dts "
157 "does not match the address of the CCSR "
158 "in u-boot. This means your .dts might "
159 "be old.\n");
160 }
Simon Glass2aec3cc2014-10-23 18:58:47 -0600161
162 return 0;
Jon Loeliger5c8aa972006-04-26 17:58:56 -0500163}
164#endif
165
Jon Loeliger72f8a8e2006-05-31 11:24:28 -0500166
Haiying Wang43d624d2006-07-28 12:41:18 -0400167/*
168 * get_board_sys_clk
169 * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ
170 */
171
Jon Loeliger4fbb09c2006-08-22 12:25:27 -0500172unsigned long
173get_board_sys_clk(ulong dummy)
Haiying Wang43d624d2006-07-28 12:41:18 -0400174{
175 u8 i, go_bit, rd_clks;
176 ulong val = 0;
Kumar Gala146c4b22009-07-22 10:12:39 -0500177 u8 *pixis_base = (u8 *)PIXIS_BASE;
Haiying Wang43d624d2006-07-28 12:41:18 -0400178
Kumar Gala146c4b22009-07-22 10:12:39 -0500179 go_bit = in_8(pixis_base + PIXIS_VCTL);
Haiying Wang43d624d2006-07-28 12:41:18 -0400180 go_bit &= 0x01;
181
Kumar Gala146c4b22009-07-22 10:12:39 -0500182 rd_clks = in_8(pixis_base + PIXIS_VCFGEN0);
Haiying Wang43d624d2006-07-28 12:41:18 -0400183 rd_clks &= 0x1C;
184
185 /*
186 * Only if both go bit and the SCLK bit in VCFGEN0 are set
187 * should we be using the AUX register. Remember, we also set the
188 * GO bit to boot from the alternate bank on the on-board flash
189 */
190
191 if (go_bit) {
192 if (rd_clks == 0x1c)
Kumar Gala146c4b22009-07-22 10:12:39 -0500193 i = in_8(pixis_base + PIXIS_AUX);
Haiying Wang43d624d2006-07-28 12:41:18 -0400194 else
Kumar Gala146c4b22009-07-22 10:12:39 -0500195 i = in_8(pixis_base + PIXIS_SPD);
Haiying Wang43d624d2006-07-28 12:41:18 -0400196 } else {
Kumar Gala146c4b22009-07-22 10:12:39 -0500197 i = in_8(pixis_base + PIXIS_SPD);
Haiying Wang43d624d2006-07-28 12:41:18 -0400198 }
199
200 i &= 0x07;
201
202 switch (i) {
203 case 0:
204 val = 33000000;
205 break;
206 case 1:
207 val = 40000000;
208 break;
209 case 2:
210 val = 50000000;
211 break;
212 case 3:
213 val = 66000000;
214 break;
215 case 4:
216 val = 83000000;
217 break;
218 case 5:
219 val = 100000000;
220 break;
221 case 6:
222 val = 134000000;
223 break;
224 case 7:
225 val = 166000000;
226 break;
227 }
228
229 return val;
230}
Ben Warren65b86232008-08-31 21:41:08 -0700231
232int board_eth_init(bd_t *bis)
233{
234 /* Initialize TSECs */
235 cpu_eth_init(bis);
236 return pci_eth_init(bis);
237}
Peter Tyser69454402009-02-05 11:25:25 -0600238
239void board_reset(void)
240{
Kumar Gala146c4b22009-07-22 10:12:39 -0500241 u8 *pixis_base = (u8 *)PIXIS_BASE;
242
243 out_8(pixis_base + PIXIS_RST, 0);
Peter Tyser69454402009-02-05 11:25:25 -0600244
245 while (1)
246 ;
247}