Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Jon Loeliger | 5c8aa97 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 2 | /* |
Kumar Gala | 365024c | 2011-01-31 15:51:20 -0600 | [diff] [blame] | 3 | * Copyright 2006, 2007, 2010-2011 Freescale Semiconductor. |
Jon Loeliger | 5c8aa97 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #include <common.h> |
Simon Glass | 18afe10 | 2019-11-14 12:57:47 -0700 | [diff] [blame] | 7 | #include <init.h> |
Simon Glass | 0f2af88 | 2020-05-10 11:40:05 -0600 | [diff] [blame] | 8 | #include <log.h> |
Simon Glass | 274e0b0 | 2020-05-10 11:39:56 -0600 | [diff] [blame] | 9 | #include <net.h> |
Jon Loeliger | 5c8aa97 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 10 | #include <pci.h> |
| 11 | #include <asm/processor.h> |
| 12 | #include <asm/immap_86xx.h> |
Kumar Gala | 9bbd643 | 2009-04-02 13:22:48 -0500 | [diff] [blame] | 13 | #include <asm/fsl_pci.h> |
York Sun | f062659 | 2013-09-30 09:22:09 -0700 | [diff] [blame] | 14 | #include <fsl_ddr_sdram.h> |
Kumar Gala | 3d02038 | 2010-12-15 04:55:20 -0600 | [diff] [blame] | 15 | #include <asm/fsl_serdes.h> |
Haiying Wang | 57b6e9c | 2007-01-22 12:37:30 -0600 | [diff] [blame] | 16 | #include <asm/io.h> |
Simon Glass | dbd7954 | 2020-05-10 11:40:11 -0600 | [diff] [blame] | 17 | #include <linux/delay.h> |
Masahiro Yamada | 75f82d0 | 2018-03-05 01:20:11 +0900 | [diff] [blame] | 18 | #include <linux/libfdt.h> |
Jon Loeliger | 6160aa4 | 2007-11-28 14:47:18 -0600 | [diff] [blame] | 19 | #include <fdt_support.h> |
Ben Warren | 65b8623 | 2008-08-31 21:41:08 -0700 | [diff] [blame] | 20 | #include <netdev.h> |
Jon Loeliger | 5c8aa97 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 21 | |
Simon Glass | 39f90ba | 2017-03-31 08:40:25 -0600 | [diff] [blame] | 22 | DECLARE_GLOBAL_DATA_PTR; |
| 23 | |
Becky Bruce | cc064ed | 2008-10-31 17:13:32 -0500 | [diff] [blame] | 24 | phys_size_t fixed_sdram(void); |
Jon Loeliger | 5c8aa97 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 25 | |
Jon Loeliger | 4fbb09c | 2006-08-22 12:25:27 -0500 | [diff] [blame] | 26 | int checkboard(void) |
Jon Loeliger | 5c8aa97 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 27 | { |
Kumar Gala | aba6397 | 2009-07-15 13:45:00 -0500 | [diff] [blame] | 28 | u8 vboot; |
| 29 | u8 *pixis_base = (u8 *)PIXIS_BASE; |
| 30 | |
| 31 | printf ("Board: MPC8641HPCN, Sys ID: 0x%02x, " |
| 32 | "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", |
| 33 | in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER), |
| 34 | in_8(pixis_base + PIXIS_PVER)); |
| 35 | |
| 36 | vboot = in_8(pixis_base + PIXIS_VBOOT); |
| 37 | if (vboot & PIXIS_VBOOT_FMAP) |
| 38 | printf ("vBank: %d\n", ((vboot & PIXIS_VBOOT_FBANK) >> 6)); |
| 39 | else |
| 40 | puts ("Promjet\n"); |
| 41 | |
Jon Loeliger | 5c8aa97 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 42 | return 0; |
| 43 | } |
| 44 | |
Simon Glass | d35f338 | 2017-04-06 12:47:05 -0600 | [diff] [blame] | 45 | int dram_init(void) |
Jon Loeliger | 5c8aa97 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 46 | { |
Becky Bruce | cc064ed | 2008-10-31 17:13:32 -0500 | [diff] [blame] | 47 | phys_size_t dram_size = 0; |
Jon Loeliger | 5c8aa97 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 48 | |
| 49 | #if defined(CONFIG_SPD_EEPROM) |
Kumar Gala | cad506c | 2008-08-26 15:01:35 -0500 | [diff] [blame] | 50 | dram_size = fsl_ddr_sdram(); |
Jon Loeliger | 5c8aa97 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 51 | #else |
Jon Loeliger | 4fbb09c | 2006-08-22 12:25:27 -0500 | [diff] [blame] | 52 | dram_size = fixed_sdram(); |
Jon Loeliger | 5c8aa97 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 53 | #endif |
| 54 | |
Timur Tabi | 107e9cd | 2010-03-29 12:51:07 -0500 | [diff] [blame] | 55 | setup_ddr_bat(dram_size); |
| 56 | |
Wolfgang Denk | f2bbb53 | 2011-07-25 10:13:53 +0200 | [diff] [blame] | 57 | debug(" DDR: "); |
Simon Glass | 39f90ba | 2017-03-31 08:40:25 -0600 | [diff] [blame] | 58 | gd->ram_size = dram_size; |
| 59 | |
| 60 | return 0; |
Jon Loeliger | 5c8aa97 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 61 | } |
| 62 | |
Jon Loeliger | 5c8aa97 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 63 | |
Jon Loeliger | 5c8aa97 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 64 | #if !defined(CONFIG_SPD_EEPROM) |
Jon Loeliger | 465b9d8 | 2006-04-27 10:15:16 -0500 | [diff] [blame] | 65 | /* |
| 66 | * Fixed sdram init -- doesn't use serial presence detect. |
| 67 | */ |
Becky Bruce | cc064ed | 2008-10-31 17:13:32 -0500 | [diff] [blame] | 68 | phys_size_t |
Jon Loeliger | 4fbb09c | 2006-08-22 12:25:27 -0500 | [diff] [blame] | 69 | fixed_sdram(void) |
Jon Loeliger | 5c8aa97 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 70 | { |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 71 | #if !defined(CONFIG_SYS_RAMBOOT) |
| 72 | volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; |
York Sun | a21803d | 2013-11-18 10:29:32 -0800 | [diff] [blame] | 73 | struct ccsr_ddr __iomem *ddr = &immap->im_ddr1; |
Jon Loeliger | 5c8aa97 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 74 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 75 | ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; |
| 76 | ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; |
| 77 | ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; |
| 78 | ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; |
| 79 | ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; |
| 80 | ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; |
Peter Tyser | af5829cb | 2009-07-17 10:14:45 -0500 | [diff] [blame] | 81 | ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1; |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 82 | ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2; |
| 83 | ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; |
| 84 | ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT; |
| 85 | ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL; |
| 86 | ddr->sdram_ocd_cntl = CONFIG_SYS_DDR_OCD_CTRL; |
| 87 | ddr->sdram_ocd_status = CONFIG_SYS_DDR_OCD_STATUS; |
Jon Loeliger | 5c8aa97 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 88 | |
| 89 | #if defined (CONFIG_DDR_ECC) |
| 90 | ddr->err_disable = 0x0000008D; |
| 91 | ddr->err_sbe = 0x00ff0000; |
| 92 | #endif |
| 93 | asm("sync;isync"); |
Jon Loeliger | e65e32e | 2006-05-31 12:44:44 -0500 | [diff] [blame] | 94 | |
Jon Loeliger | 5c8aa97 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 95 | udelay(500); |
| 96 | |
| 97 | #if defined (CONFIG_DDR_ECC) |
| 98 | /* Enable ECC checking */ |
Peter Tyser | af5829cb | 2009-07-17 10:14:45 -0500 | [diff] [blame] | 99 | ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000); |
Jon Loeliger | 5c8aa97 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 100 | #else |
Peter Tyser | af5829cb | 2009-07-17 10:14:45 -0500 | [diff] [blame] | 101 | ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL; |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 102 | ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2; |
Jon Loeliger | 5c8aa97 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 103 | #endif |
| 104 | asm("sync; isync"); |
Jon Loeliger | e65e32e | 2006-05-31 12:44:44 -0500 | [diff] [blame] | 105 | |
Jon Loeliger | 5c8aa97 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 106 | udelay(500); |
| 107 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 108 | return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; |
Jon Loeliger | 5c8aa97 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 109 | } |
| 110 | #endif /* !defined(CONFIG_SPD_EEPROM) */ |
| 111 | |
Jon Loeliger | 4fbb09c | 2006-08-22 12:25:27 -0500 | [diff] [blame] | 112 | void pci_init_board(void) |
Jon Loeliger | 5c8aa97 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 113 | { |
Kumar Gala | dbbfb00 | 2010-12-17 10:47:36 -0600 | [diff] [blame] | 114 | fsl_pcie_init_board(0); |
Peter Tyser | 8d6f9fa | 2010-09-29 13:37:26 -0500 | [diff] [blame] | 115 | |
Kumar Gala | e78f665 | 2010-07-09 00:02:34 -0500 | [diff] [blame] | 116 | #ifdef CONFIG_PCIE1 |
Ed Swarthout | 91080f7 | 2007-08-02 14:09:49 -0500 | [diff] [blame] | 117 | /* |
| 118 | * Activate ULI1575 legacy chip by performing a fake |
| 119 | * memory access. Needed to make ULI RTC work. |
| 120 | */ |
Kumar Gala | e78f665 | 2010-07-09 00:02:34 -0500 | [diff] [blame] | 121 | in_be32((unsigned *) ((char *)(CONFIG_SYS_PCIE1_MEM_VIRT |
| 122 | + CONFIG_SYS_PCIE1_MEM_SIZE - 0x1000000))); |
Kumar Gala | e78f665 | 2010-07-09 00:02:34 -0500 | [diff] [blame] | 123 | #endif /* CONFIG_PCIE1 */ |
Jon Loeliger | 5c8aa97 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 124 | } |
| 125 | |
Jon Loeliger | 84640c9 | 2008-02-18 14:01:56 -0600 | [diff] [blame] | 126 | |
Jon Loeliger | 6160aa4 | 2007-11-28 14:47:18 -0600 | [diff] [blame] | 127 | #if defined(CONFIG_OF_BOARD_SETUP) |
Simon Glass | 2aec3cc | 2014-10-23 18:58:47 -0600 | [diff] [blame] | 128 | int ft_board_setup(void *blob, bd_t *bd) |
Jon Loeliger | 5c8aa97 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 129 | { |
Becky Bruce | 48d3ce2 | 2008-11-07 13:46:19 -0600 | [diff] [blame] | 130 | int off; |
| 131 | u64 *tmp; |
Simon Glass | 9fbc632 | 2014-10-23 18:58:57 -0600 | [diff] [blame] | 132 | int addrcells; |
Becky Bruce | 48d3ce2 | 2008-11-07 13:46:19 -0600 | [diff] [blame] | 133 | |
Jon Loeliger | 84640c9 | 2008-02-18 14:01:56 -0600 | [diff] [blame] | 134 | ft_cpu_setup(blob, bd); |
Jon Loeliger | 6160aa4 | 2007-11-28 14:47:18 -0600 | [diff] [blame] | 135 | |
Kumar Gala | d0f27d3 | 2010-07-08 22:37:44 -0500 | [diff] [blame] | 136 | FT_FSL_PCI_SETUP; |
Becky Bruce | 48d3ce2 | 2008-11-07 13:46:19 -0600 | [diff] [blame] | 137 | |
| 138 | /* |
| 139 | * Warn if it looks like the device tree doesn't match u-boot. |
| 140 | * This is just an estimation, based on the location of CCSR, |
| 141 | * which is defined by the "reg" property in the soc node. |
| 142 | */ |
| 143 | off = fdt_path_offset(blob, "/soc8641"); |
Simon Glass | 9fbc632 | 2014-10-23 18:58:57 -0600 | [diff] [blame] | 144 | addrcells = fdt_address_cells(blob, 0); |
Becky Bruce | 48d3ce2 | 2008-11-07 13:46:19 -0600 | [diff] [blame] | 145 | tmp = (u64 *)fdt_getprop(blob, off, "reg", NULL); |
| 146 | |
| 147 | if (tmp) { |
| 148 | u64 addr; |
Simon Glass | 9fbc632 | 2014-10-23 18:58:57 -0600 | [diff] [blame] | 149 | |
| 150 | if (addrcells == 1) |
Becky Bruce | 48d3ce2 | 2008-11-07 13:46:19 -0600 | [diff] [blame] | 151 | addr = *(u32 *)tmp; |
Becky Bruce | eccb5e7 | 2008-11-10 19:45:35 -0600 | [diff] [blame] | 152 | else |
| 153 | addr = *tmp; |
Becky Bruce | 48d3ce2 | 2008-11-07 13:46:19 -0600 | [diff] [blame] | 154 | |
| 155 | if (addr != CONFIG_SYS_CCSRBAR_PHYS) |
| 156 | printf("WARNING: The CCSRBAR address in your .dts " |
| 157 | "does not match the address of the CCSR " |
| 158 | "in u-boot. This means your .dts might " |
| 159 | "be old.\n"); |
| 160 | } |
Simon Glass | 2aec3cc | 2014-10-23 18:58:47 -0600 | [diff] [blame] | 161 | |
| 162 | return 0; |
Jon Loeliger | 5c8aa97 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 163 | } |
| 164 | #endif |
| 165 | |
Jon Loeliger | 72f8a8e | 2006-05-31 11:24:28 -0500 | [diff] [blame] | 166 | |
Haiying Wang | 43d624d | 2006-07-28 12:41:18 -0400 | [diff] [blame] | 167 | /* |
| 168 | * get_board_sys_clk |
| 169 | * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ |
| 170 | */ |
| 171 | |
Jon Loeliger | 4fbb09c | 2006-08-22 12:25:27 -0500 | [diff] [blame] | 172 | unsigned long |
| 173 | get_board_sys_clk(ulong dummy) |
Haiying Wang | 43d624d | 2006-07-28 12:41:18 -0400 | [diff] [blame] | 174 | { |
| 175 | u8 i, go_bit, rd_clks; |
| 176 | ulong val = 0; |
Kumar Gala | 146c4b2 | 2009-07-22 10:12:39 -0500 | [diff] [blame] | 177 | u8 *pixis_base = (u8 *)PIXIS_BASE; |
Haiying Wang | 43d624d | 2006-07-28 12:41:18 -0400 | [diff] [blame] | 178 | |
Kumar Gala | 146c4b2 | 2009-07-22 10:12:39 -0500 | [diff] [blame] | 179 | go_bit = in_8(pixis_base + PIXIS_VCTL); |
Haiying Wang | 43d624d | 2006-07-28 12:41:18 -0400 | [diff] [blame] | 180 | go_bit &= 0x01; |
| 181 | |
Kumar Gala | 146c4b2 | 2009-07-22 10:12:39 -0500 | [diff] [blame] | 182 | rd_clks = in_8(pixis_base + PIXIS_VCFGEN0); |
Haiying Wang | 43d624d | 2006-07-28 12:41:18 -0400 | [diff] [blame] | 183 | rd_clks &= 0x1C; |
| 184 | |
| 185 | /* |
| 186 | * Only if both go bit and the SCLK bit in VCFGEN0 are set |
| 187 | * should we be using the AUX register. Remember, we also set the |
| 188 | * GO bit to boot from the alternate bank on the on-board flash |
| 189 | */ |
| 190 | |
| 191 | if (go_bit) { |
| 192 | if (rd_clks == 0x1c) |
Kumar Gala | 146c4b2 | 2009-07-22 10:12:39 -0500 | [diff] [blame] | 193 | i = in_8(pixis_base + PIXIS_AUX); |
Haiying Wang | 43d624d | 2006-07-28 12:41:18 -0400 | [diff] [blame] | 194 | else |
Kumar Gala | 146c4b2 | 2009-07-22 10:12:39 -0500 | [diff] [blame] | 195 | i = in_8(pixis_base + PIXIS_SPD); |
Haiying Wang | 43d624d | 2006-07-28 12:41:18 -0400 | [diff] [blame] | 196 | } else { |
Kumar Gala | 146c4b2 | 2009-07-22 10:12:39 -0500 | [diff] [blame] | 197 | i = in_8(pixis_base + PIXIS_SPD); |
Haiying Wang | 43d624d | 2006-07-28 12:41:18 -0400 | [diff] [blame] | 198 | } |
| 199 | |
| 200 | i &= 0x07; |
| 201 | |
| 202 | switch (i) { |
| 203 | case 0: |
| 204 | val = 33000000; |
| 205 | break; |
| 206 | case 1: |
| 207 | val = 40000000; |
| 208 | break; |
| 209 | case 2: |
| 210 | val = 50000000; |
| 211 | break; |
| 212 | case 3: |
| 213 | val = 66000000; |
| 214 | break; |
| 215 | case 4: |
| 216 | val = 83000000; |
| 217 | break; |
| 218 | case 5: |
| 219 | val = 100000000; |
| 220 | break; |
| 221 | case 6: |
| 222 | val = 134000000; |
| 223 | break; |
| 224 | case 7: |
| 225 | val = 166000000; |
| 226 | break; |
| 227 | } |
| 228 | |
| 229 | return val; |
| 230 | } |
Ben Warren | 65b8623 | 2008-08-31 21:41:08 -0700 | [diff] [blame] | 231 | |
| 232 | int board_eth_init(bd_t *bis) |
| 233 | { |
| 234 | /* Initialize TSECs */ |
| 235 | cpu_eth_init(bis); |
| 236 | return pci_eth_init(bis); |
| 237 | } |
Peter Tyser | 6945440 | 2009-02-05 11:25:25 -0600 | [diff] [blame] | 238 | |
| 239 | void board_reset(void) |
| 240 | { |
Kumar Gala | 146c4b2 | 2009-07-22 10:12:39 -0500 | [diff] [blame] | 241 | u8 *pixis_base = (u8 *)PIXIS_BASE; |
| 242 | |
| 243 | out_8(pixis_base + PIXIS_RST, 0); |
Peter Tyser | 6945440 | 2009-02-05 11:25:25 -0600 | [diff] [blame] | 244 | |
| 245 | while (1) |
| 246 | ; |
| 247 | } |