| Nathan Barrett-Morrison | a215cfc | 2024-04-24 20:04:00 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
| 2 | /* |
| 3 | * (C) Copyright 2022 - Analog Devices, Inc. |
| 4 | * |
| 5 | * Written and/or maintained by Timesys Corporation |
| 6 | * |
| 7 | * Contact: Nathan Barrett-Morrison <nathan.morrison@timesys.com> |
| 8 | * Contact: Greg Malysa <greg.malysa@timesys.com> |
| 9 | */ |
| 10 | |
| 11 | #ifndef MT41K128M16JT_H |
| 12 | #define MT41K128M16JT_H |
| 13 | |
| 14 | /* Default DDR3 part assumed: MT41K128M16JT-125, 2Gb part */ |
| 15 | /* For DCLK= 450 MHz */ |
| 16 | #define DMC_DLLCALRDCNT 72 |
| 17 | #define DMC_DATACYC 9 |
| 18 | #define DMC_TRCD 6 |
| 19 | #define DMC_TWTR 4 |
| 20 | #define DMC_TRP 6 |
| 21 | #define DMC_TRAS 17 |
| 22 | #define DMC_TRC 23 |
| 23 | #define DMC_TMRD 4 |
| 24 | #define DMC_TREF 3510 |
| 25 | #define DMC_TRFC 72 |
| 26 | #define DMC_TRRD 4 |
| 27 | #define DMC_TFAW 17 |
| 28 | #define DMC_TRTP 4 |
| 29 | #define DMC_TWR 7 |
| 30 | #define DMC_TXP 4 |
| 31 | #define DMC_TCKE 3 |
| 32 | #define DMC_CL0 0 |
| 33 | #define DMC_CL123 3 |
| 34 | #define DMC_WRRECOV (DMC_TWR - 1) |
| 35 | #define DMC_MR1_DLLEN 0 |
| 36 | #define DMC_MR1_DIC0 1 |
| 37 | #define DMC_MR1_RTT0 1 |
| 38 | #define DMC_MR1_AL 0 |
| 39 | #define DMC_MR1_DIC1 0 |
| 40 | #define DMC_MR1_RTT1 0 |
| 41 | #define DMC_MR1_WL 0 |
| 42 | #define DMC_MR1_RTT2 0 |
| 43 | #define DMC_MR1_TDQS 0 |
| 44 | #define DMC_MR1_QOFF 0 |
| 45 | #define DMC_WL 1 |
| 46 | #define DMC_RDTOWR 2 |
| 47 | #define DMC_CTL_AL_EN 0 |
| 48 | #define SDR_CHIP_SIZE ENUM_DMC_CFG_SDRSIZE2G |
| 49 | |
| 50 | #endif |