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Gaurav Jain81113a02022-03-24 11:50:27 +05301// SPDX-License-Identifier: GPL-2.0-or-later
Peng Fanc47e09d2019-12-30 17:46:21 +08002/*
Gaurav Jain81113a02022-03-24 11:50:27 +05303 * Copyright 2018-2019, 2021 NXP
Peng Fanc47e09d2019-12-30 17:46:21 +08004 *
Peng Fanc47e09d2019-12-30 17:46:21 +08005 */
6
7#include <common.h>
Simon Glassf11478f2019-12-28 10:45:07 -07008#include <hang.h>
Simon Glass97589732020-05-10 11:40:02 -06009#include <init.h>
Simon Glass0f2af882020-05-10 11:40:05 -060010#include <log.h>
Peng Fanc47e09d2019-12-30 17:46:21 +080011#include <spl.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060012#include <asm/global_data.h>
Peng Fana2608a12021-03-19 15:57:03 +080013#include <asm/arch/clock.h>
Peng Fanc47e09d2019-12-30 17:46:21 +080014#include <asm/arch/imx8mp_pins.h>
15#include <asm/arch/sys_proto.h>
16#include <asm/mach-imx/boot_mode.h>
Peng Fanc47e09d2019-12-30 17:46:21 +080017#include <asm/mach-imx/gpio.h>
Peng Fana2608a12021-03-19 15:57:03 +080018#include <asm/mach-imx/iomux-v3.h>
Peng Fanc47e09d2019-12-30 17:46:21 +080019#include <asm/mach-imx/mxc_i2c.h>
Peng Fanc47e09d2019-12-30 17:46:21 +080020#include <asm/arch/ddr.h>
Peng Fana2608a12021-03-19 15:57:03 +080021#include <power/pmic.h>
22#include <power/pca9450.h>
Gaurav Jain81113a02022-03-24 11:50:27 +053023#include <dm/uclass.h>
24#include <dm/device.h>
Peng Fanc47e09d2019-12-30 17:46:21 +080025
Peng Fanc47e09d2019-12-30 17:46:21 +080026DECLARE_GLOBAL_DATA_PTR;
27
28int spl_board_boot_device(enum boot_device boot_dev_spl)
29{
30 return BOOT_DEVICE_BOOTROM;
31}
32
33void spl_dram_init(void)
34{
35 ddr_init(&dram_timing);
36}
37
38void spl_board_init(void)
39{
Gaurav Jain81113a02022-03-24 11:50:27 +053040 if (IS_ENABLED(CONFIG_FSL_CAAM)) {
41 struct udevice *dev;
42 int ret;
43
44 ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
45 if (ret)
Ye Liec346892022-05-11 13:56:20 +053046 printf("Failed to initialize caam_jr: %d\n", ret);
Gaurav Jain81113a02022-03-24 11:50:27 +053047 }
Peng Fancc08e7e2021-03-19 15:57:04 +080048 /*
49 * Set GIC clock to 500Mhz for OD VDD_SOC. Kernel driver does
50 * not allow to change it. Should set the clock after PMIC
51 * setting done. Default is 400Mhz (system_pll1_800m with div = 2)
52 * set by ROM for ND VDD_SOC
53 */
54 clock_enable(CCGR_GIC, 0);
55 clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(5));
56 clock_enable(CCGR_GIC, 1);
57
Peng Fanc47e09d2019-12-30 17:46:21 +080058 puts("Normal Boot\n");
Peng Fanc47e09d2019-12-30 17:46:21 +080059}
60
61#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
62#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
63struct i2c_pads_info i2c_pad_info1 = {
64 .scl = {
65 .i2c_mode = MX8MP_PAD_I2C1_SCL__I2C1_SCL | PC,
66 .gpio_mode = MX8MP_PAD_I2C1_SCL__GPIO5_IO14 | PC,
67 .gp = IMX_GPIO_NR(5, 14),
68 },
69 .sda = {
70 .i2c_mode = MX8MP_PAD_I2C1_SDA__I2C1_SDA | PC,
71 .gpio_mode = MX8MP_PAD_I2C1_SDA__GPIO5_IO15 | PC,
72 .gp = IMX_GPIO_NR(5, 15),
73 },
74};
75
Simon Glass31339412021-08-08 12:20:27 -060076#if CONFIG_IS_ENABLED(POWER_LEGACY)
Peng Fanc47e09d2019-12-30 17:46:21 +080077#define I2C_PMIC 0
78int power_init_board(void)
79{
80 struct pmic *p;
81 int ret;
82
Peng Fanff866412021-03-19 15:57:06 +080083 ret = power_pca9450_init(I2C_PMIC, 0x25);
Peng Fanc47e09d2019-12-30 17:46:21 +080084 if (ret)
85 printf("power init failed");
86 p = pmic_get("PCA9450");
87 pmic_probe(p);
88
89 /* BUCKxOUT_DVS0/1 control BUCK123 output */
90 pmic_reg_write(p, PCA9450_BUCK123_DVS, 0x29);
91
92 /*
93 * increase VDD_SOC to typical value 0.95V before first
94 * DRAM access, set DVS1 to 0.85v for suspend.
95 * Enable DVS control through PMIC_STBY_REQ and
96 * set B1_ENMODE=1 (ON by PMIC_ON_REQ=H)
97 */
haidong.zheng62927832021-03-19 15:57:02 +080098#ifdef CONFIG_IMX8M_VDD_SOC_850MV
99 /* set DVS0 to 0.85v for special case*/
100 pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x14);
101#else
Peng Fanc47e09d2019-12-30 17:46:21 +0800102 pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x1C);
haidong.zheng62927832021-03-19 15:57:02 +0800103#endif
Peng Fanc47e09d2019-12-30 17:46:21 +0800104 pmic_reg_write(p, PCA9450_BUCK1OUT_DVS1, 0x14);
105 pmic_reg_write(p, PCA9450_BUCK1CTRL, 0x59);
106
Peng Fancc08e7e2021-03-19 15:57:04 +0800107 /* Kernel uses OD/OD freq for SOC */
108 /* To avoid timing risk from SOC to ARM,increase VDD_ARM to OD voltage 0.95v */
109 pmic_reg_write(p, PCA9450_BUCK2OUT_DVS0, 0x1C);
110
Peng Fanc47e09d2019-12-30 17:46:21 +0800111 /* set WDOG_B_CFG to cold reset */
112 pmic_reg_write(p, PCA9450_RESET_CTRL, 0xA1);
113
114 return 0;
115}
116#endif
117
118#ifdef CONFIG_SPL_LOAD_FIT
119int board_fit_config_name_match(const char *name)
120{
121 /* Just empty function now - can't decide what to choose */
122 debug("%s: %s\n", __func__, name);
123
124 return 0;
125}
126#endif
127
Peng Fana50c0a32020-05-26 20:33:49 -0300128/* Do not use BSS area in this phase */
Peng Fanc47e09d2019-12-30 17:46:21 +0800129void board_init_f(ulong dummy)
130{
131 int ret;
132
133 arch_cpu_init();
134
135 init_uart_clk(1);
136
Peng Fan5d93e1c2020-05-26 20:33:48 -0300137 ret = spl_early_init();
Peng Fanc47e09d2019-12-30 17:46:21 +0800138 if (ret) {
139 debug("spl_init() failed: %d\n", ret);
140 hang();
141 }
142
Peng Fan5d93e1c2020-05-26 20:33:48 -0300143 preloader_console_init();
144
Peng Fanc47e09d2019-12-30 17:46:21 +0800145 enable_tzc380();
146
Peng Fanc47e09d2019-12-30 17:46:21 +0800147 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
148
149 power_init_board();
150
151 /* DDR initialization */
152 spl_dram_init();
Peng Fanc47e09d2019-12-30 17:46:21 +0800153}